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Applied Sciences
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Advanced Circuits and Systems for Emerging Applications
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Advanced Circuits and Systems for Emerging Applications

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Electrical, Electronics and Communications Engineering".

Deadline for manuscript submissions: closed (20 August 2023) | Viewed by 12345

Special Issue Editors

Prof. Dr. Hui Zhang

E-Mail Website
Guest Editor
School of Integrated Circuit Science and Engineering, Beihang University, Beijing 100191, China
Interests: Internet of Things communication chips
Prof. Dr. Tianxiao Nie

E-Mail Website
Guest Editor
School of Integrated Circuit Science and Engineering, Beihang University, Beijing 100191, China
Interests: spintronic terahertz; topological insulator; vdW 2D ferromagnet
Dr. Lianbo Wu

E-Mail Website
Guest Editor
School of Integrated Circuit Science and Engineering, Beihang University, Beijing 100191, China
Interests: PLL; wireless communication; biomedical

Special Issue Information

Dear Colleagues,

This year celebrates the 75th anniversary of the invention of the first transistor. With the unending evolution of semiconductor technologies and unceasing developments of new applications, integrated circuits and systems have been part of nearly all aspects of our daily lives. Increasingly stringent specifications are imposed on the speed, power consumption, compactness, and cost of the circuits and systems in order to fulfill the new challenges brought by emerging applications such as smart biosensing systems, advanced communications, innovative medical imaging, as well as novel memory and computing architectures. This Special Issue intends to present new ideas and experimental results in the field of advanced circuits and systems for emerging applications, from theory, design, and experiments to practical uses. Areas relevant to this field include, but are not limited to, innovative integrated circuits, systems, and algorithms.

This Special Issue will publish unpublished, high-quality original research papers in the overlapping fields of:

  • Innovative analog and mixed-signal circuits (sensor interfaces, amplifiers, oscillators, power management units, data converters, etc.).
  • Advanced RF circuits and wireless/wireline architectures (building blocks and solutions at RF, mm-wave and THz frequencies for receivers, transmitters, frequency synthesizers, RF filters, SoCs, and SiPs, etc.).
  • Emerging circuits for digital-intensive systems (e.g., microprocessors), machine learning and AI, MEMS, image sensors and memory.
  • Systems and demonstrations with the aforementioned circuits and systems.

Prof. Dr. Hui Zhang
Prof. Dr. Tianxiao Nie
Dr. Lianbo Wu
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Applied Sciences is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • RFIC
  • mixed-signal IC
  • mm-wave circuits
  • emerging applications
  • brain-computer interface
  • in-memory computing
  • advanced communications

Published Papers (7 papers)

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Research

12 pages, 6474 KiB  
Article
A Self-Calibration of Capacitor Mismatch Error for Pipeline ADCs
by Dong-Hwan Seo, Sunghoon Cho, Jung-Gyun Kim and Byung-Geun Lee
Appl. Sci. 2023, 13(22), 12322; https://doi.org/10.3390/app132212322 - 14 Nov 2023
Viewed by 635
Abstract
This study proposes self-calibration of capacitor mismatch errors for high-resolution pipeline analog-to-digital converters (ADCs). The proposed calibration circuit recursively amplifies the capacitor mismatch error by re-utilizing a multiplying digital-to-analog converter in a pipeline stage without increasing the circuit complexity, and the amplified error [...] Read more.
This study proposes self-calibration of capacitor mismatch errors for high-resolution pipeline analog-to-digital converters (ADCs). The proposed calibration circuit recursively amplifies the capacitor mismatch error by re-utilizing a multiplying digital-to-analog converter in a pipeline stage without increasing the circuit complexity, and the amplified error voltage is converted into digital code by utilizing the remaining pipeline stages. Error correction is performed by subtracting the digital code from the ADC output during normal operation. A prototype of a 12-bit pipeline ADC is fabricated in a 0.18 µm standard CMOS process. The ADC comprises eight 1.5-bit stages, followed by a 4-bit flash ADC as the final stage; the capacitor mismatch errors in the first two pipeline stages are corrected by utilizing the proposed self-calibration technique. Although the calibration method is employed in a 1.5-bit stage architecture, which uses a gain-of-two switched-capacitor amplifier, it is applicable to different bit-per-stage architectures. The ADC linearity significantly improves after calibration, and this is verified through simulations and measurements. Full article
(This article belongs to the Special Issue Advanced Circuits and Systems for Emerging Applications)
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24 pages, 11109 KiB  
Article
A Fully Integrated High Efficiency 2.4 GHz CMOS Power Amplifier with Mode Switching Scheme for WLAN Applications
by Haoyu Shen, Taishan Mo and Bin Wu
Appl. Sci. 2023, 13(13), 7410; https://doi.org/10.3390/app13137410 - 22 Jun 2023
Cited by 1 | Viewed by 1422
Abstract
A 3.3 V mode-switching RF CMOS power amplifier (PA) for WLAN applications is presented, which is integrated into a 55-nm bulk CMOS process. The proposed PA offers both static control and dynamic power control, allowing it to operate efficiently in both low-power and [...] Read more.
A 3.3 V mode-switching RF CMOS power amplifier (PA) for WLAN applications is presented, which is integrated into a 55-nm bulk CMOS process. The proposed PA offers both static control and dynamic power control, allowing it to operate efficiently in both low-power and high-power modes. The pure low-power mode is achieved by reducing power cells, which are also used for linearization in high power mode. The low-power mode is achieved by reducing the number of power cells which are also used for linearization in the high-power mode. In the dynamic power control mode, the total AM–AM and AM–PM distortion is effectively compensated for by dynamically controlling the number of power cells and adjusting the matching input. The proposed PA achieves an output P1dB of 27.6 dBm with a PAE of 32.7% and an output P1dB of 17.7 dBm with a PAE of 10% in high-power and low-power modes, respectively. It is measured with an 802.11 n 64-quadrature-amplitude-modulation (MCS7) signal and shows a maximum average power of 19 dBm under an error-vector-magnitude (EVM) of −27 dB. Full article
(This article belongs to the Special Issue Advanced Circuits and Systems for Emerging Applications)
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16 pages, 6078 KiB  
Article
A 200-MS/s 10-Bit SAR ADC Applied in WLAN Systems
by Yu Zhang, Yilin Pu, Bin Wu, Taishan Mo and Tianchun Ye
Appl. Sci. 2023, 13(12), 7040; https://doi.org/10.3390/app13127040 - 12 Jun 2023
Viewed by 1305
Abstract
This paper introduces a new high-performance successive approximation register (SAR) analog-to-digital converter (ADC) designed for high-speed and low-power wireless local area network (WLAN) applications using a SMIC 55 nm 1p8m CMOS process. The design employs several innovative techniques, including an improved bootstrap switch [...] Read more.
This paper introduces a new high-performance successive approximation register (SAR) analog-to-digital converter (ADC) designed for high-speed and low-power wireless local area network (WLAN) applications using a SMIC 55 nm 1p8m CMOS process. The design employs several innovative techniques, including an improved bootstrap switch with high linearity, a 4-reference voltage method to minimize capacitive digital-to-analog converter (CDAC) mismatch, a kickback-canceling comparator to eliminate kick-back noise, and redundant design-assisted window-opening SAR logic to decrease conversion time. Experimental results reveal that the proposed ADC achieves an impressive signal-to-noise and distortion ratio (SNDR) of 55.3 dB and a spurious-free dynamic range (SFDR) of 66.6 dB at a sampling rate of 200 MHz with Nyquist frequency input while consuming a power of 2.8 mW at a 1.2 V power supply. This corresponds to a figure-of-merit (FoM) value of 29 fJ/conversion-step. Thanks to the incorporation of the 4-reference voltage method, the ADC demonstrates a significant area advantage compared to other designs with similar FOM values utilizing more advanced processes, occupying a mere 0.008 mm2 of core area. Full article
(This article belongs to the Special Issue Advanced Circuits and Systems for Emerging Applications)
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23 pages, 2523 KiB  
Article
Graded Evaluation of Health Status of Hydraulic System with Variable Operating Conditions Based on Parameter Identification
by Fengqin Lin, Qingxiang Zhang, Peng Yu and Jin Guo
Appl. Sci. 2023, 13(10), 6052; https://doi.org/10.3390/app13106052 - 15 May 2023
Cited by 1 | Viewed by 981
Abstract
In industrial production, the effective and reliable performance of hydraulic systems is closely associated with product quality, personal safety, economic efficiency, etc. It is of utmost significance to perform the health status evaluation of systems. In this paper, a least-squares recursive parameter identification [...] Read more.
In industrial production, the effective and reliable performance of hydraulic systems is closely associated with product quality, personal safety, economic efficiency, etc. It is of utmost significance to perform the health status evaluation of systems. In this paper, a least-squares recursive parameter identification algorithm is proposed to realize the graded evaluation of the health status of the hydraulic system under variable operating conditions. First, a nonlinear model of the hydraulic system is established based on a mechanism analysis. Based on the system identifiable model obtained by parameter linearization, the least squares recursive algorithm is used to get the system parameters. Second, the system measurable data are graded and labeled under the same operating condition, and the variable parameter ranges under different health states are obtained by the parameter identification algorithm. Finally, under variable operating conditions, the estimates of variable parameters are compared with the range of health state parameters to complete the system health state graded evaluation. The feasibility of the proposed evaluation method is verified by MATLAB simulation software. Full article
(This article belongs to the Special Issue Advanced Circuits and Systems for Emerging Applications)
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17 pages, 6368 KiB  
Article
A Low Phase Noise Crystal Oscillator with a Fast Start-Up Bandgap Reference for WLAN Applications
by Peng Wu, Peng Li, Xi Chen, Peng Cheng and Jian Zhu
Appl. Sci. 2023, 13(9), 5652; https://doi.org/10.3390/app13095652 - 4 May 2023
Viewed by 2334
Abstract
This article presents the design and implementation of a 40 MHz crystal oscillator (XO) with low phase noise, based on the 55 nm CMOS process, for wireless transceiver systems, particularly those used in Wireless Local Area Network (WLAN). The proposed design employs a [...] Read more.
This article presents the design and implementation of a 40 MHz crystal oscillator (XO) with low phase noise, based on the 55 nm CMOS process, for wireless transceiver systems, particularly those used in Wireless Local Area Network (WLAN). The proposed design employs a bandgap reference circuit that includes a start-up circuit and a low-voltage common-source common-gate current mirror, which ensures that the bandgap reference circuit is powered up effectively across all temperatures and process corners. A low-pass filter is also incorporated at the low dropout regulator (LDO) input to reduce the phase noise of the XO circuit. The experimental results demonstrate that the proposed design achieves a final phase noise of −164.36 dBc/Hz at 100 kHz offset frequency, with a power consumption of 0.444 mW. The test of start-up time is 0.718 ms and the compact chip area is 0.088 mm2. According to the simulation and test results, the final FOM value calculated in this paper is 209.93 dBc/Hz at 100 kHz offset. Full article
(This article belongs to the Special Issue Advanced Circuits and Systems for Emerging Applications)
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13 pages, 1850 KiB  
Article
All-Digital Computing-in-Memory Macro Supporting FP64-Based Fused Multiply-Add Operation
by Dejian Li, Kefan Mo, Liang Liu, Biao Pan, Weili Li, Wang Kang and Lei Li
Appl. Sci. 2023, 13(7), 4085; https://doi.org/10.3390/app13074085 - 23 Mar 2023
Viewed by 2018
Abstract
Recently, frequent data movement between computing units and memory during floating-point arithmetic has become a major problem for scientific computing. Computing-in-memory (CIM) is a novel computing paradigm that merges computing logic into memory, which can address the data movement problem with excellent power [...] Read more.
Recently, frequent data movement between computing units and memory during floating-point arithmetic has become a major problem for scientific computing. Computing-in-memory (CIM) is a novel computing paradigm that merges computing logic into memory, which can address the data movement problem with excellent power efficiency. However, the previous CIM paradigm failed to support double-precision floating-point format (FP64) due to its computing complexity. This paper presents a novel all-digital CIM macro-DCIM-FF to complete FP64 based fused multiply-add (FMA) operation for the first time. With 16 sub-CIM cells integrating digital multipliers to complete mantissa multiplication, DCIM-FF is able to provide correct rounded implementations for normalized/denormalized inputs in round-to-nearest-even mode and round-to-zero mode, respectively. To evaluate our design, we synthesized and tested the DCIM-FF macro in 55-nm CMOS technology. With a minimum power efficiency of 0.12 mW and a maximum computing efficiency of 26.9 TOPS/W, we successfully demonstrated that DCIM-FF can run the FP64-based FMA operation without error. Compared to related works, the proposed DCIM-FF macro shows significant power efficiency improvement and less area overhead based on CIM technology. This work paves a novel pathway for high-performance implementation of an FP64-based matrix-vector multiplication (MVM) operation, which is essential for hyperscale scientific computing. Full article
(This article belongs to the Special Issue Advanced Circuits and Systems for Emerging Applications)
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17 pages, 5294 KiB  
Article
Free Space Optical Communication Networking Technology Based on a Laser Relay Station
by Changchun Ding, Chengming Li, Ziming Wang, Zhen Gao, Zijian Liu, Junfeng Song and Min Tao
Appl. Sci. 2023, 13(4), 2567; https://doi.org/10.3390/app13042567 - 16 Feb 2023
Cited by 1 | Viewed by 2910
Abstract
Optical communication modulation technology and networking technology are two important technologies for constructing free-space optical (FSO) communication. In this paper, pulse width modulation (PWM) is used to realize free-space optical communication. The process of signal modulation and demodulation is implemented by means of [...] Read more.
Optical communication modulation technology and networking technology are two important technologies for constructing free-space optical (FSO) communication. In this paper, pulse width modulation (PWM) is used to realize free-space optical communication. The process of signal modulation and demodulation is implemented by means of a field programmable gate array (FPGA). An optical communication relay system is constructed to realize communication networking. The binary data bits in the communication process are converted into pulse signals of different widths, the data demodulation process is realized by sampling with a high-speed analog-to-digital converter (ADC), the data level is determined by counting the proportion of high and low voltages sampled in a pulse period. The relay system analyzes the routing target after receiving the pulse signal from the transmitter, and then sends the data to the target receiver. The experimental results show that the constructed system can achieve point-to-multipoint free-space optical communication. Additionally, using ADC to demodulate the received signal increases the stability of the free-space optical communication system. This system provides the design prototype system of FSO communication networking technology. Full article
(This article belongs to the Special Issue Advanced Circuits and Systems for Emerging Applications)
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