Feature Papers in Semiconductor Devices

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Semiconductor Devices".

Deadline for manuscript submissions: 31 August 2024 | Viewed by 10334

Special Issue Editors


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Guest Editor
Institute of Microelectronics, Electromagnetism and Photonics (IMEP-LaHC), University of Grenoble-Alpes, CNRS, Grenoble, France
Interests: physics of advanced materials and solid state devices; defect spectroscopy; electrical characterization; oxide/semiconductorinterface; silicon and III-V semiconductor devices; transistor devices; solar energy material; thin film solar cells

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Guest Editor
Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai 200083, China
Interests: III-V semiconductor materials and devices; infrared semiconductors; III-V infrared phtodetectors; semiconductor lasers

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Guest Editor
School of Electrical Engineering and Computer Science, Gwangju Institute of Science and Technology, Gwangju 61005, Republic of Korea
Interests: compound semiconductor electron devices; THz electronics; solar cells; metamaterials

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Guest Editor
Department of Electronic and Electrical Engineering, The University of Sheffield, Sheffield S1 3JD, UK
Interests: semiconductor materials and devices; photonics; electronics; integration of photonics and electronics; solar energy materials

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Guest Editor
Beijing National Research Center for Information Science and Technology (BNRist), Department of Electronic Engineering, Tsinghua University, Beijing 10084, China
Interests: non-imaging optics; freeform optics; dielectric metasurface optics; III-V semiconductor lasers; distributed feedback lasers (DFB); solid-state lighting devices; LEDs

Special Issue Information

Dear Colleagues,

We are pleased to announce that the Section Semiconductor Devices is compiling a collection of papers submitted by our Section’s Editorial Board members and leading scholars in this field of research. We welcome contributions, in addition torecommendations, from Editorial Board members.

The aim of this Special Issue is to publish a set of papers that characterize the best original articles, including in-depth reviews of the state of the art and original and very up-to-date contributions that involve semiconductor devices. We hope that these articles will be widely read and have a great influence on the field. All articles in this Special Issue will be compiled in a print edition book after the deadline and will be appropriately promoted.

Topics of interest include, but are not limited to, the following:

  • Semiconductor device applications;
  • Fabrication processing;
  • Simulation (theory);
  • Quantum devices;
  • Hybrid electronic and semiconductor devices;
  • Semiconductor devices for energy;
  • Flexible devices;
  • Semiconductor material and device physics;
  • Novel semiconductors;
  • 2D materials for devices;
  • New technology for semiconductor devices;
  • Semiconductor optoelectronic and photonic devices and processing.

Dr. Frédérique Ducroquet
Prof. Dr. Yi Gu
Prof. Dr. Jae-Hyung Jang
Prof. Dr. Tao Wang
Dr. Hongtao Li
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (13 papers)

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Research

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10 pages, 3346 KiB  
Article
Correlation between CO2 Sensitivity and Channel-Layer Thickness in In2O3 Thin-Film Transistor Gas Sensors
by Ayumu Nodera, Ryota Kobayashi, Tsubasa Kobayashi and Shinya Aikawa
Electronics 2024, 13(10), 1947; https://doi.org/10.3390/electronics13101947 - 16 May 2024
Viewed by 304
Abstract
CO2 monitoring is important for achieving net-zero emissions. Here, we report on a CO2 gas sensor based on an In2O3 thin-film transistor (TFT), which is expected to realize both low-temperature operation and high sensitivity. The effect of channel [...] Read more.
CO2 monitoring is important for achieving net-zero emissions. Here, we report on a CO2 gas sensor based on an In2O3 thin-film transistor (TFT), which is expected to realize both low-temperature operation and high sensitivity. The effect of channel thickness on TFT performance is well known; however, its effect on CO2 sensitivity has not been fully investigated. We fabricated In2O3 TFTs of various thicknesses to evaluate the effect of channel thickness on CO2 sensitivity. Consequently, TFT gas sensors with thinner channels exhibited higher CO2 sensitivity. This is because the surface effect is more prominent for a thinner film, suggesting that charge transfer between gas molecules and the channel surface through gas adsorption has a significant impact on changes in the TFT parameters in the subthreshold region. The results showed that the In2O3 TFT in thin channels is a promising candidate for CO2-sensitive TFT gas sensors and is useful for understanding an effect of gas adsorption in oxide TFTs with a very thin channel as well. Full article
(This article belongs to the Special Issue Feature Papers in Semiconductor Devices)
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13 pages, 8119 KiB  
Article
PSP-Equivalent Model for Double-Gate and Surrounding-Gate Field Effect Transistors for Circuit Simulation
by Luigi Colalongo, Simone Comensoli and Anna Richelli
Electronics 2024, 13(9), 1725; https://doi.org/10.3390/electronics13091725 - 30 Apr 2024
Viewed by 359
Abstract
We introduce a compact core model for double-gate (DGFET) and surrounding-gate (SGFET) MOSFETs designed for circuit simulations. Despite its high precision, the model is crafted to retain the same analytic formulation of the industry standard Pennsylvania State and Philips (PSP). Instead of linearizing [...] Read more.
We introduce a compact core model for double-gate (DGFET) and surrounding-gate (SGFET) MOSFETs designed for circuit simulations. Despite its high precision, the model is crafted to retain the same analytic formulation of the industry standard Pennsylvania State and Philips (PSP). Instead of linearizing the drain current as in the PSP model, we employ a quadratic symmetric polynomial interpolation of the charge in the channel. This eliminates the need for cumbersome derivatives, simplifications, and intricate coding when integrating into a circuit simulator, thereby preventing singularities during numerical iterations. Moreover, thanks to its mathematical formulation equivalent to PSP, this model simplifies the coding of terminal charges, capacitances, potentials, and electric fields in the channel within circuit simulators. We validate the accuracy of the model through comparisons with numerical solutions and experiments from the literature. Full article
(This article belongs to the Special Issue Feature Papers in Semiconductor Devices)
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10 pages, 3246 KiB  
Article
Effect of In-Situ H Doping on the Electrical Properties of In2O3 Thin-Film Transistors
by Peixuan Hu, Zhixiang Gao, Lu Yang, Wanfa Li, Xiaohan Liu, Ting Li, Yujia Qian, Lingyan Liang, Yufang Hu and Hongtao Cao
Electronics 2024, 13(8), 1478; https://doi.org/10.3390/electronics13081478 - 13 Apr 2024
Viewed by 514
Abstract
In this article, this research demonstrates the influence of in-situ introduction of H2 into the working gas on the physical properties of post-annealed In2O3 thin films and the performance of associated devices. A gradual increase in the H2 [...] Read more.
In this article, this research demonstrates the influence of in-situ introduction of H2 into the working gas on the physical properties of post-annealed In2O3 thin films and the performance of associated devices. A gradual increase in the H2 ratio leads to improved film quality, as indicated by spectroscopic ellipsometry, X-ray photoelectron spectroscopy, and atomic force microscope analyses showing a reduction in defect states such as band-tail states and VO in the film, and a smoother surface morphology with the root mean square roughness approximately 0.446 nm. Furthermore, this hydrogen doping effect results in a distinct shift in the device’s threshold voltage toward the positive direction, and an improvement in the field-effect mobility and subthreshold swing. Consequently, a high-performance In2O3:H TFT is developed, exhibiting a field-effect mobility of 47.8 cm2/Vs, threshold voltage of −4.1 V and subthreshold swing of 0.25 V/dec. These findings highlight the potential of in-situ H doping as a promising approach to regulate In2O3-based TFTs. Full article
(This article belongs to the Special Issue Feature Papers in Semiconductor Devices)
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35 pages, 6168 KiB  
Article
Development of a Wafer Defect Pattern Classifier Using Polar Coordinate System Transformed Inputs and Convolutional Neural Networks
by Moo Hyun Kim and Tae Seon Kim
Electronics 2024, 13(7), 1360; https://doi.org/10.3390/electronics13071360 - 4 Apr 2024
Viewed by 546
Abstract
Defect pattern analysis of wafer bin maps (WBMs) is an important means of identifying process problems. Recently, automated analysis methods using machine learning or deep learning have been studied as alternatives to manual classification by engineers. In this paper, we propose a method [...] Read more.
Defect pattern analysis of wafer bin maps (WBMs) is an important means of identifying process problems. Recently, automated analysis methods using machine learning or deep learning have been studied as alternatives to manual classification by engineers. In this paper, we propose a method to improve the feature extraction performance of defect patterns by transforming the polar coordinate system instead of the existing WBM image input. To reduce the variability of the location representation, defect patterns in the Cartesian coordinate system, where the location of the distributed defect die is not constant, were converted to a polar coordinate system. The CNN classifier, which uses polar coordinate transformed input, achieved a classification accuracy of 91.3%, which is 4.8% better than the existing WBM image-based CNN classifier. Additionally, a tree-structured classifier model that sequentially connects binary classifiers achieved a classification accuracy of 94%. The method proposed in this paper is also applicable to the defect pattern classification of WBMs consisting of different die sizes than the training data. Finally, the paper proposes an automated pattern classification method that uses individual classifiers to learn defect types and then applies ensemble techniques for multiple defect pattern classification. This method is expected to reduce labor, time, and cost and enable objective labeling instead of relying on subjective judgments of engineers. Full article
(This article belongs to the Special Issue Feature Papers in Semiconductor Devices)
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11 pages, 1741 KiB  
Article
A New 3-Dimensional Graphene Vertical Transistor with Channel Length Determination Using Dielectric Thickness
by Jong Kyung Park and Seul Ki Hong
Electronics 2024, 13(7), 1356; https://doi.org/10.3390/electronics13071356 - 3 Apr 2024
Viewed by 507
Abstract
This study introduces a novel three-dimensional (3D) vertical field-effect transistor (FET) structure that utilizes two-dimensional (2D) graphene as the channel, with channel length controlled by deposited dielectric thickness. The dielectric deposition process allows for the easier implementation of small-scale features on the order [...] Read more.
This study introduces a novel three-dimensional (3D) vertical field-effect transistor (FET) structure that utilizes two-dimensional (2D) graphene as the channel, with channel length controlled by deposited dielectric thickness. The dielectric deposition process allows for the easier implementation of small-scale features on the order of nanometers compared to traditional patterning processes. Incorporating 3D vertical structures with 2D channel materials enhances device performance beyond conventional planar designs. The fabrication process involves direct graphene growth for the channel and nanometer-scale dielectric deposition for the facile adjustment of channel length. The experimental results validate successful graphene formation and transistor operation, as evidenced by current–voltage characteristics. The 3D Vertical FET holds promise for improved device integration and overall system performance due to its unique device structure and an effective short-channel implementation method. This research underscores the potential of 2D materials in advancing transistor technology, and presents a practical approach for increasing device density and enhancing performance in semiconductor production processes. Full article
(This article belongs to the Special Issue Feature Papers in Semiconductor Devices)
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13 pages, 2559 KiB  
Article
Effects of Diffusion Barrier Layers on the Performance of Lattice-Mismatched Metamorphic In0.83Ga0.17As Photodetectors
by Zhejing Jiao, Tianyu Guo, Gaoyu Zhou, Yi Gu, Bowen Liu, Yizhen Yu, Chunlei Yu, Yingjie Ma, Tao Li and Xue Li
Electronics 2024, 13(7), 1339; https://doi.org/10.3390/electronics13071339 - 2 Apr 2024
Viewed by 569
Abstract
In the planar-type InGaAs photodetector (PD) structure, a diffusion barrier has the effect of modifying the zinc diffusion profile in the interface between the cap and the absorption layer to improve device performance. In this work, an n-type In0.83Ga0.17As [...] Read more.
In the planar-type InGaAs photodetector (PD) structure, a diffusion barrier has the effect of modifying the zinc diffusion profile in the interface between the cap and the absorption layer to improve device performance. In this work, an n-type In0.83Ga0.17As diffusion barrier layer (DBL) is employed between the In0.83Al0.17As cap layer and the low-doped In0.83Ga0.17As absorption layer of a lattice-mismatched metamorphic In0.83Ga0.17As PD. The device performance of the In0.83Ga0.17As PDs in terms of dark current, quantum efficiency, and capacitance were simulated and compared to experimental results. The effects of the thickness and doping concentration of the DBL on PD performance were analyzed and shown to be optimized at both 300 K and 200 K. Based on the simulation results, the electron concentration of the DBL is recommended to be 3×10165×1016 cm−3 and a thickness of 0.1 μm is suggested. Full article
(This article belongs to the Special Issue Feature Papers in Semiconductor Devices)
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15 pages, 3914 KiB  
Article
Physical Insights into THz Rectification in Metal–Oxide–Semiconductor Transistors
by Fabrizio Palma
Electronics 2024, 13(7), 1192; https://doi.org/10.3390/electronics13071192 - 25 Mar 2024
Viewed by 449
Abstract
Metal–oxide–semiconductor field-effect transistors (MOSFETs) have proven to be effective devices for rectifying electromagnetic radiation at extremely high frequencies, approximately 1 THz. This paper presents a new interpretation of the THz rectification process in the structure of an MOS transistor. The rectification depends on [...] Read more.
Metal–oxide–semiconductor field-effect transistors (MOSFETs) have proven to be effective devices for rectifying electromagnetic radiation at extremely high frequencies, approximately 1 THz. This paper presents a new interpretation of the THz rectification process in the structure of an MOS transistor. The rectification depends on the nonlinear effect of the carrier dynamics. The paper shows that the so-called self-mixing effect occurs within the interface region between the source and the channel. The basic tool used numerical TCAD simulations, which offer a direct interpretation of different aspects of this interaction. The complex, 2D effect is examined in terms of its basic aspects by comparing the MOS structure with a simplified case study structure. We demonstrate that a contribution to the output-rectified voltage detectable at the drain arises from the charging of the drain well capacitance due to the diffusion of excess electrons from the self-mixing interaction occurring at the source barrier. In addition, the paper provides a quantitative description of the rectification process through the definition of the output equivalent circuit, offering a new perspective for the design of detection systems. Full article
(This article belongs to the Special Issue Feature Papers in Semiconductor Devices)
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11 pages, 5690 KiB  
Article
Ballistic Performance of Quasi-One-Dimensional Hafnium Disulfide Field-Effect Transistors
by Mislav Matić and Mirko Poljak
Electronics 2024, 13(6), 1048; https://doi.org/10.3390/electronics13061048 - 11 Mar 2024
Viewed by 669
Abstract
Hafnium disulfide (HfS2) monolayer is one of the most promising two-dimensional (2D) materials for future nanoscale electronic devices, and patterning it into quasi-one-dimensional HfS2 nanoribbons (HfS2NRs) enables multi-channel architectures for field-effect transistors (FETs). Electronic, transport and ballistic device characteristics [...] Read more.
Hafnium disulfide (HfS2) monolayer is one of the most promising two-dimensional (2D) materials for future nanoscale electronic devices, and patterning it into quasi-one-dimensional HfS2 nanoribbons (HfS2NRs) enables multi-channel architectures for field-effect transistors (FETs). Electronic, transport and ballistic device characteristics are studied for sub-7 nm-wide and ~15 nm-long zigzag HfS2NR FETs using non-equilibrium Green’s functions (NEGF) formalism with density functional theory (DFT) and maximally localized Wannier functions (MLWFs). We provide an in-depth analysis of quantum confinement effects on ON-state performance. We show that bandgap and hole transport mass are immune to downscaling effects, while the ON-state performance is boosted by up to 53% but only in n-type devices. Finally, we demonstrate that HfS2NR FETs can fulfill the industry requirements for future technology nodes, which makes them a promising solution for FET architectures based on multiple nanosheets or nanowires. Full article
(This article belongs to the Special Issue Feature Papers in Semiconductor Devices)
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11 pages, 3409 KiB  
Article
Optimizing Confined Nitride Trap Layers for Improved Z-Interference in 3D NAND Flash Memory
by Yeeun Kim, Seul Ki Hong and Jong Kyung Park
Electronics 2024, 13(6), 1020; https://doi.org/10.3390/electronics13061020 - 8 Mar 2024
Viewed by 670
Abstract
This paper presents an innovative approach to alleviate Z-interference in 3D NAND flash memory by proposing an optimized confined nitride trap layer structure. Z-interference poses a significant challenge in 3D NAND flash memory, especially with the reduction in cell spacing to accommodate an [...] Read more.
This paper presents an innovative approach to alleviate Z-interference in 3D NAND flash memory by proposing an optimized confined nitride trap layer structure. Z-interference poses a significant challenge in 3D NAND flash memory, especially with the reduction in cell spacing to accommodate an increased number of vertically stacked 3D NAND flash memories. While the confined nitride trap layer device designed for complete isolation of the trapping layer in three dimensions effectively reduces Z-interference, the results showed substantial variations based on the confined structure. To clarify this issue, we compared three distinct confined nitride trap layer structures and investigated their impact on Z-interference. Our findings indicate that the rectangle structure exhibited the most significant mitigation, implying that differences in the electric field applied to the poly silicon channel, which is influenced by the structure, and the increase in effective channel length are effective strategies for alleviating Z-interference. The proposed structure undergoes a comprehensive examination through technology computer-aided design (TCAD) simulations. Additionally, we introduce a practical process flow designed to minimize Z-interference. Full article
(This article belongs to the Special Issue Feature Papers in Semiconductor Devices)
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14 pages, 3756 KiB  
Article
Enhancement of the Synaptic Performance of Phosphorus-Enriched, Electric Double-Layer, Thin-Film Transistors
by Dong-Gyun Mah, Hamin Park and Won-Ju Cho
Electronics 2024, 13(4), 737; https://doi.org/10.3390/electronics13040737 - 11 Feb 2024
Viewed by 840
Abstract
The primary objective of neuromorphic electronic devices is the implementation of neural networks that replicate the memory and learning functions of biological synapses. To exploit the advantages of electrolyte gate synaptic transistors operating like biological synapses, we engineered electric double-layer transistors (EDLTs) using [...] Read more.
The primary objective of neuromorphic electronic devices is the implementation of neural networks that replicate the memory and learning functions of biological synapses. To exploit the advantages of electrolyte gate synaptic transistors operating like biological synapses, we engineered electric double-layer transistors (EDLTs) using phosphorus-doped silicate glass (PSG). To investigate the effects of phosphorus on the EDL and synaptic behavior, undoped silicate spin-on-glass-based transistors were fabricated as a control group. Initially, we measured the frequency-dependent capacitance and double-sweep transfer curves for the metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors. Subsequently, we analyzed the excitatory post-synaptic currents (EPSCs), including pre-synaptic single spikes, double spikes, and frequency variations. The capacitance and hysteresis window characteristics of the PSG for synaptic operations were verified. To assess the specific synaptic operational characteristics of PSG-EDLTs, we examined EPSCs based on the spike number and established synaptic weights in potentiation and depression (P/D) in relation to pre-synaptic variables. Normalizing the P/D results, we extracted the parameter values for the nonlinearity factor, asymmetric ratio, and dynamic range based on the pre-synaptic variables, revealing the trade-off relationships among them. Finally, based on artificial neural network simulations, we verified the high-recognition rate of PSG-EDLTs for handwritten digits. These results suggest that phosphorus-based EDLTs are beneficial for implementing high-performance artificial synaptic hardware. Full article
(This article belongs to the Special Issue Feature Papers in Semiconductor Devices)
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15 pages, 4108 KiB  
Article
Nonlinear Dynamics in HfO2/SiO2-Based Interface Dipole Modulation Field-Effect Transistors for Synaptic Applications
by Noriyuki Miyata
Electronics 2024, 13(4), 726; https://doi.org/10.3390/electronics13040726 - 10 Feb 2024
Viewed by 607
Abstract
In the pursuit of energy-efficient spiking neural network (SNN) hardware, synaptic devices leveraging emerging memory technologies hold significant promise. This study investigates the application of the recently proposed HfO2/SiO2-based interface dipole modulation (IDM) memory for synaptic spike timing-dependent plasticity [...] Read more.
In the pursuit of energy-efficient spiking neural network (SNN) hardware, synaptic devices leveraging emerging memory technologies hold significant promise. This study investigates the application of the recently proposed HfO2/SiO2-based interface dipole modulation (IDM) memory for synaptic spike timing-dependent plasticity (STDP) learning. Firstly, through pulse measurements of IDM metal–oxide–semiconductor (MOS) capacitors, we demonstrate that IDM exhibits an inherently nonlinear and near-symmetric response. Secondly, we discuss the drain current response of a field-effect transistor (FET) incorporating a multi-stack IDM structure, revealing its nonlinear and asymmetric pulse response, and suggest that the degree of the asymmetry depends on the modulation current ratio. Thirdly, to emulate synaptic STDP behavior, we implement double-pulse-controlled drain current modulation of IDMFET using a simple bipolar rectangular pulse. Additionally, we propose a double-pulse-controlled synaptic depression that is valuable for optimizing STDP-based unsupervised learning. Integrating the pulse response characteristics of IDMFETs into a two-layer SNN system for synaptic weight updates, we assess training and classification performance on handwritten digits. Our results demonstrate that IDMFET-based synaptic devices can achieve classification accuracy comparable to previously reported simulation-based results. Full article
(This article belongs to the Special Issue Feature Papers in Semiconductor Devices)
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Review

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32 pages, 6902 KiB  
Review
A Brief Review of Single-Event Burnout Failure Mechanisms and Design Tolerances of Silicon Carbide Power MOSFETs
by Christopher A. Grome and Wei Ji
Electronics 2024, 13(8), 1414; https://doi.org/10.3390/electronics13081414 - 9 Apr 2024
Viewed by 1692
Abstract
Radiation hardening of power MOSFETs (metal oxide semiconductor field effect transistors) is of the highest priority for sustaining high-power systems in the space radiation environment. Silicon carbide (SiC)-based power electronics are being investigated as a strong alternative for high power spaceborne power electronic [...] Read more.
Radiation hardening of power MOSFETs (metal oxide semiconductor field effect transistors) is of the highest priority for sustaining high-power systems in the space radiation environment. Silicon carbide (SiC)-based power electronics are being investigated as a strong alternative for high power spaceborne power electronic systems. SiC MOSFETs have been shown to be most prone to single-event burnout (SEB) from space radiation. The current knowledge of SiC MOSFET device degradation and failure mechanisms are reviewed in this paper. Additionally, the viability of radiation tolerant SiC MOSFET designs and the modeling methods of SEB phenomena are evaluated. A merit system is proposed to consider the performance of radiation tolerance and nominal electrical performance. Criteria needed for high-fidelity SEB simulations are also reviewed. This paper stands as a necessary analytical review to intercede the development of radiation-hardened power devices for space and extreme environment applications. Full article
(This article belongs to the Special Issue Feature Papers in Semiconductor Devices)
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19 pages, 4310 KiB  
Review
Paralleling of IGBT Power Semiconductor Devices and Reliability Issues
by Ravi Nath Tripathi and Ichiro Omura
Electronics 2023, 12(18), 3826; https://doi.org/10.3390/electronics12183826 - 10 Sep 2023
Cited by 2 | Viewed by 1762
Abstract
Paralleling of power semiconductor devices is inevitable considering their widespread application and exploitation in the extended horizon of these applications. However, paralleling of power semiconductor devices is prone to severe unbalancing corresponding to the non-idealities of device parameters, which leads to non-identical dynamic [...] Read more.
Paralleling of power semiconductor devices is inevitable considering their widespread application and exploitation in the extended horizon of these applications. However, paralleling of power semiconductor devices is prone to severe unbalancing corresponding to the non-idealities of device parameters, which leads to non-identical dynamic and static characteristics of the power devices, as well as the operating conditions and aging. Therefore, the currents are generally non-uniform and cause the derating of the system. This paper discusses and analyzes issues associated with the paralleling of IGBT power devices, which can evoke serious reliability issues. Furthermore, the paper examines the techniques and methodologies that have been proposed to reduce the issue of current unbalancing of parallel-connected power devices. Full article
(This article belongs to the Special Issue Feature Papers in Semiconductor Devices)
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