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Feature Paper
Article

10 Citations

5,814 Views

22 Pages

Hardware Acceleration for RLNC: A Case Study Based on the Xtensa Processor with the Tensilica Instruction-Set Extension

Javier Acevedo,
Robert Scheffel,
Simon Wunderlich,
Mattis Hasler,
Sreekrishna Pandi,
Juan Cabrera,
Frank H. P. Fitzek,
Gerhard Fettweis and
Martin Reisslein

Electronics2018, 7(9), 180;https://doi.org/10.3390/electronics7090180

8 September 2018

Random linear network coding (RLNC) can greatly aid data transmission in lossy wireless networks. However, RLNC requires computationally complex matrix multiplications and inversions in finite fields (Galois fields). These computations are highly dem...

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Article

8 Citations

4,249 Views

28 Pages

Two-Layer Bus-Independent Instruction Set Architecture for Securing Long Protocol Data Units in Automotive Open System Architecture-Based Automotive Electronic Control Units

Ahmed Hamed,
M. Watheq El-Kharashi,
Ashraf Salem and
Mona Safar

Electronics2022, 11(6), 952;https://doi.org/10.3390/electronics11060952

18 March 2022

In this paper, we propose a bus-independent hardware (HW)-based approach to secure long protocol data units (PDUs) in Automotive Open System Architecture (AUTOSAR)-based automotive electronic control units (ECUs). Our approach is based on extending p...

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Article

1,996 Views

20 Pages

ASIP Performance Enhancement by Hazard Control through Scoreboard

Xinbing Zhou,
Yi Man,
Peng Hao,
Wei Chen,
Bo Yang,
Baoguo Ding and
Dake Liu

Micromachines2024, 15(11), 1287;https://doi.org/10.3390/mi15111287

23 October 2024

The application-specific instruction set processor (ASIP) has been gradually accepted in AI, communication, media, game and industry control. The digital signal processor (DSP) is a typical ASIP, whose benefits include high performance in specific do...

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Article

5 Citations

2,597 Views

30 Pages

ASIPAMPIUM: An Efficient ASIP Generator for Low Power Applications

Alian Engroff,
Marcelo Romanssini,
Lucas Compassi-Severo,
Paulo C. C. de Aguirre and
Alessandro Girardi

Electronics2023, 12(2), 401;https://doi.org/10.3390/electronics12020401

12 January 2023

The adoption of customized ASIPs (Application Specific Instruction Set Processors) in embedded circuits is an important alternative for optimizing power consumption, silicon area, or processing performance according to the design requirements. The pr...

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Article

1 Citations

2,737 Views

25 Pages

An ASIP for Neural Network Inference on Embedded Devices with 99% PE Utilization and 100% Memory Hidden under Low Silicon Cost

Muxuan Gao,
He Chen and
Dake Liu

Sensors2022, 22(10), 3841;https://doi.org/10.3390/s22103841

19 May 2022

The computation efficiency and flexibility of the accelerator hinder deep neural network (DNN) implementation in embedded applications. Although there are many publications on deep neural network (DNN) processors, there is still much room for deep op...

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Article

2 Citations

10,175 Views

39 Pages

CASPER: Embedding Power Estimation and Hardware-Controlled Power Management in a Cycle-Accurate Micro-Architecture Simulation Platform for Many-Core Multi-Threading Heterogeneous Processors

Kushal Datta,
Arindam Mukherjee,
Guangyi Cao,
Rohith Tenneti,
Vinay Vijendra Kumar Lakshmi,
Arun Ravindran and
Bharat S. Joshi

J. Low Power Electron. Appl.2012, 2(1), 30-68;https://doi.org/10.3390/jlpea2010030

1 February 2012

Despite the promising performance improvement observed in emerging many-core architectures in high performance processors, high power consumption prohibitively affects their use and marketability in the low-energy sectors, such as embedded processors...

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