Special Issue "All-Digital Time-Mode Approaches for Mixed Analog-Digital Signal Processing"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (30 September 2018).

Special Issue Editor

Prof. Dr. Fei Yuan
Website
Guest Editor
Department of Electrical and Computer Engineering, Faculty of Engineering and Architectural Science (FEAS) Ryerson University, 350 Victoria Street, Toronto, ON M5B 2K3, Canada
Interests: CMOS integrated circuits and systems for data communications; CMOS time-mode circuits and systems; analog-to-digital converters; and passive wireless microsystems
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Special Issue Information

Dear Colleagues,

The rapid advance of CMOS technology has been geared towards optimizing the performance of digital circuits. As a result, analog circuits not only continue to lose the benefit of specialized and process-controlled components, they must also cope with a rapidly shrinking voltage headroom, deteriorating device mismatch, and worsening linearity while satisfying ever stringent performance specifications. Although the scaling-induced performance degradation of analog circuits can be compensated to a certain degree using digital means, these approaches are not only costly both in terms of silicon area and power consumption, they also negatively impact the performance of compensated analog circuits. Technology scaling, on the other hand, has greatly improved the timing accuracy of digital circuits. As a result, time-mode signal processing where information is represented by the time difference between the occurrence of two digital events rather than the nodal voltages or branch currents of electric networks offer a viable and technology friendly means to combat difficulties encountered in design of mixed analog-digital systems. Time-mode signal processing deals with the addition, subtraction, multiplication, amplification, differentiation, integration, quantization, etc., of time variables. Since information to be processed by time-mode circuits is represented by the time difference between digital signals, these circuits are essentially digital systems capable of performing analog and mixed analog-digital signal processing without using power-greedy and speed-impaired digital signal processors. Time-mode circuits possess a number of intrinsic and attractive characteristics, such as compatibility with technology scaling, programmability, portability, immunity to disturbances and noise, and a short design cycle, to name a few that are not possessed by their analog counterparts. Time-mode approaches have found a broad spectrum of emerging applications in mixed analog-digital systems including vehicle navigation systems, analog-to-digital data converters, finite and infinite impulse response filters, all digital phase-locked loops and frequency synthesizers, and Gbps SerDes, to name a few.

This Special Issue is aimed at presenting the latest research findings in time-mode approaches for mixed analog-digital signal processing. Relevant topics include, but are not limited to, the following:

  • Voltage-to-time converters,
  • Time-to-voltage converters,
  • Time-to-digital converters,
  • Digital-to-time converters,
  • Time-mode arithmetic circuits such as time adders, time differentiators, and time integrators, etc.,
  • Time registers,
  • Time quantizers,
  • Time amplifiers,
  • Time-mode delta-sigma modulators
  • Time-mode SAR analog-to-digital converters
  • Other time-based analog-to-digital converters
  • Time-mode all-digital phase-locked loops
  • Time-mode frequency synthesizers
  • Time-mode FIR and IIR filters
  • Time-mode SerDes
Prof. Fei Yuan
Guest Editor

Manuscript Submission Information

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1500 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Time-mode signal processing
  • time integrators
  • time registers
  • time amplifiers
  • time quantizers
  • time-to-digital converters
  • digital-to-time converters
  • voltage-to-time converters
  • time-mode ADCs
  • all-digital phase-locked loops
  • all-digital frequency synthesizers

Published Papers (6 papers)

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Open AccessArticle
Maximal Q Factor for an On-Chip, Fuse-Based Trimmable Capacitor
Electronics 2019, 8(1), 62; https://doi.org/10.3390/electronics8010062 - 05 Jan 2019
Cited by 1Correction
Abstract
This paper presents a circuit for realising a fuse-programmable capacitor on-chip. The trimming mechanism is implemented using integrated circuit fuses which can be blown in order to lower the resulting equivalent capacitance. However, for integrated circuits, the non-zero fuse resistance for active fuses [...] Read more.
This paper presents a circuit for realising a fuse-programmable capacitor on-chip. The trimming mechanism is implemented using integrated circuit fuses which can be blown in order to lower the resulting equivalent capacitance. However, for integrated circuits, the non-zero fuse resistance for active fuses and finite fuse resistance for blown fuses limit the Q factor of the resulting capacitor. In this work, we present a method on how to arrange the fuses in order to achieve maximal worst-case Q factor for the given circuit topology given the process parameters and requirements on capacitance. We also analyse and discuss the accuracy and limitations of the topology with regard to fuse resistance and parasitic elements such as bond pads. Full article
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Open AccessArticle
Automatic Calibration Method of Channel Mismatches for Wideband TI-ADC System
Electronics 2019, 8(1), 56; https://doi.org/10.3390/electronics8010056 - 04 Jan 2019
Cited by 5
Abstract
Time-interleaved analog-to-digital converter (TI-ADC) technology can increase the sampling rate without changing resolution. But, the dynamic performance of TI-ADC system is seriously deteriorated by channel mismatches. Under the condition of large bandwidth, gain mismatch and timing mismatch vary with the frequency, which cannot [...] Read more.
Time-interleaved analog-to-digital converter (TI-ADC) technology can increase the sampling rate without changing resolution. But, the dynamic performance of TI-ADC system is seriously deteriorated by channel mismatches. Under the condition of large bandwidth, gain mismatch and timing mismatch vary with the frequency, which cannot be regarded as fixed values. To improve the dynamic performance of the TI-ADC system, an automatic calibration method of channel mismatches for wideband TI-ADC system is proposed in this article. Frequency-dependent channel mismatches are estimated by the algorithm based on sine fitting, and compensated by the means based on perfect reconstruction. The entire sampling and calculation process is automated and tedious operation is simplified. A 6.8-GS/s 12-bit wideband TI-ADC system is implemented. This sampling system can achieve SNDR (signal-to-noise and distortion ratio) above 49 dB and SFDR (spurious-free dynamic range) above 57 dB for an input signal from 100 MHz to 3300 MHz. The proposed calibration method improves the SNDR over 10 dB and the SFDR over 15 dB. The dynamic performance of the sampling system is close to that of its sub-ADC. Full article
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Open AccessArticle
More Discussions on Intrinsic Frequency Detection Capability of Full-Rate Linear Phase Detector in Clock and Data Recovery
Electronics 2018, 7(6), 93; https://doi.org/10.3390/electronics7060093 - 08 Jun 2018
Cited by 1
Abstract
The full-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability intrinsically. Previously, this fact has been discovered by researching the phase and frequency characteristics of the combined full-rate linear PD and charge pump (CP) under [...] Read more.
The full-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability intrinsically. Previously, this fact has been discovered by researching the phase and frequency characteristics of the combined full-rate linear PD and charge pump (CP) under the condition that the ratio of the received data frequency (fDATA) and the recovered clock frequency (fCLK) is set as an integer number. In this paper, for completeness of the theory, the phase and frequency characteristics of the combined full-rate linear PD and CP are studied again while the ratio of fDATA and fCLK is set as a general rational number. Additionally, theoretical analyses of the lock-in range and the lock time of the referenceless single-loop clock and data recovery (CDR) including the full-rate linear PD are newly developed and verified. The calculated lock times by the analysis results agree well with the measured lock times from the MATLAB Simulink simulations. Full article
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Open AccessArticle
Phase Difference Measurement Method Based on Progressive Phase Shift
Electronics 2018, 7(6), 86; https://doi.org/10.3390/electronics7060086 - 01 Jun 2018
Cited by 4
Abstract
This paper proposes a method for phase difference measurement based on the principle of progressive phase shift (PPS). A phase difference measurement system based on PPS and implemented in the FPGA chip is proposed and tested. In the realized system, a fully programmable [...] Read more.
This paper proposes a method for phase difference measurement based on the principle of progressive phase shift (PPS). A phase difference measurement system based on PPS and implemented in the FPGA chip is proposed and tested. In the realized system, a fully programmable delay line (PDL) is constructed, which provides accurate and stable delay, benefitting from the feed-back structure of the control module. The control module calibrates the delay according to process, voltage and temperature (PVT) variations. Furthermore, a modified method based on double PPS is incorporated to improve the resolution. The obtained resolution is 25 ps. Moreover, to improve the resolution, the proposed method is implemented on the 20 nm Xilinx Kintex Ultrascale platform, and test results indicate that the obtained measurement error and clock synchronization error is within the range of ±5 ps. Full article
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Open AccessArticle
SystemC/TLM Controller for Efficient NAND Flash Management in Electronic Musical Instruments
Electronics 2018, 7(5), 75; https://doi.org/10.3390/electronics7050075 - 18 May 2018
Cited by 1
Abstract
The design of an efficient memory subsystem is a fundamentally challenging task in the design of electronic equipment. The storage hierarchy chosen for a particular design has a significant impact on the overall performance and cost. Flash memory often contains the boot code, [...] Read more.
The design of an efficient memory subsystem is a fundamentally challenging task in the design of electronic equipment. The storage hierarchy chosen for a particular design has a significant impact on the overall performance and cost. Flash memory often contains the boot code, operating system kernel, device drivers, middleware, and other application-specific software that can result in megabytes of non-volatile stored data. To maximize the performance, data are moved from non-volatile memory to faster SDRAM (synchronous dynamic random-access memory). Non-volatile memory technologies reach a performance level close to that of dynamic RAMs with the additional benefit of persistent data storage. When cost is critical, an approach where the data are managed directly from non-volatile memory can be used. In this case the non-volatile memory subsystem is constantly accessed to retrieve data. The deep understanding of the system architecture is critical to identify any factor that affects memory performance and the resulting system performance; particularly in specific applications with stricter requests like streaming audio when more than one hundred data streams must be handled in a real-time environment and sound must be generated with a total latency of a few milliseconds. This article reports the development of the system-level model of a controller in a SystemC simulation environment capable of optimizing the use of NAND type flash memories for storage and playback of audio samples in real-time music applications, with the aim of reducing the quantity of the system SDRAM memory, thus lowering the cost of the final product, while still providing the most high-fidelity sound experience. Full article
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Open AccessCorrection
Correction: Nilsson, J. et al. Maximal Q Factor for an On-Chip, Fuse-Based Trimmable Capacitor. Electronics 2019, 8, 62
Electronics 2019, 8(6), 688; https://doi.org/10.3390/electronics8060688 - 18 Jun 2019
Abstract
The authors wish to make the following correction to our published paper [...] Full article
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