Maximal Q Factor for an On-Chip, Fuse-Based Trimmable Capacitor

This paper presents a circuit for realising a fuse-programmable capacitor on-chip. The trimming mechanism is implemented using integrated circuit fuses which can be blown in order to lower the resulting equivalent capacitance. However, for integrated circuits, the non-zero fuse resistance for active fuses and finite fuse resistance for blown fuses limit the Q factor of the resulting capacitor. In this work, we present a method on how to arrange the fuses in order to achieve maximal worst-case Q factor for the given circuit topology given the process parameters and requirements on capacitance. We also analyse and discuss the accuracy and limitations of the topology with regard to fuse resistance and parasitic elements such as bond pads.


Introduction
The goal to design resonant circuits for single-chip RF systems has created the need for trimmable [1] IC capacitors.Applications for such circuits exist in the field of wireless transfer of power directly to a single-chip system, where the RF inductor is integrated on the die.Examples of applications include implantable chips in humans for biomedical purposes [2,3], and sensors for condition monitoring of power semiconductors, where a wireless power supply and communication interface provides galvanic isolation from the high-voltage power semiconductors [4,5].
For both examples, the on-chip coils would be optimised based on the properties of the surrounding materials: tissue data [6] in the case for biomedical implants, and power semiconductor module geometry data [5] in the case for sensors for condition monitoring.In these types of application, a capacitor can be used to form a resonant circuit with the receiver on-chip coil, which boosts the voltage induced in the coil.However, for resonant circuits in single-chip systems such as described above, the obtained resonant frequency may deviate from the desired one because of large tolerances in the IC manufacturing process.Obtaining a specific frequency can be important for RF applications for which the frequency must lie within a frequency band which allows sufficient energy to be radiated, for example an ISM band [7].Tunability is also important for applications where many devices must be powered by the same transmitter and thus operate at the same frequency.One way to adjust the resonant frequency is to trim the value of the capacitor in an LC circuit.
As an alternative to relatively costly laser-trimmed [8] IC capacitors, in this paper we discuss how to optimise fuse-based binary-weighted trimmable capacitors in order to maximise their Q factors which in turn will maximise the Q factors for any resonant circuits built from such capacitors.One such circuit could be an LC circuit consisting of an RF receiver coil and a resonant trimmable capacitor used for frequency tuning.The main issue we address is the effect of non-zero and finite resistance for active and blown IC fuses, respectively.
Although the theory presented in this work is valid not only for fuses, but also for semiconductor switches such as MOSFETs, this paper addresses only fuses.This decision is motivated by the fact that for applications which require a wireless power supply, no power source is available to bias a semiconductor into a desired switching state.Furthermore, even if semiconductors were to be used, such as in [9], effects from e.g., parasitic capacitance and temperature-dependent leakage current would still have to be taken into account.
Furthermore, because fuses are one-time programmable, if possible, we recommend using capacitive structures which have good temperature and bias stability such as MIM capacitors [10], which also exhibit high Q factors.In contrast, using MOSFET capacitors would introduce a strong dependence on bias for the resulting capacitance [11].Furthermore, if no power source is available for bias, the MOSFETs would be biased in the region where the capacitance varies the most and the variation in capacitance with voltage would be extremely strong [11], defeating the purpose of trimming.
For biomedical implants, a concern could be that the impedance of an implanted coil would be sensitive to the electromagnetic properties of the surrounding tissue which are only known approximately and may change over time, which in turn would result in a change in resonant frequency.However, the encapsulation of the IC chip can be made comparable in size to the coil diameter, for example a 2 × 2 mm 2 chip with a 1 mm encapsulation.In such a case, the electromagnetic fields generated by the on-chip coil will extend mainly into the encapsulation material (whose electromagnetic properties are known to a high accuracy and do not change) and not into the surrounding tissue.Thus the resonance frequency can be trimmed before implantation and will not change over time.
The paper is organised as follows.In Section 2, we introduce the circuit and discuss how to optimise it for maximum Q factor and in Section 3 we discuss the accuracy of the optimised circuit.In Section 4, we present an example relating the theory to an application and discuss the results.The conclusion is presented in Section 5.

Trimmable Capacitor Bank
Consider the trimmable capacitor bank shown in Figure 1.The circuit comprises one base capacitor, C, in parallel with m binary-weighed trim capacitors, C 0 , C 1 , ..., C m−1 , distributed as C n = C x 2 n .The trim capacitors can be deactivated by blowing their corresponding fuse in {F 0 , F 1 , ..., F m−1 }.The equivalent capacitance, C eq , seen between nodes a and b can be written as where F n is 0 if fuse n is blown and 1 if it is active.From Equation (1), it can be seen that by letting F n represent bit n of an m-bit binary number, C eq can be controlled from C to C + ∆C with the resolution of the smallest trim capacitance, Because ∆C is the sum of all the trim capacitances, it can be written as By solving Equation (2) for C x , we arrive at the following expression: Thus, from the base capacitance, C, and trim capacitance, ∆C, needed for the application, values can be selected for all the capacitors in the circuit of Figure 1.

Finite/Non-Zero Fuse Resistance
For ICs, both the fuse on-resistance, R f, on , and off-resistance, R f, off can be significant.In many process technologies, a unit fuse is available with a fixed on-and off-resistance and for the examples in this work, values of R f, on = 25 Ω and R f, off = 80 kΩ, relevant to a 180 nm process, are assumed.It is however possible to realise arbitrary on-and off-resistances, r f, on and r f, off by connecting a number of fuses in series and/or parallel and then either blowing all or none of the fuses in a branch.Because R f, on and R f, off are constant, the on-resistance of the resulting network will always be linearly related to its off-resistance by a factor, The question thus arises on how to select r f, on (or, equivalently r f, off ) in order to maximise the Q factor for the resulting capacitor for the worst-case configuration of active/blown fuses.It should be noted that both R f, on and R f, off is highly process dependent, which may make fuse trimming less attractive in some processes than others, particularly those in which k f is small, which will be demonstrated later in this section.

Q Factor Optimisation for a Single Branch
Consider starting with the base capacitance, C, and adding a single fuse-controlled branch to that circuit.The resulting Q factor, Q eq (a f ), for arbitrarily selected component values are plotted in Figure 2 as a function of the fuse scaling factor, a f , with the fuse resistance, R f , attaining values for both active and blown fuses.Here a f is the factor by which a fuse is scaled by a series and/or parallel connection that gives a scaled fuse resistance r f = a f R f , and also r f, on = a f R f, on and r f, off = a f R off .In order to maximise the resulting worst-case Q factor, we want to find the value of a f for which the worst-case Q eq (a f ) for both cases of R f is as large as possible.That is, we want to maximise the function From the figure, it can be seen that the maximum Q eq is obtained either for very small values for a f or for very large values for a f .In fact, Q eq tends towards infinity for such values.The reason for this is that, for very small a f , the fuse behaves as a short circuit for both its active and blown state and thus does not contribute significantly to the total equivalent resistance of the circuit.The contrary is true for very large a f , where the fuse behaves as an open circuit for both cases and thus the branch does not contribute significantly to the equivalent impedance.Thus, if we choose such extreme values for a f , the resulting equivalent capacitance can no longer be controlled by the fuse.Therefore, we must choose a value for a f in a region where the fuse behaves as a short circuit for active fuses (to the left of the minimum Q eq (a f ) of the blue solid line), and as an open circuit for blown fuses (to the right of the minimum Q eq (a f ) for the red dashed line).It can be seen from Figure 2 that a local maximum for f (a f ) within this region occurs at the intersection point of the of the curves representing the Q factor for R f = R f, on and R f = R f, off , respectively.
Note that this point represents the fuse resistances for which the Q factor has degraded equally for the active and blown states of the fuse.Deviating from this point increases the Q factor for one of these states, but decreases it for the other.The intersection point thus represents the highest possible worst-case Q factor for the equivalent capacitor.It should also be noted that Figure 2 assumes infinite Q factors for all involved capacitors.If IC capacitors can be manufactured with a Q factor of Q cap , for extreme values for a f , Q eq would approach Q cap asymptotically instead of tending towards infinity.In fact, this behaviour is shown in a lighter shade in the figure.The simplification is made because it is reasonable to assume that the series resistance contributed to one of the capacitors by a scaled fuse will be much larger than the ESR of the capacitor itself.Thus, for non-extreme values for a f , which are the values we are interested in, Q cap will be much larger than Q eq .0.0001 0.01 1 100 10,000 10 100 1 000 10 000 100 000 1 000 000 ), for a 3 pF capacitor in parallel with a series combination of a fuse and a 1 pF capacitor, plotted as a function of fuse scaling factor, a f .Q eq (a f ) is plotted for both active and blown fuses corresponding to different fuse resistances.Plots for manufactured capacitors with both infinte Q factors and Q factors of 10 000 are shown, with the latter case in a lighter shade.
In the pursuit to find an expression for the intersection point of Figure 2, consider the equivalent impedance, Z eq , resulting from the parallel connection of two impedances, Here, symbols R and X denote the resistance and reactance, respectively, of the impedance Z with corresponding index.It can be shown that Z eq is given by Regarding the resulting impedance as a capacitor with a series resistance, the resulting Q factor is given by To find the intersection point of Figure 2 in terms of the scaled fuse resistance, r f, on = a f R f, on , we set where k f is given by Equation ( 4) and a f is the scaling factor which can be obtained by a series and/or parallel connection of fuses.Substituting Equation ( 7) into Equation ( 8) yields Solving Equation ( 9) for r f, on yields Relating this expression to Figure 1, we substitute X 1 = −1/(ωC n ), X 2 = −1/(ωC) and R 2 = R, where C n is the added capacitance in the branch currently being added, C is the base capacitance including all thus far added branches, R is the resistance in series with C resulting from all fuse resistances from all thus far added branches and ω is the angular frequency under which the circuit is intended to operate.Thus, r f, on as a function of branch number, n, can be written as Let Q represent the Q factor given by the series combination of C and R.Then, Q = 1/ωCR.Substituting this expression into Equation ( 11) yields For practical component values, the inequalities Q 1/Q and hold and because r f, on > 0, Equation (12) reduces to Thus we have arrived at an expression for how to select the scaled fuse resistance, r f, on (n), when adding one fuse-controlled branch to the base capacitance.

Q Factor Optimisation for Multiple Branches
In order to find r f, on (n) for the fuses in each branch, one possible solution is to use Equation ( 14) recursively for all the branches.However, there is a challenge associated with this approach.Consider adding the first branch to the base capacitance.In this case, it is obvious which value to use for C.However, for the next branch, C might take on two different values depending on whether the fuse will be active or blown in the first branch, so we would also need to consider the case for when C is substituted for C + ∆C.When adding the third branch, there will be four possible values for C. In fact, the number of values would double for each new branch added.
Because of this complexity, we do not pursue this approach further.Instead, we use Equation ( 14) to obtain an expression for the Q factor, Q n , of the branch being added when its fuse is active: If only one branch would be added, we could use Equation (15) to know which Q factor it should have in its active state, which would in turn yield a value for r f, on (n).However, as explained above, we don't know which value to use for C in the coming branches because the fuse configuration is unknown.Thus, it appears that we can only use Equation (15) to find r f, on (n) for one of the branches.
However, consider the case when all branches have the same Q factor with all fuses active.We denote this Q factor Q on .The equivalent Q factor does not change if multiple branches with identical Q factor are connected in parallel.Therefore, for a certain fuse configuration, we would have one equivalent Q factor, Q on , for all active branches and one equivalent Q factor, Q off , for all blown branches.Because the Q factor is inversely proportional to the branch resistance, Q on = k f Q off .If we attempt to increase Q on by increasing the Q factor for a single branch, the Q factor for that branch in its blown state will also increase.While this would result in an increased Q eq for when this branch is active, it would decrease it for when it is blown.Refer to Figure 2 and note that at the intersection point, an increased Q on would mean a decreased a f and thus a decreased scaled fuse resistance, r f, on (n).Following the blue solid line from the intersection point for decreasing a f yields a higher Q eq .However, for Q off , following the red dashed line for decreasing a f yields a lower Q eq .
Similarly, we could try to increase the worst-case Q eq by increasing Q off .However, this would also increase it for Q on and, by the same reasoning as before, would result in a lower worst-case Q eq .Attempting to change the fuse resistance for multiple branches simultaneously will also not improve the worst-case Q eq because for the worst-case, the fuse state resulting in the lowest Q eq will be in use for each branch.Thus, we conclude that Q eq will be maximised when all branches have the same Q factor.This Q factor can be found by considering the equivalent circuit for all branches with the fuses in their active state and then using Equation (15) and substituting C n for the equivalent parallel resistance for the branches, ∆C, to find the Q factor for a branch, Q branch = Q n , for all n: Equations ( 15) and ( 16) can then be used to find r f, on (n) as This is an expression for the scaled fuse resistance, r f, on (n), for each branch, which yields the maximal worst-case equivalent Q factor, Q eq .Here, C n = C x 2 n was used in order to obtain an expression for r f, on (n) as a function of C x .It should be noted that if the exact value for r f, on (n) required by Equation ( 17) cannot be obtained because a prohibitively large number of fuses would be required, an error will be introduced in Q branch .Because the Q factor of a capacitor is given by its reactance divided by its resistance (that is, in the case for Q branch , divided by r f, on (n)), the relative error in the worst-case Q branch will be no greater than the relative worst-case error in r f, on (n), or equivalently, no greater than the relative error in the fuse scaling factor, a f , in the fuse with the largest relative scaling mismatch.
To obtain an expression for the resulting worst-case equivalent Q factor when a fuse-controlled branch is connected in parallel with the base capacitance, C, we use Equation ( 7) and substitute where r f, on, eq is the scaled fuse on-resistance obtained for a branch with ∆C as series capacitance.
The resulting expression is given by Inserting Equation (16) into Equation ( 22) and making the assumption that Q branch 1 yields From Equation (23) it can be seen that increasing the ratio of base capacitance to trim capacitance, C/∆C, increases Q eq .This is intuitive because that increases the ratio of capacitance contributed by capacitors with no series resistance to capacitance contributed by capacitors with series resistance.It can also be seen that a higher ratio, k f , between off and on resistance for the fuses used will increase Q eq , which is also intutive because higher quality fuses should yield better Q factors.
It is interesting to note that highest possible worst-case Q factor, Q eq , depends only on the ratio between desired base and trim capacitance as well as on the ratio of resistance between blown and active fuses for the process technology and is thus frequency-independent.

Capacitance Accuracy
Because C eq is the result of connecting a capacitor with no series resistance in parallel to a number of capacitors with series resistance, the resulting capacitance value will not be exactly equal to the target capacitance.Another contribution to the mismatch in capacitance comes from parasitic elements such as bond pads used to program (blow) the fuses.In this section, we quantify these mismatches.

Effects of Fuse Resistance
Consider adding a single branch to the base capacitance, C. If the fuse for that branch is active, the contributed capacitance will be slightly lower than the actual value of the capacitor in that branch, C n , because of the series resistance of the branch.On the other hand, if the fuse for that branch is blown, the intent is that no capacitance should be contributed, but because of the finite fuse resistance, indeed some capacitance will be contributed.Thus, we see that active branches contribute too little capacitance, whereas blown branches contribute too much capacitance.The magnitude of the mismatch of target capacitance to actual capacitance will thus be largest either for all fuses active or for all fuses blown.
For the case for all fuses active, the equivalent impedance, Z eq , can be found from Equation ( 6).Since we are only interested in the difference in capacitance, we are only interested in the reactive part of Z eq .Using the substitutions in Equations ( 18)-( 21), it can be shown that the reactive part of Z eq is given by The maximum difference between the target capacitance, (C + ∆C), and the capacitance contributed by Xeq is given by Substituting Equation (24) into Equation (25) yields, after some algebra, Thus, we have arrived at an expression for the maximum error in capacitance, Ĉerror , for all fuses active.It is interesting to note that Equation ( 27) can be interpreted as follows: The maximum error in capacitance equals the equivalent capacitance of two series-connected capacitors of capacitance C and ∆C, respectively, scaled by the factor 1/Q 2 branch .An expression for for the equivalent reactance for the case for all fuses blown, here denoted Xeq , can be obtained from Equation ( 6) using the substitutions in Equations ( 19)-( 21), and substituting Utilising Equation ( 16) and solving for k f , Xeq is given as The maximum difference between the target capacitance, C, and the capacitance contributed by Xeq is given by It can be shown that substituting Equation (29) into Equation (30) yields which is exactly equal in magnitude to Ĉerror in Equation ( 26), but with opposite sign; Čerror = − Ĉerror .
The error in capacitance for any fuse configuration, C error , will thus lie within the interval In assessing the accuracy we have neglected the effects of capacitance variations with respect to process, voltage and temperature.As stated in the introduction, we recommend using MIM capacitors to realise the trim capacitor presented in this work because of their temperature and voltage stability [10].However, the capacitors will still be subject some variation, especially as a result of variations in the manufacturing process.Because fuses are one-time programmable, they can not be used to compensate for variations in temperature or voltage which change over time, but they can be used to compensate for process variation.As an example, consider the application of an LC resonator discussed in the introduction.If the low-frequency inductance and the untrimmed resonant frequency are measured, the base capacitance, C, can be estimated from the resonance equation: where f 0 is the resonant frequency and L is the inductance of the resonator.When C is known, Equation (33) can be used again to calculate the value needed for the trim capacitance, ∆C, in order to realise the desired value for f 0 .If care is taken when designing the chip layout, the variations between C and ∆C can be matched to a high degree of accuracy and thus by estimating C, an estimation for ∆C can also be obtained.However, if the on-chip inductance can not be measured with sufficient accuracy or if the parasitic capacitance of the inductive element is significant, a two-step (or multi-step) procedure could be performed in order to estimate values for the reactive elements.One measurement of f 0 could be taken before fuse-programming and a second one after blowing the most significant fuse, F 0 .
Then, a least-squares approximation could be performed in order to obtain estimations of the sought values.However, for this case, because F 0 is used for parameter estimations instead of for trimming, the Q factor of the resulting capacitor would decrease compared to a single-step estimation procedure.

Parasitic Bond Pad Capacitance
To program (blow) a fuse, a large current is required.The current can be supplied through probe needles touching bond-pads on both sides of a fuse during factory testing.However, because bond-pads typically present a parasitic capacitance to ground on the order of hundreds of femtofarads, they can be an obstacle for the accuracy of the trimmable capacitor.This effect becomes significant when the bond pad capacitance becomes comparable to the smallest capacitor in the circuit, Note also that if a fuse consists of multiple fuses in series, an additional bond pad will be required for each series connection in order to be able to blow every fuse.
If a higher resolution is required than what a bond pad-based system can provide, probe pads could be used instead.Probe pads can typically be made small enough to present a parasitic capacitance to ground of the order of only a few femtofarads.
Another possibility is to let the programming of fuses be controlled by transistors.However, the ratio of capacitance to current-driving capability of transistors as well as the current required to blow a fuse is very dependent on process technology, and thus we do not attempt to assess the viability of this idea further in this work.

Discussion and Examples
In this section we discuss the performance of the circuit of this work by relating it to an example application.
Consider an application where we need a base capacitance, C, of 3 pF and a trim capacitance, ∆C, of 1 pF with a 3-bit resolution and at an operating frequency of 433 MHz.We thus use the circuit in Figure 1 and choose C x = 571 fF according to Equation (3).The resolution is thus C res = C 2 = C x /2 2 = 143 fF.The question arises on how to select the scaled fuse resistance for the different fuses, r f, on (n).Consider first the naive design in which all fuses have the same resistance and consist only of a single fuse whose resistance is R f, on = 25 Ω while active and R f, off = 80 kΩ while blown.Figure 3a shows the resulting equivalent Q factor, Q eq (F), as a function of fuse configuration, F. Here, F is represented by a 3-bit binary number where 1 signifies an active fuse and 0 signifies that a fuse is blown.While the best-case Q factor is high at Q eq (110) = 297, the worst-case Q factor is much lower at Q eq (001) = 114.(b) The ideal design, where all fuses have been scaled to their optimal resistance r f = a f R f ; and (c) The practical design, where all the fuses consist of series/parallel combinations of one or two fuses of resistance R f in order to approximate r f, on .
A more balanced equivalent Q factor can be achieved if Equations ( 16) and ( 17) are used to obtain an expression for the scaled fuse resistance, r f, on (n).Using these equations, we get r f (0) = 13.13Ω, (34) Figure 3b shows the resulting Q factor, Q eq (F), as a function of F. It can be seen from the figure that the Q factor is constant independent of fuse configuration and that the worst-case Q factor has been increased to Q eq (F) = 196, a 72 % increase compared to the naive design.Note that, as expected, this value for Q eq coincides with the value at the intersection point of Figure 2.
The improvement results from the fact that we have identified that some configurations yield a much higher Q factor than others and made appropriate adjustments.By sacrificing the Q factor of the good configurations we have increased it for the worse ones resulting in a better Q factor for the worst case.The variation of the Q factor from 114 to 297 has been reduced to no variation at all.
Because of the potential high fuse count, it may be impractical to realise the values for r f, on (n) in Equations ( 34)-(36) to a high degree of accuracy with a series/parallel combination of a single fuse resistance, R f, on .However, the following combinations yield values that are within 6 % of the desired ones using only one or two fuses for each branch: Figure 3c shows the resulting equivalent Q factor, Q eq (F).The worst-case value has now decreased to Q eq (000) = 187, a 5 % decrease compared to the ideal design.A result of this deviation from the ideal is that the Q factor is once again not completely constant.
The number of bond pads required to be able to blow all fuses amounts to 6 because there are a total of 5 fuses in the circuit and one additional bond pad for the current return path is required.Standard-size bond pads for a 180 nm process present a capacitance to ground around of 140 fF per pad.The total amount of capacitance from bond pads would thus be much larger than C res = 143 fF and we would need to consider a different approach.Scaling down the pad area to 10 × 10 µm 2 , probe pads with a capacitance of approximately 3.5 fF per pad can be manufactured.Using such pads to program the fuses results in a total parasitic capacitance contribution from pads of maximum 21 fF, which is about a factor of 7 smaller than the resolution, C res .The variation in capacitance due to the non-ideal Q factors of the trim branches amounts to 344 aF, close to the ideal case of 312 aF, calculated from Equation (26), which is far below the intended resolution.
In the previous example, the worst-case Q factor for the naive design is smaller than that for the practical design, however, not by a huge factor.This is because the process parameters, R f, on and R f, off , the desired base and trim capacitances, C and ∆C, number of bits, m, as well as the operating frequency happen to be of values which are beneficial for high Q factors.Consider what would happen if both specified capacitances, C and ∆C, are decreased by a factor of 10.Equations ( 16) and (17) show that significantly larger values would be needed for the scaled fuse resistance, r f, on (n). Figure 4 shows the equivalent Q factor, Q eq (F), as a function of fuse configuration, F, for C = 300 fF and ∆C = 100 fF.Interestingly, identical graphs would be produced if either the operating frequency or R f, on and R f, off were decreased by a factor of 10 instead of C and ∆C.From the figure, it can be seen that the fuse configuration F = 111 achieves a much more favourable Q factor than the other configurations, with Q eq (111) = 1370.The worst-case Q factor is significantly lower at Q eq (000) = 22.9.Relating to Figure 2, the reason for this behaviour is that the fuse scaling factor, a f , for each fuse is not high enough and the operating point ends up to the left of the intersection point yielding very high Q factors for active fuses, but very low ones for blown fuses.Coming back to Figure 4, we see that only the case for all fuses active yields a high Q factor.By scaling the fuses appropriately and because the maximum worst-case Q factor is frequency-independent and constant for constant k f = R f, off /R f, on and ∆C/C, we can again achieve the Q factors of Figure 3b with a worst-case (and best-case) Q factor of Q eq (F) = 196.0 500 1 000 , of a trimmable capacitor as a function of the configuration of 3 fuses with the same resistance, R f .All parameters are the same as in Figure 3a, except the specified capacitances, C and ∆C, have both been decreased by a factor of 10.
To illustrate what could happen if care is not taken to ensure a sufficiently high Q factor, consider what would happen if a state-of-the art coil was to be used with the capacitor from the last example to form an LC resonator.Q factors of on-chip coils of 11.05 [2] and 10.5 [3] operating at hundreds of MHz have been demonstrated.Connecting one such coil to a capacitor with a worst-case Q factor of 22.9, as in the example, the worst-case Q factor of the resulting LC circuit would be reduced by over 30 % compared to the original Q factor of the coil.However, if the method described in this work was to be used, the coils could be connected to a capacitor with a worst-case Q factor of 187 as in Figure 3c, reducing the worst-case Q factor of the resulting LC circuit by less than 6 %.
Another challenge arises when we attempt to implement a practical circuit approximating the ideal design for this case of smaller capacitances.For instance, the highest resistance we would need to realise is R 2 = 525 kΩ for which 21 fuses would be needed.Such a circuit would require around 40 bond or probe pads which would present a relatively large parasitic pad capacitance, 140 fF in the worst case, to the trim capacitor, limiting the resolution.Since the desired resolution is even less than that at 100 fF, the circuit designers should consider accepting a lower resolution, reducing the number of bits and/or reducing the base capacitance, C.
The requirement of high numbers of series fuses arises when the largest scaled fuse resistance, r f, on (m − 1), becomes much larger than R f, on .Equations ( 16) and (17) show that this occurs when Thus, for higher frequencies, larger specified capacitances, larger fuse resistances or a fewer number of bits than for the previous example, a high number of series fuses would not be an issue.In this case, most fuses will be required in parallel instead, to achieve sufficiently low values for r f, on (n).

Conclusions
In this paper, we present a circuit implementing a fuse-based IC trimmable capacitor.A theory is presented on how to choose fuse resistances in order to achieve the highest possible worst-case Q factor for the capacitor.One advantage of a fused-based approach is that it is cheaper than the alternative method of laser trimming.The theory presented in this work is novel in that, to the authors' knowledge, high-Q, fuse-based trimmable IC capacitors have not previously been published.
We show that proper selection of fuse resistances not only maximises the worst-case Q factor, but also makes it constant and independent of fuse configuration.This makes it possible to build applications such as on-chip tunable LC resonant circuits with a predictable Q factor that is independent of tuned frequency without resorting to laser trimming.
Furthermore the accuracy of the capacitance is discussed and it is concluded that capacitance from bond pads may be a limiting factor.This limitation can to some extent be overcome by the use of smaller, low capacitance probe pads.

Figure 3 .
Figure3.Equivalent Q factor, Q eq (F), of a trimmable capacitor of C = 3 pF and ∆C = 1 pF, operating at 433 MHz as a function of the configuration of 3 fuses, represented by a binary number, F, where the nth bit represents fuse n, F n .F n = 1 signifies an active fuse, while F n = 0 signifies that fuse n is blown.Plots are shown for three designs: (a) The naive design, where all fuses have the same resistance, R f ; (b) The ideal design, where all fuses have been scaled to their optimal resistance r f = a f R f ; and (c) The practical design, where all the fuses consist of series/parallel combinations of one or two fuses of resistance R f in order to approximate r f, on .