More Discussions on Intrinsic Frequency Detection Capability of Full-Rate Linear Phase Detector in Clock and Data Recovery

The full-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability intrinsically. Previously, this fact has been discovered by researching the phase and frequency characteristics of the combined full-rate linear PD and charge pump (CP) under the condition that the ratio of the received data frequency (f DATA) and the recovered clock frequency (f CLK) is set as an integer number. In this paper, for completeness of the theory, the phase and frequency characteristics of the combined full-rate linear PD and CP are studied again while the ratio of f DATA and f CLK is set as a general rational number. Additionally, theoretical analyses of the lock-in range and the lock time of the referenceless single-loop clock and data recovery (CDR) including the full-rate linear PD are newly developed and verified. The calculated lock times by the analysis results agree well with the measured lock times from the MATLAB Simulink simulations.


Introduction
To cover the wide range of data rates of the clock and data recovery (CDR) loops and to compensate for the process, voltage, and temperature (PVT) variations of clock frequency from voltage controlled oscillator (VCO), various frequency acquisition techniques have been utilized [1][2][3][4][5][6][7][8][9] in the serial data interfaces.However, most of these techniques originate from the thought that the phase detectors cannot detect the frequency difference between the received data and the recovered clock in the CDR loops.
Recently, it has been discovered in Reference [10] that the full-rate Hogge linear phase detector (PD) [11] has not only phase detection capability but also intrinsic single-sided frequency detection capability, and such that a referenceless single-loop CDR can be simply implemented by using only the full-rate linear PD without any frequency acquisition techniques.To prove this intrinsic frequency detection capability of the full-rate linear PD, several timing diagrams have been drawn at different clock frequencies specifically when the ratio of the received data frequency (f DATA ) and the recovered clock frequency (f CLK ) is set as an integer number and the phase and frequency characteristics of the combined full-rate linear PD and charge pump (CP) have been obtained [10].However, if the ratio of f DATA and f CLK is not an integer number, we could not help but use interpolation between adjacent integer ratios and confirm the interpolated phase and frequency characteristics by providing many supportive MATLAB Simulink simulations.In Reference [10], we have also developed the frequency-locked loop (FLL) analysis to prove that the locking trajectory of the referenceless single-loop CDR utilizing the frequency detection capability of the full-rate linear PD is uniquely represented by an exponential decay function with a single time constant.However, we could not derive in [10] the closed-form equations of the lock-in range and the lock time of the CDR loop theoretically.
In this paper, for completeness of the theory, the phase and frequency characteristics of the combined full-rate linear PD and CP are to be studied again while the ratio of f DATA and f CLK is not constrained to just an integer but extended to a general rational number.Additionally, theoretical analyses of the lock-in range and the lock time are to be newly developed for the referenceless single-loop CDR implemented by using only the full-rate linear PD without any frequency acquisition aids and verified by comparing the calculated lock times by the analysis results and the measured lock times from the MATLAB Simulink simulations.
Therefore, this paper is organized as follows.In Section 2, the phase and frequency characteristics of the combined full-rate linear PD and CP are presented when the ratio of f DATA and f CLK is set as a general rational number.In Section 3, theoretical analyses of the lock-in range and the lock time of the referenceless single-loop CDR including the full-rate linear PD are developed and verified by using the MATLAB Simulink simulations.The conclusion is given in Section 4.

Phase and Frequency Characteristics of the Combined Full-Rate Linear PD and CP
Figure 1 shows the referenceless single-loop CDR architecture including the full-rate linear PD, which is the so-called Hogge PD [11].If θ is defined as the phase difference between the center of the received data (DIN) and the rising edge of the recovered clock (CLK) as shown in Figure 1, we have shown in Reference [10] that the full-rate linear PD outputs the up (UP) and down (DN) pulses of which pulse widths are (2n − 1)π + θ and nπ, respectively, per every n bits when f CLK = 1/n × f DATA and n is an integer number greater than or equal to 1.As the one bit duration of the received data is 2π, the CP output current can be represented as where I UP is the CP up current, I DN is the CP down current, α is the bit transition density, and the current sources of the CP up and down paths are both equal to I CP .Figure 2a,b show the timing diagrams when n = 1 and n = 2, respectively, for example.For ease of understanding, the rising and falling edges of the recovered clock are colored in red and green, respectively.In these timing diagrams, we can observe that θ is kept constant from bit to bit as time goes on because n is set as an integer number exactly.In Figure 2a,b, the UP pulse is null during π − θ, which is equivalent to the time difference between the rising edge (in red color) of the recovered clock and the next bit transition of the received data.Thus, the UP pulse width is 2nπ − (π − θ) per every n bits.However, the DN pulse width is always nπ because it is equal to half of the recovered clock period per every n bits.
exponential decay function with a single time constant.However, we could not derive in [10] the closed-form equations of the lock-in range and the lock time of the CDR loop theoretically.In this paper, for completeness of the theory, the phase and frequency characteristics of the combined full-rate linear PD and CP are to be studied again while the ratio of fDATA and fCLK is not constrained to just an integer but extended to a general rational number.Additionally, theoretical analyses of the lock-in range and the lock time are to be newly developed for the referenceless singleloop CDR implemented by using only the full-rate linear PD without any frequency acquisition aids and verified by comparing the calculated lock times by the analysis results and the measured lock times from the MATLAB Simulink simulations.
Therefore, this paper is organized as follows.In Section 2, the phase and frequency characteristics of the combined full-rate linear PD and CP are presented when the ratio of fDATA and fCLK is set as a general rational number.In Section 3, theoretical analyses of the lock-in range and the lock time of the referenceless single-loop CDR including the full-rate linear PD are developed and verified by using the MATLAB Simulink simulations.The conclusion is given in Section 4.

Phase and Frequency Characteristics of the Combined Full-Rate Linear PD and CP
Figure 1 shows the referenceless single-loop CDR architecture including the full-rate linear PD, which is the so-called Hogge PD [11].If θ is defined as the phase difference between the center of the received data (DIN) and the rising edge of the recovered clock (CLK) as shown in Figure 1, we have shown in Reference [10] that the full-rate linear PD outputs the up (UP) and down (DN) pulses of which pulse widths are (2n − 1)π + θ and nπ, respectively, per every n bits when fCLK = 1/n × fDATA and n is an integer number greater than or equal to 1.As the one bit duration of the received data is 2π, the CP output current can be represented as where IUP is the CP up current, IDN is the CP down current, α is the bit transition density, and the current sources of the CP up and down paths are both equal to ICP. Figure 2a,b show the timing diagrams when n = 1 and n = 2, respectively, for example.For ease of understanding, the rising and falling edges of the recovered clock are colored in red and green, respectively.In these timing diagrams, we can observe that θ is kept constant from bit to bit as time goes on because n is set as an integer number exactly.In Figure 2a,b, the UP pulse is null during π − θ, which is equivalent to the time difference between the rising edge (in red color) of the recovered clock and the next bit transition of the received data.Thus, the UP pulse width is 2nπ − (π − θ) per every n bits.However, the DN pulse width is always nπ because it is equal to half of the recovered clock period per every n bits.
(a) (b)   By following the similar way, we can also derive the CP output current when n is set as a general rational number greater than 1.Since n is now a rational number greater than 1, n = p/q, p > q, and p and q are relatively prime integers.Then, we can find regularity in the UP and DN pulses by carefully observing the timing diagrams when n is set as rational numbers.Figure 2c,d show the timing diagrams when n = 3/2 and n = 4/3, respectively, for example.In these timing diagrams, it is interestingly observed that there are exactly q clocks and so q different θ  {θ1, θ2, …, θq} in every p bits and that the UP pulse is null during π − θ again.Thus, the UP pulse width is per every p bits and the DN pulse width is π × p per every p bits since the DN pulse is always null for half of the recovered clock period.Consequently, the CP output current can be represented in a simple form as follows.
  For the calculation of   q i i q 1 1  in Equation ( 2), we have to carefully consider the distribution of the rising edges of the recovered clock signals in Figure 3. Since n = p/q is a rational number greater than 1, θ increases linearly within the range of (−π, +π) as time goes on.Since θ is periodic for every q clocks such that θi+q = θi, θ is uniformly distributed over one bit period between π and +π with the same space of 2π/q as shown in Figure 3. Accordingly, 1  has the minimum value of π/q if the rising edges of the clock signals are aligned as shown in Figure 3b and the maximum value of +π/q if the rising edges of the clock signals are aligned as shown in Figure 3c.Thus, By following the similar way, we can also derive the CP output current when n is set as a general rational number greater than 1.Since n is now a rational number greater than 1, n = p/q, p > q, and p and q are relatively prime integers.Then, we can find regularity in the UP and DN pulses by carefully observing the timing diagrams when n is set as rational numbers.Figure 2c,d show the timing diagrams when n = 3/2 and n = 4/3, respectively, for example.In these timing diagrams, it is interestingly observed that there are exactly q clocks and so q different θ ∈ {θ 1 , θ 2 , . . ., θ q } in every p bits and that the UP pulse is null during π − θ again.Thus, the UP pulse width is 2π per every p bits and the DN pulse width is π × p per every p bits since the DN pulse is always null for half of the recovered clock period.Consequently, the CP output current can be represented in a simple form as follows.
For the calculation of 1 q q ∑ i=1 θ i in Equation (2), we have to carefully consider the distribution of the rising edges of the recovered clock signals in Figure 3. Since n = p/q is a rational number greater than 1, θ increases linearly within the range of (−π, +π) as time goes on.Since θ is periodic for every q clocks such that θ i+q = θ i , θ is uniformly distributed over one bit period between −π and +π with the same space of 2π/q as shown in Figure 3. Accordingly, 1 q q ∑ i=1 θ i has the minimum value of −π/q if the rising edges of the clock signals are aligned as shown in Figure 3b and the maximum value of +π/q if the rising edges of the clock signals are aligned as shown in Figure 3c.Thus, when θ ∈ {θ 1 , θ 2 , . . ., θ q } and j = 0, 1, . . ., q − 1.Consequently, from Equations ( 2) and ( 3), the CP output current is represented by when θ ∈ {θ 1 , θ 2 , . . ., θ q } and j = 0, 1, . . ., q − 1.Additionally, it is worth noting that, if n is an integer number, or equivalently q = 1, the derived Equation ( 4) for a general rational number becomes equal to the previous Equation ( 1) for an integer number.
Electronics 2018, 7, x FOR PEER REVIEW 4 of 9 when θ  {θ1, θ2, …, θq} and j = 0, 1, …, q − 1.Consequently, from Equations ( 2) and ( 3), the CP output current is represented by when θ  {θ1, θ2, …, θq} and j = 0, 1, …, q − 1.Additionally, it is worth noting that, if n is an integer number, or equivalently q = 1, the derived Equation ( 4) for a general rational number becomes equal to the previous Equation ( 1) for an integer number.4) and the dot points are the simulated values by MATLAB Simulink.As shown in the figures, the calculated and simulated values agree well with each other.The difference between them is due to the randomness of the received data pattern.Figure 4c shows the figure of the general phase characteristic when n = p/q and n ≥ 1.The general phase characteristic is composed of the same q segments of which the width is 2π/q and the height is α ICP/p.The average value of the general phase characteristic becomes the frequency characteristic of the combined full-rate linear PD and CP.    4) and the dot points are the simulated values by MATLAB Simulink.As shown in the figures, the calculated and simulated values agree well with each other.The difference between them is due to the randomness of the received data pattern.Figure 4c shows the figure of the general phase characteristic when n = p/q and n ≥ 1.The general phase characteristic is composed of the same q segments of which the width is 2π/q and the height is α I CP /p.The average value of the general phase characteristic becomes the frequency characteristic of the combined full-rate linear PD and CP.  where Figure 6 shows both the ideal and actual locking trajectories of fCLK(t).The difference between them is due to the high-frequency ripple voltage which is added onto the ideal VCO control voltage (VCONT).This ripple voltage is mostly generated by R and C2 of the loop filter and by the real-time CP output current which is depending on θ and the bit transition pattern of the received random data.Since the lock-in range is defined as the frequency range within which a phase-locked loop (PLL) locks fast without cycle slip between the reference frequency and the output frequency, the lock-in range of the referenceless single-loop CDR is equivalent to the peak frequency deviation of fCLK(t) due to the ripple voltage [12].Thus, where flockin is the lock-in range and tlock is the lock time as shown in Figure 6.
Figure 6 shows both the ideal and actual locking trajectories of f CLK (t).The difference between them is due to the high-frequency ripple voltage which is added onto the ideal VCO control voltage (V CONT ).This ripple voltage is mostly generated by R and C 2 of the loop filter and by the real-time CP output current which is depending on θ and the bit transition pattern of the received random data.Since the lock-in range is defined as the frequency range within which a phase-locked loop (PLL) locks fast without cycle slip between the reference frequency and the output frequency, the lock-in range of the referenceless single-loop CDR is equivalent to the peak frequency deviation of f CLK (t) due to the ripple voltage [12].Thus, f CLK (t lock ) + ∆ f lockin = f DATA (7) where ∆f lockin is the lock-in range and t lock is the lock time as shown in Figure 6.To derive the lock time of the referenceless single-loop CDR, we should obtain the peak frequency deviation of fCLK(t).Figure 7 depicts the R and C2 of the loop filter and the CP of the referenceless single-loop CDR.v(t) is the ripple voltage and i(t) is the real-time CP output current.The value of v(t) will be maximum if θ = π and there comes consecutive bit transitions in the received data.Of course, keeping θ = π with long consecutive bit transitions is actually not possible and, thus, v(t) may be a bit smaller than the maximum value.Figure 8a shows the ideal waveforms of the realtime CP output current after each bit transition assuming that θ = π and there comes consecutive bit transitions and Figure 8b shows that of the effective real-time CP output current.Since i(t) flows into R and C2, v(t) increases asymptotically toward the maximum value (vmax) as shown in Figure 8c and can be derived as when m ≥ 2. Figure 9 shows the MATLAB Simulink simulated waveforms of the UP and DN pulses and the VCONT while frequency acquisition is being made.Since vmax = v(mTb) when m is  in Equation ( 8), the peak frequency deviation, or the lock-in range, is obtained from Equation ( 8) as By using Equations ( 6) and ( 7), the lock time can be also derived as follows.
For verification purpose, the MATLAB Simulink simulations were performed.The loop parameters of the referenceless single-loop CDR are set as fDATA = 2 GHz, fCLK(0) = 1 GHz, α = 0.5, KVCO = 2 GHz/V, ICP = 100 µA, R = 1 kΩ, C1 = 159 pF and C2 = 1.59 pF.The Bernoulli random binary sequence was used as the input data stream.Since VCONT is linear with fCLK in this simulation setup, we could measure the locking trajectory of VCONT instead of fCLK directly.To derive the lock time of the referenceless single-loop CDR, we should obtain the peak frequency deviation of fCLK(t).Figure 7 depicts the R and C2 of the loop filter and the CP of the referenceless single-loop CDR.v(t) is the ripple voltage and i(t) is the real-time CP output current.The value of v(t) will be maximum if θ = π and there comes consecutive bit transitions in the received data.Of course, keeping θ = π with long consecutive bit transitions is actually not possible and, thus, v(t) may be a bit smaller than the maximum value.Figure 8a shows the ideal waveforms of the realtime CP output current after each bit transition assuming that θ = π and there comes consecutive bit transitions and Figure 8b shows that of the effective real-time CP output current.Since i(t) flows into R and C2, v(t) increases asymptotically toward the maximum value (vmax) as shown in Figure 8c and can be derived as ) when m ≥ 2. Figure 9 shows the MATLAB Simulink simulated waveforms of the UP and DN pulses and the VCONT while frequency acquisition is being made.Since vmax = v(mTb) when m is  in Equation ( 8), the peak frequency deviation, or the lock-in range, is obtained from Equation (8) as By using Equations ( 6) and ( 7), the lock time can be also derived as follows.
For verification purpose, the MATLAB Simulink simulations were performed.The loop parameters of the referenceless single-loop CDR are set as fDATA = 2 GHz, fCLK(0) = 1 GHz, α = 0.5, KVCO = 2 GHz/V, ICP = 100 µA, R = 1 kΩ, C1 = 159 pF and C2 = 1.59 pF.The Bernoulli random binary sequence was used as the input data stream.Since VCONT is linear with fCLK in this simulation setup, we could measure the locking trajectory of VCONT instead of fCLK directly.To derive the lock time of the referenceless single-loop CDR, we should obtain the peak frequency deviation of f CLK (t). Figure 7 depicts the R and C 2 of the loop filter and the CP of the referenceless single-loop CDR.∆v(t) is the ripple voltage and i(t) is the real-time CP output current.The value of ∆v(t) will be maximum if θ = π and there comes consecutive bit transitions in the received data.Of course, keeping θ = π with long consecutive bit transitions is actually not possible and, thus, ∆v(t) may be a bit smaller than the maximum value.Figure 8a shows the ideal waveforms of the real-time CP output current after each bit transition assuming that θ = π and there comes consecutive bit transitions and Figure 8b shows that of the effective real-time CP output current.Since i(t) flows into R and C 2 , ∆v(t) increases asymptotically toward the maximum value (∆v max ) as shown in Figure 8c and can be derived as (8) when m ≥ 2. Figure 9 shows the MATLAB Simulink simulated waveforms of the UP and DN pulses and the V CONT while frequency acquisition is being made.Since ∆v max = ∆v(mT b ) when m is ∞ in Equation ( 8), the peak frequency deviation, or the lock-in range, is obtained from Equation (8) as By using Equations ( 6) and ( 7), the lock time can be also derived as follows.

Conclusions
In this paper, the phase and frequency characteristics of the combined full-rate linear PD and CP have been derived while the ratio of fDATA to fCLK is set as a general rational number.Additionally, the closed-form equations of the lock-in range and the lock time of the referenceless single-loop CDR including the full-rate linear PD have been derived theoretically.The calculated lock times by the derived equations agree well with the measured lock times from the MATLAB Simulink simulations.Red and blue colors are used to highlight that the values of the variables are changed for simulations and the resulted ratios are almost 1.

Conclusions
In this paper, the phase and frequency characteristics of the combined full-rate linear PD and CP have been derived while the ratio of f DATA to f CLK is set as a general rational number.Additionally, the closed-form equations of the lock-in range and the lock time of the referenceless single-loop CDR including the full-rate linear PD have been derived theoretically.The calculated lock times by the derived equations agree well with the measured lock times from the MATLAB Simulink simulations.

Figure 1 .
Figure 1.(a) The referenceless single-loop clock and data recovery (CDR) architecture including (b) the full-rate Hogge linear phase detector (PD).

Figure 1 .
Figure 1.(a) The referenceless single-loop clock and data recovery (CDR) architecture including (b) the full-rate Hogge linear phase detector (PD).

Figure 3 .i i 1 
Figure 3.The rising edges of the clock signals when  

Figure
Figure 4a,b show the phase characteristics of the combined full-rate linear PD and CP at several rational numbers of n.The solid lines are the calculated values by the derived Equation (4) and the dot points are the simulated values by MATLAB Simulink.As shown in the figures, the calculated and simulated values agree well with each other.The difference between them is due to the randomness of the received data pattern.Figure4cshows the figure of the general phase characteristic when n = p/q and n ≥ 1.The general phase characteristic is composed of the same q segments of which the width is 2π/q and the height is α ICP/p.The average value of the general phase characteristic becomes the frequency characteristic of the combined full-rate linear PD and CP.

Figure 3 .
Figure 3.The rising edges of the clock signals when

Figure
Figure 4a,b show the phase characteristics of the combined full-rate linear PD and CP at several rational numbers of n.The solid lines are the calculated values by the derived Equation (4) and the dot points are the simulated values by MATLAB Simulink.As shown in the figures, the calculated and simulated values agree well with each other.The difference between them is due to the randomness of the received data pattern.Figure4cshows the figure of the general phase characteristic when n = p/q and n ≥ 1.The general phase characteristic is composed of the same q segments of which the width is 2π/q and the height is α I CP /p.The average value of the general phase characteristic becomes the frequency characteristic of the combined full-rate linear PD and CP.

Figure 6 .
Figure 6.The locking trajectory of fCLK and the lock-in range.

Figure 6 .
Figure 6.The locking trajectory of fCLK and the lock-in range.

Figure 6 .
Figure 6.The locking trajectory of f CLK and the lock-in range.

Figure 7 .
Figure 7.The calculation of the ripple voltage due to R and C2.

Figure 8 .
Figure 8.(a) Each and (b) the effective real-time charge pump current after consecutive bit transitions when θ = π and (c) the consequent ripple voltage.

Figure 7 . 9 Figure 7 .Figure 8 .
Figure 7.The calculation of the ripple voltage due to R and C 2.

Figure 8 .
Figure 8.(a) Each and (b) the effective real-time charge pump current after consecutive bit transitions when θ = π and (c) the consequent ripple voltage.

Figure 7 .Figure 8 .
Figure 7.The calculation of the ripple voltage due to R and C2.

Figure 9 .
Figure 9.The simulated UP/DN pulses and V CONT voltage.

Figure 10 .
Figure 10.The simulated locking trajectories of V CONT when (a) f DATA , (b) I CP , (c) C 1 and (d) C 2 are varied.

Table 1 .
The loop parameters and lock times.

Table 1 .
The loop parameters and lock times. f