Special Issue "Advanced Analog Circuits for Emerging Applications"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Artificial Intelligence Circuits and Systems (AICAS)".

Deadline for manuscript submissions: 15 April 2023 | Viewed by 6341

Special Issue Editors

Dr. Shiwei Wang
E-Mail Website
Guest Editor
Institute for Integrated Micro & Nano Systems, School of Engineering, University of Edinburgh, Edinburgh EH8 9YL, UK
Interests: analogue and mixed signal integrated circuits; circuits for AI; biomedical; implantable/wearable; brain–machine interface; sensor instrumentation
Dr. Shuang Song
E-Mail Website
Guest Editor
School of Micro-nano Electronics, Zhejiang University, Hangzhou, Zhejiang 310030, China
Interests: analog and mixed signal IC design; biomedical SoCs for wearable devices; interface circuits for MEMS and sensors; physiological signal acquisition and processing

Special Issue Information

Dear Colleagues,

Analog circuits are still playing a critical role in a world today that seems to be dominated by digital electronics. It is vital to interface with the physical world where the signals are analog in nature. Looking further into the future, we are embracing an era in which everything will be unprecedentedly connected, and the world–machine interactions will become ubiquitous. This is accompanied by various emerging applications which bring about opportunities and challenges to future analog circuit design. In this context, this Special Issues calls for in-depth studies and advanced developments on analog circuit designs for applications including but not limited to:·        

  • Bio-medical and health care electronics;·        
  • Environmental sensing and monitoring;·        
  • Food screening and agricultural applications;·        
  • IoT in energy and other industrial applications;·        
  • Resilient electronics in harsh environments;·        
  • Machine learning and artificial intelligence;·        
  • Design with emerging technologies such as flexible electronics, thin film devices, emerging memory devices, etc.

Dr. Shiwei Wang
Dr. Shuang Song
Guest Editors

Manuscript Submission Information

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Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2000 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

 

Keywords

  • Analog circuits
  • Ultra-low power design
  • Emerging technologies
  • Intelligent sensors and sensor interfaces
  • Analog processing and computation
  • VLSI and microsystems

Published Papers (6 papers)

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Research

Article
A Fast Homeostatic Inhibitory Plasticity Rule Circuit with a Memristive Synapse
Electronics 2023, 12(3), 490; https://doi.org/10.3390/electronics12030490 - 17 Jan 2023
Viewed by 255
Abstract
Learning from the robust mechanism of the biological nervous system is critical for creating reliable neuromorphic hardware. The homeostatic inhibition plasticity rule is a robust biological mechanism to balance Hebbian plasticity and resist external environmental disturbances and local damage. It plays an essential [...] Read more.
Learning from the robust mechanism of the biological nervous system is critical for creating reliable neuromorphic hardware. The homeostatic inhibition plasticity rule is a robust biological mechanism to balance Hebbian plasticity and resist external environmental disturbances and local damage. It plays an essential role in maintaining the homeostatic sparse firing patterns of the nervous system. This paper imitates this mechanism and provides a fast homeostatic inhibitory plasticity rule circuit with a memristive synapse. Firstly, the design method and principle of the circuit are demonstrated. Secondly, the function of the circuit was verified in PSpice© using a commercial Knowm memristor as a synapse. The PSpice© simulation results show that the circuit can achieve a weight update curve similar to the biological homeostatic inhibitory plasticity rule, and the time scale of the circuit is improved by a factor of 1000 compared to that of the biological nervous system. Furthermore, the circuit has wide applicability due to the tunable qualities of the homeostatic learning window, scaling factor, and homeostatic factor. This study provides new opportunities for building fast and reliable neuromorphic hardware. Full article
(This article belongs to the Special Issue Advanced Analog Circuits for Emerging Applications)
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Article
Resolving the Unusual Gate Leakage Currents of Thin-Film Transistors with Single-Walled Carbon-Nanotube-Based Active Layers
Electronics 2022, 11(22), 3719; https://doi.org/10.3390/electronics11223719 - 13 Nov 2022
Viewed by 563
Abstract
Solution-processed single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) in the research stage often have large active areas. This results in unusual gate leakage currents with high magnitudes that vary with applied voltages. In this paper, we report an improved structure for solution-processed SWCNT-based [...] Read more.
Solution-processed single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) in the research stage often have large active areas. This results in unusual gate leakage currents with high magnitudes that vary with applied voltages. In this paper, we report an improved structure for solution-processed SWCNT-based TFTs. The unusual gate leakage current in the improved structure is resolved by patterning the SWCNT active layer to confine it to the channel region. For comparative purposes, this improved structure is compared to a traditional structure whose unpatterned SWCNT active layer expands well beyond the channel region. As TFT performance also varies with oxide layer thickness, 90 nm and 300 nm thick oxides were considered. The improved TFTs have gate leakage currents far lower than the traditional TFT with the same dimensions (aside from the unpatterned active area). Moreover, the unusual variation in gate leakage current with applied voltages is resolved. Patterning the SWCNT layer, increasing the oxide thickness, and reducing the top electrode length all help prevent a rapid dielectric breakdown. To take advantage of solution-based fabrication processes, the active layer and electrodes of our TFTs were fabricated with solution-based depositions. The performance of the TFT can be further improved in the future by increasing SWCNT solution incubation time and reducing channel size. Full article
(This article belongs to the Special Issue Advanced Analog Circuits for Emerging Applications)
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Article
A 0.00426 mm2 77.6-dB Dynamic Range VCO-Based CTDSM for Multi-Channel Neural Recording
Electronics 2022, 11(21), 3477; https://doi.org/10.3390/electronics11213477 - 26 Oct 2022
Viewed by 575
Abstract
Driven by needs in neuroscientific research, future neural interface technologies demand integrated circuits that can record a large number of channels of neural signals in parallel while maintaining a miniaturized physical form factor. Using conventional methods, it is challenging to reduce circuit area [...] Read more.
Driven by needs in neuroscientific research, future neural interface technologies demand integrated circuits that can record a large number of channels of neural signals in parallel while maintaining a miniaturized physical form factor. Using conventional methods, it is challenging to reduce circuit area while maintaining the high dynamic range, low noise, and low power consumption required in the neural application. This paper proposes to address this challenge using a VCO-based continuous-time delta-sigma modulator (CTDSM) circuit, which can record and digitize neural signals directly without the need for front-end instrumentation amplifiers and anti-aliasing filters, which are limited by the abovementioned circuit-area performance tradeoff. Thanks to the multi-level quantization and intrinsic mismatch-shaping capabilities of the VCO-based approach, the proposed first-order CTDSM can achieve comparable electrical performance to a higher-order CTDSM while offering further area and power reductions. We prototyped the circuit in a 22-channel test chip and demonstrate, based on the chip measurement results, that the proposed modulator occupies an area of 0.00426 mm2 while achieving input-referred noise levels of 6.26 and 3.54 µVrms in the action potential (AP) and local field potential (LFP) bands, respectively. With a 77.6 dB wide-dynamic range, the noise and total harmonic distortion meet the requirements of a neural interface with up to 149 mVpp input AC amplitude or up to ±68 mV DC offsets. We also validated the feasibility of the circuit for multi-channel recording applications by examining the impact of cross-channel VCO oscillation interferences on the circuit noise performance. The experimental results demonstrate the proposed architecture is an excellent candidate to implement future multi-channel neural-recording interfaces. Full article
(This article belongs to the Special Issue Advanced Analog Circuits for Emerging Applications)
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Article
A Band-Pass Instrumentation Amplifier Based on a Differential Voltage Current Conveyor for Biomedical Signal Recording Applications
Electronics 2022, 11(7), 1087; https://doi.org/10.3390/electronics11071087 - 30 Mar 2022
Cited by 1 | Viewed by 924
Abstract
Recently, due to their abundant benefits, current-mode instrumentation amplifiers have received considerable attention in medical instrumentation and read-out circuit for biosensors. This paper is focused on the design of current-mode instrumentation amplifiers for portable, implantable, and wearable electrocardiography and electroencephalography applications. To this [...] Read more.
Recently, due to their abundant benefits, current-mode instrumentation amplifiers have received considerable attention in medical instrumentation and read-out circuit for biosensors. This paper is focused on the design of current-mode instrumentation amplifiers for portable, implantable, and wearable electrocardiography and electroencephalography applications. To this end, a CMOS differential voltage second-generation current conveyor (DVCCII) based on a linear transconductor is presented. A new band-pass instrumentation amplifier, based on the designed DVCCII, is also implemented in this paper. The concept of the proposed differential voltage current conveyor and instrumentation amplifier is validated numerically and their predicted performance is presented. The simulation results of the presented circuits were tested for 0.18 μm TSMC CMOS technology in a post layout simulation level using the Cadence Virtuoso tool with a ±0.9 V power supply, and demonstrated that the designed DVCCII has a wide dynamic range of ±400 mV and ±0.85 mA and a power consumption of 148 μW. The layout of the DVCCII circuit occupies a total area of 0.378 μm2. It is shown that the designed DVCCII benefits from good linearity over a wide range of input signals and provides a low input impedance at terminal X. Two versions of the proposed band-pass instrumentation amplifier using pseudo resistances were designed with different specifications for two different applications, namely for EEG and ECG signals. Numerical analyses of both designs show proper outputs and frequency responses by eliminating the undesired artifact and DC component of the EEG and ECG input signals. Full article
(This article belongs to the Special Issue Advanced Analog Circuits for Emerging Applications)
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Article
An 8-bit Radix-4 Non-Volatile Parallel Multiplier
Electronics 2021, 10(19), 2358; https://doi.org/10.3390/electronics10192358 - 27 Sep 2021
Cited by 1 | Viewed by 1396
Abstract
The data movement between the processing and storage units has been one of the most critical issues in modern computer systems. The emerging Resistive Random Access Memory (RRAM) technology has drawn tremendous attention due to its non-volatile ability and the potential in computation [...] Read more.
The data movement between the processing and storage units has been one of the most critical issues in modern computer systems. The emerging Resistive Random Access Memory (RRAM) technology has drawn tremendous attention due to its non-volatile ability and the potential in computation application. These properties make them a perfect choice for application in modern computing systems. In this paper, an 8-bit radix-4 non-volatile parallel multiplier is proposed, with improved computational capabilities. The corresponding booth encoding scheme, read-out circuit, simplified Wallace tree, and Manchester carry chain are presented, which help to short the delay of the proposed multiplier. While the presence of RRAM save computational time and overall power as multiplicand is stored beforehand. The area of the proposed non-volatile multiplier is reduced with improved computing speed. The proposed multiplier has an area of 785.2 μm2 with Generic Processing Design Kit 45 nm process. The simulation results show that the proposed multiplier structure has a low computing power at 161.19 μW and a short delay of 0.83 ns with 1.2 V supply voltage. Comparative analyses are performed to demonstrate the effectiveness of the proposed multiplier design. Compared with conventional booth multipliers, the proposed multiplier structure reduces the energy and delay by more than 70% and 19%, respectively. Full article
(This article belongs to the Special Issue Advanced Analog Circuits for Emerging Applications)
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Article
Miller Plateau Corrected with Displacement Currents and Its Use in Analyzing the Switching Process and Switching Loss
Electronics 2021, 10(16), 2013; https://doi.org/10.3390/electronics10162013 - 20 Aug 2021
Viewed by 1516
Abstract
This paper reveals the relationship between the Miller plateau voltage and the displacement currents through the gate–drain capacitance (CGD) and the drain–source capacitance (CDS) in the switching process of a power transistor. The corrected turn-on Miller plateau [...] Read more.
This paper reveals the relationship between the Miller plateau voltage and the displacement currents through the gate–drain capacitance (CGD) and the drain–source capacitance (CDS) in the switching process of a power transistor. The corrected turn-on Miller plateau voltage and turn-off Miller plateau voltage are different even with a constant current load. Using the proposed new Miller plateau, the turn-on and turn-off sequences can be more accurately analyzed, and the switching power loss can be more accurately predicted accordingly. Switching loss models based on the new Miller plateau have also been proposed. The experimental test result of the power MOSFET (NCE2030K) verified the relationship between the Miller plateau voltage and the displacement currents through CGD and CDS. A carefully designed verification test bench featuring a power MOSFET written in Verilog-A proved the prediction accuracy of the switching waveform and switching loss with the new proposed Miller plateau. The average relative error of the loss model using the new plateau is reduced to 1/2∼1/4 of the average relative error of the loss model using the old plateau; the proposed loss model using the new plateau, which also takes the gate current’s variation into account, further reduces the error to around 5%. Full article
(This article belongs to the Special Issue Advanced Analog Circuits for Emerging Applications)
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