# An 8-bit Radix-4 Non-Volatile Parallel Multiplier

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## Abstract

**:**

## 1. Introduction

## 2. Background and Related Work

#### 2.1. Resistive Non-Volatile Memory

#### 2.2. Booth Multiplier

## 3. Proposed 8-bit Non-Volatile Booth Multiplier

#### 3.1. Booth Encoding and Partial Product Generator

- 1.
- ‘−1A’ RRAM is LRS, others types are HRS;
- 2.
- ‘+1A’ RRAM is LRS, others types are HRS;
- 3.
- ‘−2A’ RRAM is LRS, others types are HRS;
- 4.
- ‘+2A’ RRAM is LRS, others types are HRS.

#### 3.2. Sign Bit

#### 3.3. Readout Circuit

#### 3.3.1. Current Sensing Circuit

#### 3.3.2. Latched Comparator

#### 3.4. Proposed Wallace Tree

#### 3.5. Manchester Carry Chain

#### 3.6. Structure of Partial Product Generator

## 4. Simulation Result and Comparison

#### 4.1. RRAM Circuit Simulation

#### 4.2. AD Circuit Simulation

#### 4.3. Multiplier Circuit Simulation

#### 4.3.1. Transient Simulation Analysis

#### 4.3.2. PVT Analysis

#### 4.4. Performance Analysis and Comparison

#### 4.5. System Power Comparison

## 5. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 2.**One-row and two-row multiplier circuits with relevant critical components. The proposed 8-bit radix-4 non-volatile parallel multiplier has two kinds of structures: one-row structure and two-row structure. Both two kinds of structures consist of partial product (PP) generator array, AD, simplified Wallace tree, and Manchester carry chain. (

**a**) Two-row structure of the proposed multiplier with 2 kinds of AD. (

**b**) One-row structure of the proposed multiplier with 4 kinds of AD. (

**c**) The key components of the Wallace tree including adders and compressors. (

**d**) The cell of partial product generator array. (

**e**) The read-out circuit (AD1.5b). AD contains the current sensing circuit and latched comparator. A two-phase non-overlap clock circuit is needed to generate gate signal Charge and Discharge.

**Figure 9.**Transient simulation of current sensing circuit considering different combinations of data inputs $A0$ and $A1$.

**Figure 10.**Transient simulation of AD1.5b considering different combinations of data inputs $A0$ and $A1$.

**Figure 11.**Transient simulation of an 8-bit radix-4 non-volatile parallel multiplier with multiplicator $B=00110011$.

**Figure 13.**The results of Monte Carlo analysis for total power of proposed two-row multiplier. (

**a**) ${V}_{dd}$ = 0.9 V. (

**b**) ${V}_{dd}$ = 1.0 V. (

**c**) ${V}_{dd}$ = 1.1 V. (

**d**) ${V}_{dd}$ = 1.2 V.

Shift & Add | Array Multiplier | Modified Booth Multiplier | Modified Booth Wallace Multiplier | |
---|---|---|---|---|

Serial/Parallel | Serial | Parallel | Parallel | Parallel |

Area | Small | Large | Medium | Medium |

Power Consumption | Small | Large | Medium | Medium |

Delay | Large | Medium | Small | Smallest |

Complexity | Simple | Simple | Complex | Complex |

Implementation | Easy | Easy | Medium | Difficult |

Type | ${\mathit{V}}_{\mathit{x}}\mathit{min}$ (mV) | One-Row | Two-Row | Coding |
---|---|---|---|---|

AD1b | 253 | 3 | 6 | 0,1 |

AD1.5b | 183 | 4 | 17 | 00,10,11 |

AD3b | 132 | 3 | 0 | 000,001,011,111 |

AD4b | 100 | 5 | 0 | 0000,0001,0011,0111,1111 |

${P}_{capacitance}$ ($\mathsf{\mu}$W) | 4.92 | 4.99 | - |

Resistance | X0 | X1 | Cin | S | Cout |
---|---|---|---|---|---|

$\frac{{R}_{H}}{4}$ | 0 | 0 | 0 | 0 | 0 |

$\frac{{R}_{H}}{4}$ | 0 | 0 | 1 | 1 | 0 |

/ | 0 | 1 | 0 | X | X |

/ | 0 | 1 | 1 | X | X |

$\frac{{R}_{H}}{3}//{R}_{L}$ | 1 | 0 | 0 | 1 | 0 |

$\frac{{R}_{H}}{3}//{R}_{L}$ | 1 | 0 | 1 | 0 | 1 |

$\frac{{R}_{H}}{2}//\frac{{R}_{L}}{2}$ | 1 | 1 | 0 | 0 | 1 |

$\frac{{R}_{H}}{2}//\frac{{R}_{L}}{2}$ | 1 | 1 | 1 | 1 | 1 |

Parameter | Description | Default Value |
---|---|---|

L | Oxide thickness | 5 nm |

gap_min | Min. gap distance | 0.1 nm |

gap_max | Max. gap distance | 1.7 nm |

gap_ini | Initial gap distance | 1.367 nm |

a0 | Atomic distance | 0.25 nm |

Eag | Activation energy for vacancy generation | 1.501 eV |

Ear | Activation energy for vacancy recombination | 1.5 eV |

I0 | I-V fitting parameter | $3\times {10}^{-5}$ |

g0 | I-V fitting parameter | $1.8819\times {10}^{-10}$ |

V0 | I-V fitting parameter | 4.3 |

${v}_{0}$ | Gap dynamics fitting parameter | 150 |

${\gamma}_{0}$ | Gap dynamics fitting parameter | 16.5 |

${g}_{1}$ | Gap dynamics fitting parameter | $1\times {10}^{-9}$ |

$\beta $ | Gap dynamics fitting parameter | 1.25 |

Process | MC | FF | SS |
---|---|---|---|

Average Current ($\mathsf{\mu}$A) | 89.8 | 134.0 | 75.4 |

Delay (ns) | 1.05 | 0.90 | 1.38 |

Process (nm) | ${\mathit{V}}_{\mathbf{dd}}$ (V) | Delay (ns) | Power ($\mathsf{\mu}$W) | PDP (fJ) | Area ($\mathsf{\mu}$m${}^{2}$) | Memory | PDP Save (%) | ||
---|---|---|---|---|---|---|---|---|---|

[44] | 90 | 1.2 | 1.04 | 435.9 | 453 | – | regular CMOS | 0 | |

[3] | 65 | 1.2 | 1.03 | 335 | 345.05 | 738.23 | RRAM | 23 | |

[45] | 65 | 1.32 | 1.04 | 358 | 372 | 749.12 | regular CMOS | 17 | |

[46] | 180 | 1.2 | – | 1200 | – | – | RRAM | – | |

Proposed | two-row | 45 | 1.2 | 0.83 | 161.19 | 133.80 | 785.20 | RRAM | 70 |

one-row | 45 | 1.2 | 0.83 | 135.72 | 112.65 | 749.61 | RRAM | 75 | |

two-row | 45 | 1 | 1.05 | 87.25 | 91.52 | 785.20 | RRAM | 79 | |

two-row | 45 | 1 | 1.05 | 79.19 | 83.15 | 749.61 | RRAM | 81 |

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**MDPI and ACS Style**

Fu, C.; Zhu, X.; Huang, K.; Gu, Z. An 8-bit Radix-4 Non-Volatile Parallel Multiplier. *Electronics* **2021**, *10*, 2358.
https://doi.org/10.3390/electronics10192358

**AMA Style**

Fu C, Zhu X, Huang K, Gu Z. An 8-bit Radix-4 Non-Volatile Parallel Multiplier. *Electronics*. 2021; 10(19):2358.
https://doi.org/10.3390/electronics10192358

**Chicago/Turabian Style**

Fu, Chengjie, Xiaolei Zhu, Kejie Huang, and Zheng Gu. 2021. "An 8-bit Radix-4 Non-Volatile Parallel Multiplier" *Electronics* 10, no. 19: 2358.
https://doi.org/10.3390/electronics10192358