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Computers
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Reconfigurable Computing Technologies and Applications
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Reconfigurable Computing Technologies and Applications

A special issue of Computers (ISSN 2073-431X).

Deadline for manuscript submissions: closed (1 July 2018) | Viewed by 50109

Special Issue Editors

Dr. Neil Bergmann

E-Mail Website
Guest Editor
School of Information Technology and Electrical Engineering, The University of Queensland, Sir Fred Schonell Drive, St Lucia, Brisbane, QLD 4072, Australia
Interests: reconfigurable computing; sensor networks; Internet of Things
Special Issues, Collections and Topics in MDPI journals
Associate Professor Paul Beckett

E-Mail Website
Guest Editor
School of Electrical and Biomedical Engineering, RMIT University, Melbourne, Australia
Interests: emerging technologies – nanoscale computer architecture; high performance digital logic design; embedded computer architecture; programmable logic synthesis; hardware description languages; VLSI design

Special Issue Information

Dear Colleagues,

Reconfigurable computing bridges the gap between general purpose computers, in which function is determined by software, and Application Specific Integrated Circuits (ASICs), in which single specific functions are built using custom hardware. Reconfigurable computers are built around a set of programmable hardware primitives and a set of programmable interconnection networks. For fine-grained reconfigurable computers, such as FPGAs, the processing elements are logic gates and interconnection networks are switches and wires. For coarse-grained reconfigurable computers, the processing elements are software-configurable processors, and the interconnections use a programmable network-on-chip. Heterogeneous reconfigurable computers combine elements, such as conventional general purpose processors, ASIC elements, such as memories and DSP blocks, and fine-grained programmable logic elements.

 

This Special Issue is interested in compelling new research results that extend knowledge in all of these areas of reconfigurable computing. Topics include:

  • Devices and Technologies for Reconfigurable Computing
  • Architectures for Reconfigurable Computing
  • Tools and Design Techniques for Reconfigurable Computing
  • Novel Applications of Reconfigurable Computing
  • Surveys and Tutorials of Reconfigurable Computing
  • Education for Reconfigurable Computing

Note that simply implementing a particular application on a reconfigurable computing platform may be good engineering, but is seldom novel research. Applications-based papers especially must emphasize the research contribution of the work.

 

This Special Issue also specifically invites extended versions of conference papers presented at the "2017 International Conference on Field-Programmable Technology".

 

Professor Neil Bergmann
Associate Professor Paul Beckett
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Computers is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • reconfigurable computing
  • field programmable technologies
  • field programmable gate arrays
  • FPGAs
  • design automation

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Published Papers (6 papers)

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Research

36 pages, 1347 KiB  
Article
Automatic Configurable Hardware Code Generation for Software-Defined Radios
by Lekhobola Tsoeunyane, Simon Winberg and Michael Inggs
Computers 2018, 7(4), 53; https://doi.org/10.3390/computers7040053 - 19 Oct 2018
Viewed by 5773
Abstract
The development of software-defined radio (SDR) systems using field-programmable gate arrays (FPGAs) compels designers to reuse pre-existing Intellectual Property (IP) cores in order to meet time-to-market and design efficiency requirements. However, the low-level development difficulties associated with FPGAs hinder productivity, even when the [...] Read more.
The development of software-defined radio (SDR) systems using field-programmable gate arrays (FPGAs) compels designers to reuse pre-existing Intellectual Property (IP) cores in order to meet time-to-market and design efficiency requirements. However, the low-level development difficulties associated with FPGAs hinder productivity, even when the designer is experienced with hardware design. These low-level difficulties include non-standard interfacing methods, component communication and synchronization challenges, complicated timing constraints and processing blocks that need to be customized through time-consuming design tweaks. In this paper, we present a methodology for automated and behavioral integration of dedicated IP cores for rapid prototyping of SDR applications. To maintain high performance of the SDR designs, our methodology integrates IP cores using characteristics of the dataflow model of computation (MoC), namely the static dataflow with access patterns (SDF-AP). We show how the dataflow is mapped onto the low-level model of hardware by efficiently applying low-level based optimizations and using a formal analysis technique that guarantees the correctness of the generated solutions. Furthermore, we demonstrate the capability of our automated hardware design approach by developing eight SDR applications in VHDL. The results show that well-optimized designs are generated and that this can improve productivity while also conserving the hardware resources used. Full article
(This article belongs to the Special Issue Reconfigurable Computing Technologies and Applications)
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34 pages, 5614 KiB  
Article
Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC
by Dimple Sharma, Lev Kirischian and Valeri Kirischian
Computers 2018, 7(4), 52; https://doi.org/10.3390/computers7040052 - 11 Oct 2018
Cited by 4 | Viewed by 5207
Abstract
Systems for application domains like robotics, aerospace, defense, autonomous vehicles, etc. are usually developed on System-on-Programmable Chip (SoPC) platforms, capable of supporting several multi-modal computation-intensive tasks on their FPGAs. Since such systems are mostly autonomous and mobile, they have rechargeable power sources and [...] Read more.
Systems for application domains like robotics, aerospace, defense, autonomous vehicles, etc. are usually developed on System-on-Programmable Chip (SoPC) platforms, capable of supporting several multi-modal computation-intensive tasks on their FPGAs. Since such systems are mostly autonomous and mobile, they have rechargeable power sources and therefore, varying power budgets. They may also develop hardware faults due to radiation, thermal cycling, aging, etc. Systems must be able to sustain the performance requirements of their multi-task multi-modal workload in the presence of variations in available power or occurrence of hardware faults. This paper presents an approach for mitigating power budget variations and hardware faults (transient and permanent) by run-time structural adaptation of the SoPC. The proposed method is based on dynamically allocating, relocating and re-integrating task-specific processing circuits inside the partially reconfigurable FPGA to accommodate the available power budget, satisfy tasks’ performances and hardware resource constraints, and/or to restore task functionality affected by hardware faults. The proposed method has been experimentally implemented on the ARM Cortex-A9 processor of Xilinx Zynq XC7Z020 FPGA. Results have shown that structural adaptation can be done in units of milliseconds since the worst-case decision-making process does not exceed the reconfiguration time of a partial bit-stream. Full article
(This article belongs to the Special Issue Reconfigurable Computing Technologies and Applications)
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20 pages, 2135 KiB  
Article
An Analytical Comparison of Locally-Connected Reconfigurable Neural Network Architectures Using a C. elegans Locomotive Model
by Jonathan Graham-Harper-Cater, Benjamin Metcalfe and Peter Wilson
Computers 2018, 7(3), 43; https://doi.org/10.3390/computers7030043 - 15 Aug 2018
Cited by 1 | Viewed by 6214
Abstract
The scale of modern neural networks is growing rapidly, with direct hardware implementations providing significant speed and energy improvements over their software counterparts. However, these hardware implementations frequently assume global connectivity between neurons and thus suffer from communication bottlenecks. Such issues are not [...] Read more.
The scale of modern neural networks is growing rapidly, with direct hardware implementations providing significant speed and energy improvements over their software counterparts. However, these hardware implementations frequently assume global connectivity between neurons and thus suffer from communication bottlenecks. Such issues are not found in biological neural networks. It should therefore be possible to develop new architectures to reduce the dependence on global communications by considering the connectivity of biological networks. This paper introduces two reconfigurable locally-connected architectures for implementing biologically inspired neural networks in real time. Both proposed architectures are validated using the segmented locomotive model of the C. elegans, performing a demonstration of forwards, backwards serpentine motion and coiling behaviours. Local connectivity is discovered to offer up to a 17.5× speed improvement over hybrid systems that use combinations of local and global infrastructure. Furthermore, the concept of locality of connections is considered in more detail, highlighting the importance of dimensionality when designing neuromorphic architectures. Convolutional Neural Networks are shown to map poorly to locally connected architectures despite their apparent local structure, and both the locality and dimensionality of new neural processing systems is demonstrated as a critical component for matching the function and efficiency seen in biological networks. Full article
(This article belongs to the Special Issue Reconfigurable Computing Technologies and Applications)
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29 pages, 1150 KiB  
Article
FPGA-Based Architectures for Acoustic Beamforming with Microphone Arrays: Trends, Challenges and Research Opportunities
by Bruno Da Silva, An Braeken and Abdellah Touhafi
Computers 2018, 7(3), 41; https://doi.org/10.3390/computers7030041 - 3 Aug 2018
Cited by 12 | Viewed by 15741
Abstract
Over the past decades, many systems composed of arrays of microphones have been developed to satisfy the quality demanded by acoustic applications. Such microphone arrays are sound acquisition systems composed of multiple microphones used to sample the sound field with spatial diversity. The [...] Read more.
Over the past decades, many systems composed of arrays of microphones have been developed to satisfy the quality demanded by acoustic applications. Such microphone arrays are sound acquisition systems composed of multiple microphones used to sample the sound field with spatial diversity. The relatively recent adoption of Field-Programmable Gate Arrays (FPGAs) to manage the audio data samples and to perform the signal processing operations such as filtering or beamforming has lead to customizable architectures able to satisfy the most demanding computational, power or performance acoustic applications. The presented work provides an overview of the current FPGA-based architectures and how FPGAs are exploited for different acoustic applications. Current trends on the use of this technology, pending challenges and open research opportunities on the use of FPGAs for acoustic applications using microphone arrays are presented and discussed. Full article
(This article belongs to the Special Issue Reconfigurable Computing Technologies and Applications)
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23 pages, 9150 KiB  
Article
Phase Calibrated Ring Oscillator PUF Design and Application
by Wei Yan and John Chandy
Computers 2018, 7(3), 40; https://doi.org/10.3390/computers7030040 - 26 Jul 2018
Cited by 2 | Viewed by 7932
Abstract
A Ring Oscillator Physical Unclonable Function (RO PUF) is an application-constrained hardware security primitive that can be used for authentication and key generation. PUFs depend on variability during the fabrication process to produce random outputs that are nevertheless stable across multiple measurements. Though [...] Read more.
A Ring Oscillator Physical Unclonable Function (RO PUF) is an application-constrained hardware security primitive that can be used for authentication and key generation. PUFs depend on variability during the fabrication process to produce random outputs that are nevertheless stable across multiple measurements. Though industry has a growing need for PUF implementations on Field Programmable Gate Arrays (FPGA) and Application-Specific Integrated Circuits (ASIC), the bit errors in PUF responses become a bottleneck and limit the usage. In this work, we comprehensively evaluate the RO PUF’s stability on FPGAs, and we propose a phase calibration process to improve the stability of RO PUFs. We also make full use of the instability of PUFs to provide a novel solution for authentication. The results show that the bit errors in our PUFs are reduced to less than 1%. Full article
(This article belongs to the Special Issue Reconfigurable Computing Technologies and Applications)
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28 pages, 8680 KiB  
Article
Comparing the Cost of Protecting Selected Lightweight Block Ciphers against Differential Power Analysis in Low-Cost FPGAs
by William Diehl, Abubakr Abdulgadir, Jens-Peter Kaps and Kris Gaj
Computers 2018, 7(2), 28; https://doi.org/10.3390/computers7020028 - 23 Apr 2018
Cited by 10 | Viewed by 8020
Abstract
Lightweight block ciphers are an important topic in the Internet of Things (IoT) since they provide moderate security while requiring fewer resources than the Advanced Encryption Standard (AES). Ongoing cryptographic contests and standardization efforts evaluate lightweight block ciphers on their resistance to power [...] Read more.
Lightweight block ciphers are an important topic in the Internet of Things (IoT) since they provide moderate security while requiring fewer resources than the Advanced Encryption Standard (AES). Ongoing cryptographic contests and standardization efforts evaluate lightweight block ciphers on their resistance to power analysis side channel attack (SCA), and the ability to apply countermeasures. While some ciphers have been individually evaluated, a large-scale comparison of resistance to side channel attack and the formulation of absolute and relative costs of implementing countermeasures is difficult, since researchers typically use varied architectures, optimization strategies, technologies, and evaluation techniques. In this research, we leverage the Test Vector Leakage Assessment (TVLA) methodology and the FOBOS SCA framework to compare FPGA implementations of AES, SIMON, SPECK, PRESENT, LED, and TWINE, using a choice of architecture targeted to optimize throughput-to-area (TP/A) ratio and suitable for introducing countermeasures to Differential Power Analysis (DPA). We then apply an equivalent level of protection to the above ciphers using 3-share threshold implementations (TI) and verify the improved resistance to DPA. We find that SIMON has the highest absolute TP/A ratio of protected versions, as well as the lowest relative cost of protection in terms of TP/A ratio. Additionally, PRESENT uses the least energy per bit (E/bit) of all protected implementations, while AES has the lowest relative cost of protection in terms of increased E/bit. Full article
(This article belongs to the Special Issue Reconfigurable Computing Technologies and Applications)
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