Special Issue "Silicon Nanowires and Their Applications"

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Nanotechnology and Applied Nanosciences".

Deadline for manuscript submissions: closed (30 June 2019).

Special Issue Editors

Prof. Dr. Qing-Tai Zhao
Website
Guest Editor
Peter Grünberg Institute 9, Forschungszentrum Jülich, Jülich 52425, Germany
Interests: semiconductor devices; electronic materials
Prof. Dr. Steffen Strehle
Website
Guest Editor
Microsystems Technology, Technische Universität Ilmenau, Germany (Image: © E. Eberhardt, Ulm University)
Interests: bottom-up synthesis and properties of nanostructures; advanced nanowire device fabrication; nanowire sensors & electron devices; nanostructured semiconductor surfaces for photocatalytic applications

Special Issue Information

Dear Colleagues,

We invite you to contribute to a Special Issue of the journal Applied Sciences, "Silicon Nanowires and Their Applications", which aims to present recent advances in the investigation silicon nanowires (SiNWs) and SiNW-based devices including also fabrication strategies, SiNW characterization, and theoretical studies.

SiNWs provide a unique set of material and morphological properties comprising 1D transport phenomena and a high surface to volume ratio that enable a broad spectrum of applications. The enhanced electrostatics in SiNW devices offers for instance the possibility to scale field effect transistors (FETs) down to <10 nm following Moor's law. In addition, TFETs, which are based on band to band tunnelling and thus break the subthreshold slope limit of 60 mV/dec at 300 K in MOSFETs, can be significantly improved by utilizing wrapped gate SiNW configurations. Multiple applications were also demonstrated in the fields of chemical, biochemical and biological sensing ranging from ion-sensitive FETs and vertical electrode arrays to nanoscale injectable probes. SiNWs can be furthermore implemented in photonic and quantum computing devices. The compatibility with well-established CMOS microfabrication technologies supports here not only the overall device assembly but enables also possibilities of a simultaneous integration of photonics and electronics, or qubits and traditional control devices/circuits on the same platform. For thermo-electric applications, SiNWs promise significant enhancements in thermoelectric efficiency with low thermal conductivity. Furthermore, SiNWs show advantages in energy generation and storage: for example, to improve the properties of Lithium-ion battery anodes and solar cells. Other aspects and applications of SiNWs, besides the examples listed above, are also very welcome.

Prof. Qing-Tai Zhao
Prof. Steffen Strehle
Guest Editors

Manuscript Submission Information

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Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2000 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Si nanowire

  • 1D transport

  • Electrostatics

  • Field effect transistor

  • Fabrication

  • Quantum computing

  • Sensor

  • Thermo-electrics

  • Battery

  • Photovoltaics

Published Papers (10 papers)

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Research

Open AccessArticle
Spin Qubits Confined to a Silicon Nano-Ridge
Appl. Sci. 2019, 9(18), 3823; https://doi.org/10.3390/app9183823 - 12 Sep 2019
Abstract
Electrostatically-defined quantum dots (QDs) in silicon are an attractive platform for quantum computation. Localized single electron spins define qubits and provide excellent manipulation and read-out fidelities. We propose a scalable silicon-based qubit device that can be fabricated by industry-compatible processes. The device consists [...] Read more.
Electrostatically-defined quantum dots (QDs) in silicon are an attractive platform for quantum computation. Localized single electron spins define qubits and provide excellent manipulation and read-out fidelities. We propose a scalable silicon-based qubit device that can be fabricated by industry-compatible processes. The device consists of a dense array of QDs localized along an etched silicon nano-ridge. Due to its lateral confinement, a simple dense array of metallic top-gates forms an array of QDs with controllable tunnel-couplings. To avoid potential fluctuations because of roughness and charged defects at the nano-ridge sidewall, the cross-section of the nano-ridge is trapezoidal and bounded by atomically-flat {111} facets. In addition to side-gates on top of the low-defect oxidized {111} facets, we implement a global back-gate facilitated by the use of silicon-on-insulator. The most relevant process modules are demonstrated experimentally including anisotropic wet-etching and local oxidation of the silicon nano-ridge, side-gate formation with chemical-mechanical polishing, and top-gate fabrication employing the spacer process. According to electrostatic simulations, our device concept allows forming capacitively-coupled QD double-arrays or adjacent charge detectors for spin-readout. Defining a logical qubit or realizing a single electron conveyor for mid-range qubit-coupling will be future applications. Full article
(This article belongs to the Special Issue Silicon Nanowires and Their Applications)
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Open AccessFeature PaperArticle
Towards Reconfigurable Electronics: Silicidation of Top-Down Fabricated Silicon Nanowires
Appl. Sci. 2019, 9(17), 3462; https://doi.org/10.3390/app9173462 - 22 Aug 2019
Cited by 3
Abstract
We present results of our investigations on nickel silicidation of top-down fabricated silicon nanowires (SiNWs). Control over the silicidation process is important for the application of SiNWs in reconfigurable field-effect transistors. Silicidation is performed using a rapid thermal annealing process on the SiNWs [...] Read more.
We present results of our investigations on nickel silicidation of top-down fabricated silicon nanowires (SiNWs). Control over the silicidation process is important for the application of SiNWs in reconfigurable field-effect transistors. Silicidation is performed using a rapid thermal annealing process on the SiNWs fabricated by electron beam lithography and inductively-coupled plasma etching. The effects of variations in crystallographic orientations of SiNWs and different NW designs on the silicidation process are studied. Scanning electron microscopy and transmission electron microscopy are performed to study Ni diffusion, silicide phases, and silicide–silicon interfaces. Control over the silicide phase is achieved together with atomically sharp silicide–silicon interfaces. We find that {111} interfaces are predominantly formed, which are energetically most favorable according to density functional theory calculations. However, control over the silicide length remains a challenge. Full article
(This article belongs to the Special Issue Silicon Nanowires and Their Applications)
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Open AccessArticle
Comparison of Various Factors Affected TID Tolerance in FinFET and Nanowire FET
Appl. Sci. 2019, 9(15), 3163; https://doi.org/10.3390/app9153163 - 03 Aug 2019
Cited by 2
Abstract
Analysis of the radiation effects in a device is of great importance. The gate all around (GAA) structure that contributes to device scaling not only solves the short channel effects (SCE) problem but also makes the device more resistant in radiation environments. In [...] Read more.
Analysis of the radiation effects in a device is of great importance. The gate all around (GAA) structure that contributes to device scaling not only solves the short channel effects (SCE) problem but also makes the device more resistant in radiation environments. In this article, the total ionizing dose (TID) simulation of nanowire FET (NW) and FinFET was performed. Both these devices were compared and analyzed in terms of the shift of threshold voltage (VT). The channel insulator was composed of two materials, SiO2 and HfO2. To improve the accuracy of the simulation, the interfacial trap parameter of SiO2 and HfO2 was applied. Based on the simulation result, the NW with a larger oxide area and larger gate controllability showed less VT shift than that of the FinFET. It was therefore proved that NW had better TID resistance characteristics in a radiation environment. The gate controllability was found to affect the TID effect more than the oxide area. In addition, we analyzed the manner in which the TID effect changed depending on the VDD and channel doping. Full article
(This article belongs to the Special Issue Silicon Nanowires and Their Applications)
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Open AccessArticle
Comprehensive Study of Cross-Section Dependent Effective Masses for Silicon Based Gate-All-Around Transistors
Appl. Sci. 2019, 9(9), 1895; https://doi.org/10.3390/app9091895 - 08 May 2019
Cited by 7
Abstract
The use of bulk effective masses in simulations of the modern-day ultra-scaled transistor is erroneous due to the strong dependence of the band structure on the cross-section dimensions and shape. This has to be accounted for in transport simulations due to the significant [...] Read more.
The use of bulk effective masses in simulations of the modern-day ultra-scaled transistor is erroneous due to the strong dependence of the band structure on the cross-section dimensions and shape. This has to be accounted for in transport simulations due to the significant impact of the effective masses on quantum confinement effects and mobility. In this article, we present a methodology for the extraction of the electron effective masses, in both confinement and the transport directions, from the simulated electronic band structure of the nanowire channel. This methodology has been implemented in our in-house three-dimensional (3D) simulation engine, NESS (Nano-Electronic Simulation Software). We provide comprehensive data for the effective masses of the silicon-based nanowire transistors (NWTs) with technologically relevant cross-sectional area and transport orientations. We demonstrate the importance of the correct effective masses by showing its impact on mobility and transfer characteristics. Full article
(This article belongs to the Special Issue Silicon Nanowires and Their Applications)
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Open AccessFeature PaperArticle
The Electronic Properties of Silicon Nanowires during Their Dissolution under Simulated Physiological Conditions
Appl. Sci. 2019, 9(4), 804; https://doi.org/10.3390/app9040804 - 25 Feb 2019
Abstract
Silicon nanowires are considered promising future biomedical sensors. However, their limited stability under physiological conditions poses a challenge in sensor development and necessitates a significantly improved knowledge of underlying effects as well as new solutions to enhance silicon nanowire durability. In the present [...] Read more.
Silicon nanowires are considered promising future biomedical sensors. However, their limited stability under physiological conditions poses a challenge in sensor development and necessitates a significantly improved knowledge of underlying effects as well as new solutions to enhance silicon nanowire durability. In the present study, we deduced the dissolution rates of silicon nanowires under simulated physiological conditions from atomic force microscopy measurements. We correlated the relevant change in nanowire diameter to changes in the electronic properties by examining the I-V characteristics of kinked silicon nanowire p–n junctions. Contact potential difference measurements and ambient pressure photoemission spectroscopy additionally gave insights into the electronic surface band structure. During the first week of immersion, the Fermi level of n-type silicon nanowires shifted considerably to higher energies, partly even above the conduction band edge, which manifested in an increased conductivity. After about a week, the Fermi level stabilized and the conductivity decreased consistently with the decreasing diameter caused by continuous nanowire dissolution. Our results show that a physiological environment can substantially affect the surface band structure of silicon nanowire devices, and with it, their electronic properties. Therefore, it is necessary to study these effects and find strategies to gain reliable biomedical sensors. Full article
(This article belongs to the Special Issue Silicon Nanowires and Their Applications)
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Open AccessArticle
High Performance GAA SNWT with a Triangular Cross Section: Simulation and Experiments
Appl. Sci. 2018, 8(9), 1553; https://doi.org/10.3390/app8091553 - 04 Sep 2018
Cited by 3
Abstract
In this paper, we present a gate-all-around silicon nanowire transistor (GAA SNWT) with a triangular cross section by simulation and experiments. Through the TCAD simulation, it was found that with the same nanowire width, the triangular cross-sectional SNWT was superior to the circular [...] Read more.
In this paper, we present a gate-all-around silicon nanowire transistor (GAA SNWT) with a triangular cross section by simulation and experiments. Through the TCAD simulation, it was found that with the same nanowire width, the triangular cross-sectional SNWT was superior to the circular or quadrate one in terms of the subthreshold swing, on/off ratio, and SCE immunity, which resulted from the smallest equivalent distance from the nanowire center to the surface in triangular SNWTs. Following this, we fabricated triangular cross-sectional GAA SNWTs with a nanowire width down to 20 nm by TMAH wet etching. This process featured its self-stopped etching behavior on a silicon (1 1 1) crystal plane, which made the triangular cross section smooth and controllable. The fabricated triangular SNWT showed an excellent performance with a large Ion/Ioff ratio (~107), low SS (85 mV/dec), and preferable DIBL (63 mV/V). Finally, the surface roughness mobility of the fabricated device at a low temperature was also extracted to confirm the benefit of a stable cross section. Full article
(This article belongs to the Special Issue Silicon Nanowires and Their Applications)
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Open AccessArticle
Gating Hysteresis as an Indicator for Silicon Nanowire FET Biosensors
Appl. Sci. 2018, 8(6), 950; https://doi.org/10.3390/app8060950 - 08 Jun 2018
Cited by 10
Abstract
We present a biosensor chip with integrated large area silicon nanowire-based field effect transistors (FET) for human α-thrombin detection and propose to implement the hysteresis width of the FET transfer curve as a reliable parameter to quantify the concentration of biomolecules in the [...] Read more.
We present a biosensor chip with integrated large area silicon nanowire-based field effect transistors (FET) for human α-thrombin detection and propose to implement the hysteresis width of the FET transfer curve as a reliable parameter to quantify the concentration of biomolecules in the solution. We further compare our results to conventional surface potential based measurements and demonstrate that both parameters distinctly respond at a different analyte concentration range. A combination of the two approaches would provide broader possibilities for detecting biomolecules that are present in a sample with highly variable concentrations, or distinct biomolecules that can be found at very different levels. Finally, we qualitatively discuss the physical and chemical origin of the hysteresis signal and associate it with the polarization of thrombin molecules upon binding to the receptor at the nanowire surface. Full article
(This article belongs to the Special Issue Silicon Nanowires and Their Applications)
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Open AccessArticle
Tensile Strength of Silicon Nanowires Batch-Fabricated into Electrostatic MEMS Testing Device
Appl. Sci. 2018, 8(6), 880; https://doi.org/10.3390/app8060880 - 28 May 2018
Cited by 10
Abstract
The tensile strength of a silicon nanowire (SiNW) that had been integrated into a silicon-on-insulator (SOI)-based microelectromechanical system (MEMS) device was measured using electrostatic actuation and sensing. SiNWs of about 150 nm diameter and 5 μm length were batch-fabricated into a 5-μm-thick SOI [...] Read more.
The tensile strength of a silicon nanowire (SiNW) that had been integrated into a silicon-on-insulator (SOI)-based microelectromechanical system (MEMS) device was measured using electrostatic actuation and sensing. SiNWs of about 150 nm diameter and 5 μm length were batch-fabricated into a 5-μm-thick SOI device layer. Since there was no interface between the SiNW and the MEMS device and the alignment was perfect, the SiNW integration into an SOI-MEMS was expected to be useful for developing highly sensitive biochemical sensors or highly reliable torsional mirror devices. The SiNW was tensile tested using the electrostatic MEMS testing device. The integration was achieved using a combination of anisotropic and an isotropic dry etching of silicon, with an inductively coupled plasma reactive ion etching. A fabricated silicon beam of 800 nm square was thinned by a sacrificial oxidation process. The tensile strength of the wire was 2.6–4.1 GPa, which was comparable to that of microscale silicon MEMS structures. The reliability of such a thin device was successfully verified for future applications of the device structures. Full article
(This article belongs to the Special Issue Silicon Nanowires and Their Applications)
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Open AccessFeature PaperArticle
Strained Silicon Single Nanowire Gate-All-Around TFETs with Optimized Tunneling Junctions
Appl. Sci. 2018, 8(5), 670; https://doi.org/10.3390/app8050670 - 26 Apr 2018
Cited by 5
Abstract
In this work, we demonstrate a strained Si single nanowire tunnel field effect transistor (TFET) with gate-all-around (GAA) structure yielding Ion-current of 15 μA/μm at the supply voltage of Vdd = 0.5V with linear onset at low drain voltages. The [...] Read more.
In this work, we demonstrate a strained Si single nanowire tunnel field effect transistor (TFET) with gate-all-around (GAA) structure yielding Ion-current of 15 μA/μm at the supply voltage of Vdd = 0.5V with linear onset at low drain voltages. The subthreshold swing (SS) at room temperature shows an average of 76 mV/dec over 4 orders of drain current Id from 5 × 10−6 to 5 × 10−2 µA/µm. Optimized devices also show excellent current saturation, an important feature for analog performance. Full article
(This article belongs to the Special Issue Silicon Nanowires and Their Applications)
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Open AccessArticle
Correlation between the Golden Ratio and Nanowire Transistor Performance
Appl. Sci. 2018, 8(1), 54; https://doi.org/10.3390/app8010054 - 02 Jan 2018
Cited by 1
Abstract
An observation was made in this research regarding the fact that the signatures of isotropic charge distributions in silicon nanowire transistors (NWT) displayed identical characteristics to the golden ratio (Phi). In turn, a simulation was conducted regarding ultra-scaled n-type Si (NWT) with respect [...] Read more.
An observation was made in this research regarding the fact that the signatures of isotropic charge distributions in silicon nanowire transistors (NWT) displayed identical characteristics to the golden ratio (Phi). In turn, a simulation was conducted regarding ultra-scaled n-type Si (NWT) with respect to the 5-nm complementary metal-oxide-semiconductor (CMOS) application. The results reveal that the amount of mobile charge in the channel and intrinsic speed of the device are determined by the device geometry and could also be correlated to the golden ratio (Phi). This paper highlights the issue that the optimization of NWT geometry could reduce the impact of the main sources of statistical variability on the Figure of Merit (FoM) of devices. In the context of industrial early successes in fabricating vertically stacked NWT, ensemble Monte Carlo (MC) simulations with quantum correction are used to accurately predict the drive current. This occurs alongside a consideration of the degree to which the carrier transport in the vertically stacked lateral NWTs are complex. Full article
(This article belongs to the Special Issue Silicon Nanowires and Their Applications)
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