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Applied Sciences
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RF Front-End Circuit and Device for 5G/4G LTE
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RF Front-End Circuit and Device for 5G/4G LTE

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Optics and Lasers".

Deadline for manuscript submissions: closed (15 October 2021) | Viewed by 7639

Special Issue Editors

Dr. Heesauk Jhon

E-Mail Website
Guest Editor
Department of Electrical, Information and Communication Engineering, Mokpo National University, Mokpo 530729, Korea
Interests: electrical & electronics engineering
Dr. Min-Su Kim

E-Mail Website
Guest Editor
Department of Digital Electronics, Daelim University College, 29 Imgoklo, Dongan-gu, Anyang-si, Gyunggi-do 431-715, Korea
Interests: mixed/analog cmos process; symmetric; helical inductor; voltage-controlled oscillator; vco; phase noise

Special Issue Information

Dear Colleagues,

The continuous growth and adoption of smartphone access to voice and data services for billions of people worldwide and the explosive requirement for high data rates are driving the adoption of 4G/5G long-term evolution (LTE) and WiFi6. 5G will give higher data capacity and low latency using sub-6GHz bands and mmWave spectrum together with other RF technologies such as ultra-wideband (UWB) and sensing and computation techniques will enable multiple services. 4G/5G LTE basically requires more RF carries compared to the legacy voice (2G/3G), so there is an important challenge for RF front-end (RFFE) in terms of what parts of the RF systems are portioned in advanced CMOS nodes and what RF and analog blocks are integrated with other components such as acoustic duplexers and filters (FBAR, SAW, and BAW) in multiple modules (RF FEMs). This Special Issue of Applied Sciences will present an in-depth discussion of new devices and technologies for RF front-ends toward 4G/5G-LTE with WiFi6 that will have an impact on the electronics world in the next decade. Papers are solicited on next-generation RF front-end architectures, RF devices such as high-speed CMOS, HBT and GaN, LNAs (low noise amplifier), switches,  power amplifiers (PAs), package technologies, and any other technology that can take up the challenges of RFFE for 4G/5G-LTE. Topics of interest include, but are not limited to the following:

  • Design, modeling, simulation, and reliability of high-speed RF devices (sub-10nm MOSFET, FinFET, nanowire, nanoplate, HBT, GaN, etc.)
  • Design, modeling, simulation, and reliability of high-speed RF front-end circuits (LNA, Switch, filter, Power amplifier, etc.)
  • Design, modeling, simulation, and reliability of RF front-end analog and digital circuits (DC-to-DC converter, MIPI, regulator, etc.)
  • Applications of RFFE with new system architecture
  • RFFE package techniques and PCB design, modeling, simulation, and reliability analysis

Dr. Heesauk Jhon
Dr. Min-Su Kim
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Applied Sciences is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Design, modeling, simulation, and reliability of high-speed RF devices (sub-10nm MOSFET, FinFET, nanowire, nanoplate, HBT, GaN etc.
  • Design, modeling, simulation, and reliability of high-speed RF front-end circuits (LNA, switch, filter, power amplifier and antenna, etc.)
  • Design, modeling, simulation, and reliability of RF front-end analog and digital circuits (DC-to-DC converter, MIPI, regulator, etc.)
  • Applications of RFFE with new system architecture
  • RFFE package techniques and PCB design, modeling, simulation, and reliability analysis
  • RF transceiver and receiver design, simulation, and reliability for 4G/5G LTE in sub-6GHz, New Radio (NR), 28GHz, and millimeter-wave frequency ranges

Published Papers (3 papers)

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Research

15 pages, 1392 KiB  
Article
A Weighted Linearization Method for Highly RF-PA Nonlinear Behavior Based on the Compression Region Identification
by Jose Alejandro Galaviz-Aguilar, Cesar Vargas-Rosales, José Ricardo Cárdenas-Valdez, Yasmany Martínez-Reyes, Everardo Inzunza-González, Yuma Sandoval-Ibarra and José Cruz Núñez-Pérez
Appl. Sci. 2021, 11(7), 2942; https://doi.org/10.3390/app11072942 - 25 Mar 2021
Cited by 4 | Viewed by 2422
Abstract
In this paper, we present an adaptive modeling and linearization algorithm using the weighted memory polynomial model (W-MPM) implemented in a chain involving the indirect learning approach (ILA) as a linearization technique. The main aim of this paper is to offer an alternative [...] Read more.
In this paper, we present an adaptive modeling and linearization algorithm using the weighted memory polynomial model (W-MPM) implemented in a chain involving the indirect learning approach (ILA) as a linearization technique. The main aim of this paper is to offer an alternative to correcting the undesirable effect of spectral regrowth based on modeling and linearization stages, where the 1-dB compression point (P1dB) of a nonlinear device caused by memory effects within a short time is considered. The obtained accuracy is tested for a highly nonlinear behavior power amplifier (PA) properly measured using a field-programmable gate array (FPGA) system. The adaptive modeling stage shows, for the two PAs under test, performances with accuracies of −32.72 dB normalized mean square error (NMSE) using the memory polynomial model (MPM) compared with −38.03 dB NMSE using the W-MPM for the (i) 10 W gallium nitride (GaN) high-electron-mobility transistor (HEMT) radio frequency power amplifier (RF-PA) and of −44.34 dB NMSE based on the MPM and −44.90 dB NMSE using the W-MPM for (ii) a ZHL-42W+ at 2000 MHz. The modeling stage and algorithm are suitably implemented in an FPGA testbed. Furthermore, the methodology for measuring the RF-PA under test is discussed. The whole algorithm is able to adapt both stages due to the flexibility of the W-MPM model. The results prove that the W-MPM requires less coefficients compared with a static model. The error vector magnitude (EVM) is estimated for both the static and adaptive schemes, obtaining a considerable reduction in the transmitter chain. The development of an adaptive stage such as the W-MPM is ideal for digital predistortion (DPD) systems where the devices under test vary their electrical characteristics due to use or aging degradation. Full article
(This article belongs to the Special Issue RF Front-End Circuit and Device for 5G/4G LTE)
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10 pages, 3356 KiB  
Article
Optimum Layout of Low Power LC-Based Digitally Controlled Oscillator for Bluetooth Low Energy in a 4G/5G LTE System
by Min-Su Kim and Sang-Sun Yoo
Appl. Sci. 2021, 11(3), 1059; https://doi.org/10.3390/app11031059 - 25 Jan 2021
Cited by 1 | Viewed by 2061
Abstract
This paper presents an optimum layout method of a low-power, digitally controlled oscillator (DCO) for a Bluetooth low-energy (BLE) transceiver in a 4G/5G LTE system. For the optimal LC-based DCO layout, three different layouts, including different gm cell locations and an Al [...] Read more.
This paper presents an optimum layout method of a low-power, digitally controlled oscillator (DCO) for a Bluetooth low-energy (BLE) transceiver in a 4G/5G LTE system. For the optimal LC-based DCO layout, three different layouts, including different gm cell locations and an Al metal layer, were implemented, and performance was compared and verified for BLE application. The implemented neck DCO (NDCO), where the gm cell is located in the neck of the main inductor, showed superior performance compared to other layouts in terms of low phase noise and low power consumption. The designed NDCO had a low phase noise of −116.1 dBc/Hz at 1 MHz with a 0.5 mW power consumption. The supply voltage and oscillation frequency range were 0.8 V and 4.7–5.7 GHz, respectively, and the NDCO designed with the optimal layout had a good figure-of-merit of −192.6 dBc/Hz. Full article
(This article belongs to the Special Issue RF Front-End Circuit and Device for 5G/4G LTE)
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8 pages, 4857 KiB  
Article
The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology
by Min-Su Kim, Youngoo Yang, Hyungmo Koo and Hansik Oh
Appl. Sci. 2021, 11(1), 429; https://doi.org/10.3390/app11010429 - 04 Jan 2021
Cited by 1 | Viewed by 1923
Abstract
To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS [...] Read more.
To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz. Full article
(This article belongs to the Special Issue RF Front-End Circuit and Device for 5G/4G LTE)
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