Deep Learning Study on Memory IC Package Warpage Using Deep Neural Network and Finite Element Simulation
Abstract
1. Introduction
2. Methodology
2.1. Quality Factors and DOE Matrix for DL Model
2.2. Finite Element Analysis
2.3. DNN Regression Model
3. Results and Discussion
3.1. FEA Simulation Warpage Result
3.2. DNN Trained Model and Validation
3.3. Factor Sensitivity Study Using Regression Model
3.4. DNN Regression Model Application on New Package Design
4. Conclusions
- Ten critical factors relating to geometry and materials have been defined based on experience and sensitivity study to develop DNN model for predicting package warpage on UFS memory package.
- To reduce package warpage, wider die size, lower die stacking ratios, lower EMC CTE, thinner die stacking, thicker substrate, and thicker mold cap are recommended based on DNN model prediction on UFS package warpage.
- The implementation of a deep learning model in NPI support significantly reduces cycle time. Compared to traditional methods such as FEA simulation, the AI-based approach achieves approximately 95% reduction in development time and effectively supports for package optimization on UFS package.
- In general, package design and development should leverage AI to optimize structure/performance, reduce costs, and shorten development time. This physics-based DNN model can also be applied to other processes and reliability-related risk assessment areas such as strip warpage, solder joint reliability, thermal analysis, and package strength for advanced packages, which are our on-going and future work.
Author Contributions
Funding
Conflicts of Interest
References
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No of Factors | Factors Name | Level |
---|---|---|
X1 | Substrate Thickness (µm) | 106, 127, 160 |
X2 | Substrate Shrinkage (ppm) | 0, 400, 800 |
X3 | Mold Cap Thickness (µm) | 350, 500, 640 |
X4 | EMC Shrinkage (ppm) | 0, 250, 500 |
X5 | LDR (Left Side Die Stack Ratio) | 0, 0.5, 0.8 |
X6 | RDR (Right Side Die Stack Ratio) | 0.5, 0.65, 0.8 |
X7 | Die Width (µm) | 4000, 5500 |
X8 | Substrate Material CTE (ppm/k) | 6, 12 |
X9 | Solder Mask CTE (ppm/k) | 20, 50 |
X10 | EMC Material CTE (ppm/k) | 9, 13 |
Neural Network Parameter | Attribute Range Setting | Final Attribute/Value |
---|---|---|
Neuron Number | 1~10 | 6 |
Hidden Layer | 2~6 | 4 |
Activation Function | Sigmoid, Relu, Tanh, SoftMax | Relu |
Loss Function | MSE | MSE |
Learning Rate | 0~1 | 0.0001 |
Batch Size | 2~10 | 2 |
Epoch (Iteration) | 100~2000 | 500, 1000 |
Preprocess | Min-Max, Robust, Standard | Min-Max, Standard Scaler |
Cross-Validation (K-Fold) | 5, 10, 15 | 15 |
Training/Validation | 234/16 | 234/16 |
Factors | X1 | X2 | X3 | X4 | X5 | X6 | X7 | X8 | X9 | X10 |
---|---|---|---|---|---|---|---|---|---|---|
DOE 1 | 0 | 1 | 0 | 0.5 | 0.625 | 0.5 | 0 | 0 | 0 | 0 |
DOE 2 | 0 | 0.5 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 |
DOE 3 | 0.388 | 0 | 0 | 0.5 | 0 | 1 | 1 | 1 | 0 | 0 |
DOE 4 | 0.388 | 0.5 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 |
DOE 5 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 |
DOE 6 | 0 | 1 | 0.517 | 0.5 | 0 | 0.5 | 1 | 1 | 0 | 0 |
DOE 7 | 1 | 0 | 1 | 0.5 | 0 | 0.5 | 1 | 0 | 0 | 1 |
DOE 8 | 1 | 0 | 0.517 | 1 | 0 | 0.5 | 1 | 1 | 0 | 1 |
DOE 9 | 1 | 1 | 0.517 | 0 | 0 | 1 | 1 | 1 | 0 | 1 |
DOE 10 | 1 | 0.5 | 0 | 0.5 | 0 | 0 | 1 | 0 | 0 | 1 |
Temperature °C | Training Score | Validation Score |
---|---|---|
30 | 0.95 | 0.95 |
100 | 0.97 | 0.97 |
150 | 0.99 | 0.96 |
180 | 0.99 | 0.96 |
200 | 0.99 | 0.96 |
220 | 0.99 | 0.97 |
240 | 0.98 | 0.97 |
260 | 0.97 | 0.95 |
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Panigrahy, S.K.; Che, F.X.; Ong, Y.C.; Ng, H.W.; Kumar, G. Deep Learning Study on Memory IC Package Warpage Using Deep Neural Network and Finite Element Simulation. Chips 2025, 4, 35. https://doi.org/10.3390/chips4030035
Panigrahy SK, Che FX, Ong YC, Ng HW, Kumar G. Deep Learning Study on Memory IC Package Warpage Using Deep Neural Network and Finite Element Simulation. Chips. 2025; 4(3):35. https://doi.org/10.3390/chips4030035
Chicago/Turabian StylePanigrahy, Sunil Kumar, Fa Xing Che, Yeow Chon Ong, Hong Wan Ng, and Gokul Kumar. 2025. "Deep Learning Study on Memory IC Package Warpage Using Deep Neural Network and Finite Element Simulation" Chips 4, no. 3: 35. https://doi.org/10.3390/chips4030035
APA StylePanigrahy, S. K., Che, F. X., Ong, Y. C., Ng, H. W., & Kumar, G. (2025). Deep Learning Study on Memory IC Package Warpage Using Deep Neural Network and Finite Element Simulation. Chips, 4(3), 35. https://doi.org/10.3390/chips4030035