Chips

29 pages, 9331 KiB

Open AccessReview

Radiation-Induced Effects on Semiconductor Devices: A Brief Review on Single-Event Effects, Their Dynamics, and Reliability Impacts

by Vitor A. P. Aguiar, Saulo G. Alberton and Matheus S. Pereira

Chips 2025, 4(1), 12; https://doi.org/10.3390/chips4010012 - 18 Mar 2025

Viewed by 422

Abstract

Radiation effects on electronic devices represent a major concern in applications for harsh environments, such as aerospace and nuclear facilities. This article presents a review of fundamental aspects of radiation effects on semiconductors, with a primary focus on Single-Event Effects. It discusses charge [...] Read more.

Radiation effects on electronic devices represent a major concern in applications for harsh environments, such as aerospace and nuclear facilities. This article presents a review of fundamental aspects of radiation effects on semiconductors, with a primary focus on Single-Event Effects. It discusses charge collection models, destructive effects, applications in detectors, and impacts on digital devices, drawing from recent research findings. Full article

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11 pages, 18756 KiB

Open AccessArticle

Three-Dimensional Simulation of Bipolar Resistive Switching Memory with Embedded Conductive Nanocrystals in an Oxide Matrix

by Juan Ramirez-Rios, José Juan Avilés-Bravo, Mario Moreno-Moreno, Luis Hernández-Martínez and Alfredo Morales-Sánchez

Chips 2025, 4(1), 11; https://doi.org/10.3390/chips4010011 - 11 Mar 2025

Viewed by 358

Abstract

In this work, the simulation of deoxidation–oxidation of oxygen vacancies (V_Os) in an oxide matrix with embedded conductive nanocrystals (c-NCs) is carried out for the development of bipolar resistive switching memories (BRSMs). We have employed the three-dimensional kinetic Monte Carlo (3D-kMC) [...] Read more.

In this work, the simulation of deoxidation–oxidation of oxygen vacancies (V_Os) in an oxide matrix with embedded conductive nanocrystals (c-NCs) is carried out for the development of bipolar resistive switching memories (BRSMs). We have employed the three-dimensional kinetic Monte Carlo (3D-kMC) method to simulate the RS behavior of BRSMs. The c-NC is modeled as fixed oxygen vacancy (f-V_O) clusters, defined as sites with zero recombination probability. The three-dimensional oxygen vacancy configuration (3D-V_OC) obtained for each voltage step of the simulation is used to calculate the resistive state and the electrical current. It was found that the c-NC reduces the voltage required to switch the memory state from a high to a low resistive state due to the increase in a nonhomogeneous electrical field between electrodes. Full article

(This article belongs to the Special Issue New Advances in Memristors: Design and Applications)

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21 pages, 7095 KiB

Open AccessReview

Review of Industrialization Development of Nanoimprint Lithography Technology

by Yuanxun Cao, Dayong Ma, Haiming Li, Guangxu Cui, Jie Zhang and Zhiwei Yang

Chips 2025, 4(1), 10; https://doi.org/10.3390/chips4010010 - 10 Mar 2025

Viewed by 908

Abstract

This article summarizes the current development status of nanoimprint lithography (NIL) technology and its application prospects in multiple industries. Nanoimprint lithography technology has significant advantages, such as low cost, high resolution, and no development, and is not affected by standing wave effects, making [...] Read more.

This article summarizes the current development status of nanoimprint lithography (NIL) technology and its application prospects in multiple industries. Nanoimprint lithography technology has significant advantages, such as low cost, high resolution, and no development, and is not affected by standing wave effects, making it a potential technology in industries such as semiconductors, photovoltaics, and LEDs. However, nanoimprint lithography technology still faces challenges in terms of film characteristics and material selection during application. This article analyzes existing research and discusses its application advantages in the fields of patterned sapphire substrates (PSSs), Light-Emitting Diode (LED) chips, photovoltaic cells, etc., and proposes the role of technological progress in promoting industrialization. This article summarizes the opportunities and challenges of nanoimprint lithography technology in the future industrialization process and anticipates its development prospects for large-scale production. Full article

(This article belongs to the Special Issue New Research in Microelectronics and Electronics)

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9 pages, 3584 KiB

Open AccessCommunication

Thermal Analysis and Evaluation of Memristor-Based Compute-in-Memory Chips

by Awang Ma, Bin Gao, Peng Yao, Jianshi Tang, He Qian and Huaqiang Wu

Chips 2025, 4(1), 9; https://doi.org/10.3390/chips4010009 - 5 Mar 2025

Viewed by 502

Abstract

The rapid advancement of artificial intelligence (AI) technologies has significantly increased the demand for high-performance computational hardware. Memristor-based compute-in-memory (CIM) technology, also known as resistive random-access memory (RRAM)-based CIM technology, shows great potential for addressing the data transfer bottleneck and supporting high-performance computing [...] Read more.

The rapid advancement of artificial intelligence (AI) technologies has significantly increased the demand for high-performance computational hardware. Memristor-based compute-in-memory (CIM) technology, also known as resistive random-access memory (RRAM)-based CIM technology, shows great potential for addressing the data transfer bottleneck and supporting high-performance computing (HPC). In this paper, a multi-scale thermal model is developed to evaluate the temperature distribution in RRAM-based CIM chips and the influence of various factors on thermal behavior. The results indicate that hotspot temperatures can be mitigated by reducing the epoxy molding compound (EMC) thickness, increasing the substrate thickness, and lowering boundary thermal resistance. Moreover, optimizing the layout of analog computing circuits and digital circuits can reduce the maximum temperature by up to 4.04 °C. Furthermore, the impact of temperature on the conductance of RRAM devices and the inference accuracy of RRAM-based CIM chips is analyzed. Simulation results reveal that thermal-induced accuracy loss in CIM chips is significant, but the computation correction method effectively reduces the accuracy loss from 66.4% to 1.4% at 85 °C. Full article

(This article belongs to the Special Issue New Advances in Memristors: Design and Applications)

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26 pages, 4969 KiB

Open AccessReview

A Review of Recent Advances in High-Dynamic-Range CMOS Image Sensors

by Jingyang Chen, Nanbo Chen, Zhe Wang, Runjiang Dou, Jian Liu, Nanjian Wu, Liyuan Liu, Peng Feng and Gang Wang

Chips 2025, 4(1), 8; https://doi.org/10.3390/chips4010008 - 3 Mar 2025

Viewed by 1272

Abstract

High-dynamic-range (HDR) technology enhances the capture of luminance beyond the limits of traditional images, facilitating the capture of more nuanced and lifelike visual effects. This advancement has profound implications across various sectors, such as medical imaging, augmented reality (AR), virtual reality (VR), and [...] Read more.

High-dynamic-range (HDR) technology enhances the capture of luminance beyond the limits of traditional images, facilitating the capture of more nuanced and lifelike visual effects. This advancement has profound implications across various sectors, such as medical imaging, augmented reality (AR), virtual reality (VR), and autonomous driving systems. The evolution of complementary metal-oxide semiconductor (CMOS) image sensor (CIS) manufacturing techniques, particularly through backside illumination (BSI) and advancements in three-dimensional (3D) stacking architectures, is driving progress in HDR’s capabilities. This paper provides a review of the technologies developed over the past six years that augment the dynamic range (DR) of CIS. It systematically introduces and summarizes the implementation methodologies and distinguishing features of each technology. Full article

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13 pages, 12529 KiB

Open AccessArticle

Automated R-DAC Layout Design with Parameterized Topology Written in SWA: SoftWare Analog

by Mitsutoshi Sugawara, Hidekana Susa, Kenji Mori and Akira Matsuzawa

Chips 2025, 4(1), 7; https://doi.org/10.3390/chips4010007 - 19 Feb 2025

Viewed by 453

Abstract

Leading-edge analog/mixed-signal LSI designs are still hand-crafted using graphic editors. These graphic editors do not include functionality for parameterized topologies in variable designs. Instead of graphic editors, we have developed the SWA (SoftWare Analog) language, which can describe and display placements and routing [...] Read more.

Leading-edge analog/mixed-signal LSI designs are still hand-crafted using graphic editors. These graphic editors do not include functionality for parameterized topologies in variable designs. Instead of graphic editors, we have developed the SWA (SoftWare Analog) language, which can describe and display placements and routing for analog/mixed-signal LSI layouts with less or similar labor time. By using SWA, we have developed an R-DAC (resistive digital–analog converter) layout with a parameterized topology and various parameters, such as ~1 Gsps, 4~12-bit (upper segment type + lower R-2R type) R-DAC, and 1~3.3 V logic with 1~3.3 V_pp analog output. Full article

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16 pages, 413 KiB

Open AccessArticle

Open-Source FPGA Implementation of an I3C Controller

by Jorge André Gastmaier Marques, Sergiu Arpadi and Maximiliam Luppe

Chips 2025, 4(1), 6; https://doi.org/10.3390/chips4010006 - 27 Jan 2025

Viewed by 926

Abstract

Multiple serial interfaces have emerged to meet system requirements across devices, ranging from slower-speed buses, such as I²C, to high throughput serial interfaces, like JESD204. To address the need for a medium-speed protocol and to resolve I²C shortcomings, the [...] Read more.

Multiple serial interfaces have emerged to meet system requirements across devices, ranging from slower-speed buses, such as I²C, to high throughput serial interfaces, like JESD204. To address the need for a medium-speed protocol and to resolve I²C shortcomings, the MIPI Alliance developed the I3C specification, which is a royalty-free next-generation version of I²C with new features and backward compatibility. Since the MIPI Alliance’s I3C work only includes the specifications, it depends on third-party vendors to develop their own cores according to the specifications. Only a few processing systems contain I3C Controllers, each with its own partial implementation of the specification, and there are no open-source controller cores. Thus, this work presents an open-source I3C Controller HDL framework that operates at the maximum specified SDR frequency and is compatible with the Linux kernel. Both the core and Linux kernel drivers are available under permissive open-source licenses. The solution is mostly aimed at development boards with Xilinx Zynq and Intel Cyclone SoC; nevertheless, the structure of the project allows it to be ported to other vendors and carriers. Full article

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31 pages, 7798 KiB

Open AccessReview

High-Accuracy Bandgap Reference of <20 ppm/°C: A Review

by Haoyu Zhuang, Xudong Chen, Enzhe Zhang and Qiang Li

Chips 2025, 4(1), 5; https://doi.org/10.3390/chips4010005 - 21 Jan 2025

Viewed by 1156

Abstract

This review discusses the principle of typical bandgap reference circuits and analyzes their sources of errors. In order to provide readers with a clear perspective, we categorize the error sources into four types: (a) amplifier offset; (b) high-order nonlinearity of

V_{B E}

[...] Read more.

This review discusses the principle of typical bandgap reference circuits and analyzes their sources of errors. In order to provide readers with a clear perspective, we categorize the error sources into four types: (a) amplifier offset; (b) high-order nonlinearity of

V_{B E}

; (c) current mirror mismatch; and (d) other error sources. For these error sources, the most commonly used methods to reduce or minimize them to achieve high accuracy are summarized. Furthermore, this review explores sub-1V bandgap reference design techniques, addressing the increasing demand for low-power and low-voltage applications. Finally, we provide some suggestions for a future high-accuracy reference design. Full article

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11 pages, 736 KiB

Open AccessCommunication

Low-Power, High-Speed Adder Circuit Utilizing Current-Starved Inverters in 22 nm FDSOI

by Jeff Dix

Chips 2025, 4(1), 4; https://doi.org/10.3390/chips4010004 - 3 Jan 2025

Viewed by 762

Abstract

A low-power, high-speed adder circuit topology based on current-starved inverters is presented to provide a basic arithmetic function for low-power, high-frequency signal processing systems. The adder is designed in 22 nm FDSOI (Fully-Depleted Silicon-on-Insulator) technology and is suitable for operation up to 5 [...] Read more.

A low-power, high-speed adder circuit topology based on current-starved inverters is presented to provide a basic arithmetic function for low-power, high-frequency signal processing systems. The adder is designed in 22 nm FDSOI (Fully-Depleted Silicon-on-Insulator) technology and is suitable for operation up to 5 GHz (Giga-Hertz). The proposed adder utilizes current-starved inverters to implement low-power operation while still maintaining signal integrity for high-frequency sine signals. The circuit uses a differential input and output structure to mitigate potential noise coupling onto any high-frequency signal pathways. The proposed solution differs from standard adder architectures by utilizing a fully analog signal processing design, accepting analog inputs while outputting an analog signal, and offering suitable functionality at Giga-Hertz level signals as compared to other relevant works. The simulated experimental results show the power consumption to be approximately 150 nW at 0.8 V supply with an input-referred noise of 6.091 nV/Hz at 5 GHz. Full article

(This article belongs to the Special Issue IC Design Techniques for Power/Energy-Constrained Applications)

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27 pages, 4677 KiB

Open AccessReview

Weak Physycally Unclonable Functions in CMOS Technology: A Review

by Massimo Vatalaro, Raffaele De Rose, Marco Lanuzza and Felice Crupi

Chips 2025, 4(1), 3; https://doi.org/10.3390/chips4010003 - 30 Dec 2024

Viewed by 775

Abstract

Physically unclonable functions (PUFs) represent emerging cryptographic primitives that exploit the uncertainty of the CMOS manufacturing process as an entropy source for generating unique, random and stable keys. These devices can be potentially used in a wide variety of applications ranging from secret [...] Read more.

Physically unclonable functions (PUFs) represent emerging cryptographic primitives that exploit the uncertainty of the CMOS manufacturing process as an entropy source for generating unique, random and stable keys. These devices can be potentially used in a wide variety of applications ranging from secret key generation, anti-counterfeiting, and low-cost authentications to advanced protocols such as oblivious transfer and key exchange. Unfortunately, guaranteeing adequate PUF stability is still challenging, thus often requiring post-silicon stability enhancement techniques. The latter help to contrast the raw sensitivity to on-chip noise and variations in the environmental conditions (i.e., voltage and temperature variations), but their area and energy costs are not always feasible for IoT devices that operate with constrained budgets. This pushes the demand for ever more stable, area- and energy-efficient solutions at design time. This review aims to provide an overview of several weak PUF solutions implemented in CMOS technology, discussing their performance and suitability for being employed in security applications. Full article

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21 pages, 1104 KiB

Open AccessArticle

Advancing Applications of Robot Audition Systems: Efficient HARK Deployment with GPU and FPGA Implementations

by Zirui Lin, Hideharu Amano, Masayuki Takigahira, Naoya Terakado, Katsutoshi Itoyama, Haris Gulzar and Kazuhiro Nakadai

Chips 2025, 4(1), 2; https://doi.org/10.3390/chips4010002 - 27 Dec 2024

Viewed by 724

Abstract

This paper proposes efficient implementations of robot audition systems, specifically focusing on deployments using HARK, an open-source software (OSS) platform designed for robot audition. Although robot audition systems are versatile and suitable for various scenarios, efficiently deploying them can be challenging due to [...] Read more.

This paper proposes efficient implementations of robot audition systems, specifically focusing on deployments using HARK, an open-source software (OSS) platform designed for robot audition. Although robot audition systems are versatile and suitable for various scenarios, efficiently deploying them can be challenging due to their high computational demands and extensive processing times. For scenarios involving intensive high-dimensional data processing with large-scale microphone arrays, our generalizable GPU-based implementation significantly reduced processing time, enabling real-time Sound Source Localization (SSL) and Sound Source Separation (SSS) using a 60-channel microphone array across two distinct GPU platforms. Specifically, our implementation achieved speedups of 23.3× for SSL and 3.0× for SSS on a high-performance server equipped with an NVIDIA A100 80 GB GPU. Additionally, on the Jetson AGX Orin 32 GB, which represents embedded environments, it achieved speedups of 14.8× for SSL and 1.6× for SSS. For edge computing scenarios, we developed an adaptable FPGA-based implementation of HARK using High-Level Synthesis (HLS) on M-KUBOS, a Multi-Access Edge Computing (MEC) FPGA Multiprocessor System on a Chip (MPSoC) device. Utilizing an eight-channel microphone array, this implementation achieved a 1.2× speedup for SSL and a 1.1× speedup for SSS, along with a 1.1× improvement in overall energy efficiency. Full article

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11 pages, 4263 KiB

Open AccessCommunication

A Well-Defined Procedure for Designing Robust Asynchronous Controllers for DC-DC Converters

by Rosario Mita and Angelo Mazzone

Chips 2025, 4(1), 1; https://doi.org/10.3390/chips4010001 - 24 Dec 2024

Viewed by 620

Abstract

This paper presents a novel procedure for designing robust high-speed asynchronous DC-DC converter controllers. The method relies on the use of Workcraft©, a plugin-based development system designed to synthesize and validate the asynchronous control logic, ensuring hazard-free implementation even in the case of [...] Read more.

This paper presents a novel procedure for designing robust high-speed asynchronous DC-DC converter controllers. The method relies on the use of Workcraft©, a plugin-based development system designed to synthesize and validate the asynchronous control logic, ensuring hazard-free implementation even in the case of non-persistent input signals. The simulation results (using a proprietary 90 nm technology) showed a typical time response from input to output of less than 1.4 ns, which fits the fast response requirements for DC-DC converters. Full article

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Chips, Volume 4, Issue 1 (March 2025) – 12 articles

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