Radiation-Induced Effects on Semiconductor Devices: A Brief Review on Single-Event Effects, Their Dynamics, and Reliability Impacts
Abstract
:1. Introduction
2. Cumulative Effects: Total Ionizing Dose (TID) and Displacement Damage (DD)
3. Single-Event Effects
3.1. General Aspects and Test Methods
- Large beam spot to cover the entire area of interest or a microbeam with scanning capability. In the case of a large spot, it should be at least 90% uniform in the considered area.
- Flux: The particle flux should fall within the range of to ions.cm−2.s−1. This requirement ensures that the device is not hit by more than one ion during a data acquisition cycle.
- Range: The minimum beam penetration should be 30 µm in silicon. However, for several studies, it can be assumed that the range should simply be much greater than the thickness of the active layer [38].
- Energy and LET: The energy and linear energy transfer (LET) (linear energy transfer is the amount of energy deposited in the device per unit path length) of the beam in the device must be known within a maximum variation of 10%. The LET depends on the particle energy and species and is generally calculated through computational simulations, using SRIM software [42], for example. To ensure that the LET does not vary by more than 10%, it must be guaranteed that the Bragg curve in the region where the charge is collected (the active layer) forms a plateau, a condition that is usually met when the range is much greater than the thickness of the active layer.
- Beams: Tests should be performed with several beams, ideally some with the same LET, as the effects can vary with the ion species. If possible, data should be obtained up to twice the saturation LET.
- Single-Event Transient—SET: A transient effect (voltage/current pulses) that propagates through the circuit and can trigger subsequent effects. Its correction is complex, as the transient effect generated in the device may only be detected at another point in the circuit. Newer technologies are more susceptible to SET because the critical charge is smaller.
- Single-Event Upset—SEU: The generation of charge produces current/voltage spikes (SET) that affect the logic (on/off) of the device. In general, these effects can be summarized as a bit flipping from 0 to 1 or vice versa. These effects primarily affect digital devices. In cases where multiple bits are affected, this effect is called Multiple-Bit Upset (MBU) [48];
- Single-Event Functional Interrupt—SEFI: A subclass of SEU related to high-density digital devices such as Field-Programmable Gate Arrays (FPGAs), as radiation can affect the logical system of the component.
- Single-Event Latch-Up—SEL: A parasitic thyristor is activated in CMOS circuits by a high-LET particle, generating a high current flow and overheating, potentially destroying the device. Since the parasitic thyristor is activated in deep layers (below the source and drain channels), it is important that the particle deposits energy in this region.
- Single-Event Burnout—SEB: Power devices in the “off” state can be activated by a particle capable of generating enough charge to burn out the device.
- Single-Event Gate Rupture—SEGR: Primarily affects MOS power devices. The accumulation of charges at the Si/SiO2 interface increases the electric field in the gate oxide, permanently breaking its dielectric strength.
3.2. Cross-Section and Failure Rate
3.3. Single-Event-Transients: Charge Injection and Collection
- .
- High-energy ions (>8.0 MeV/u) in large tech node devices: LET can be considered constant and equal to the value at the surface;
- High-energy ions (>8.0 MeV/u) in small tech node devices: radial LET variation should be considered;
- Low-energy ions (<0.3 MeV/u) in large tech node devices: longitudinal LET variation should be considered;
- Low-energy ions (<0.3 MeV/u) in small tech node devices: both longitudinal and radial LET variations should be considered.
3.4. Simulations and Computational Methods
3.5. Particle Detectors and Systems for Nuclear and Particle Physics
3.6. Destructive Effects: Single-Event Gate Rupture and Single-Event Burnout
3.6.1. Single-Event Gate Rupture (SEGR)
3.6.2. Single-Event Burnout
3.7. Neutron Secondary Effects
4. Impacts on Reliability in Harsh Environments
4.1. Power Systems
- De-rating: Typically consists in reducing the operating bias by 25% from the destructive SEE onset, preventing or eliminating the occurrence of destructive SEEs.
- Hardening by design: Structural and process modifications can improve radiation hardness, often at the cost of electrical performance [123]. For instance, SEB robustness in BJTs and MOSFETs can be improved by reducing the parasitic base–emitter resistance and lowering emitter current injection efficiency [158], as well as incorporating optimized buffer layers [159]. SEGR robustness can be improved by reducing neck width and implementing alternative stripe geometries [160].
4.2. Digital Circuits
- Layout- and electrical-level techniques:
- –
- Built-in current sensors (BICSs) are used to detect soft errors by monitoring currents in the bulk region of transistors. These sensors can differentiate ionization events, which cause sharp current spikes, from regular circuit activity. Bulk-BICSs detect SETs with a slight delay, which depends on the number of transistors connected, the intensity of the SET, and the calibration for SET signals. Once an SET is detected, the control logic can perform a fault-tolerant technique. The detection of SETs can be performed even with the use of neural networks [166].
- –
- Transistor resizing is used to increase the capacitance at sensitive nodes, thereby raising the critical charge level required to cause an SET. By increasing the capacitance at these nodes, the circuit becomes less susceptible to radiation-induced errors. However, resizing must be performed carefully to avoid performance and power drawbacks.
- Logic-level techniques:
- –
- Hardware redundancy, such as duplication with comparison (DWC), where a module is duplicated and the outputs are compared. However, DWC can only indicate that an error has occurred, not which specific part of the logic failed. Parity checking can be used for improved robustness. A more advanced approach is N-modular redundancy (N-MR), where multiple modules (usually three in the case of Triple Modular Redundancy, TMR) are used and a majority voter selects the correct output [167,168,169].
- –
- Time redundancy techniques, such as using two flip-flops with delayed clock signals to capture the output at two distinct times, enabling SET detection. A more advanced approach, full-time redundancy, uses three clocked latches with a majority voter to select the correct output based on multiple observations over time. However, in nanometer technologies, this technique faces challenges when SET pulses last longer than the clock cycle, limiting its effectiveness. The time delay between clocks must be sufficient to capture SETs, but the method becomes impractical when SET durations are comparable to the clock period [170].
- –
- Memory cells can be hardened against SEUs with additional transistors or resistors that allow for the recovery of the stored value when an upset occurs. These techniques typically involve slowing the regenerative feedback of a memory cell or adding feedback mechanisms to restore corrupted data [171]. New materials and technologies for memories also represent a possibility for increasing reliability in harsh environments [172,173]
- –
- Error-correcting codes (ECCs) use information redundancy to mitigate soft errors (SEUs) in integrated circuits. They are primarily used in memory arrays but can also be applied to microprocessor registers and other small memory structures. ECCs can be implemented on hardware or software. Simple ECC methods, like Hamming code, can detect double-bit errors and correct single-bit errors at the cost of including extra check bits, while more complex codes can address multi-bit errors, implemented at hardware and software levels.
5. Concluding Remarks
Author Contributions
Funding
Conflicts of Interest
References
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Semiconductor | Energy/Pair (eV) | Charge per Deposited Energy (fC/MeV) |
---|---|---|
Si | 3.6 | 45 |
Ge | 2.9 | 55 |
SiC | 7.8 | 21 |
GaAs | 4.8 | 33 |
GaN | 8.9 | 18 |
Diamond | 13.0 | 12 |
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Aguiar, V.A.P.; Alberton, S.G.; Pereira, M.S. Radiation-Induced Effects on Semiconductor Devices: A Brief Review on Single-Event Effects, Their Dynamics, and Reliability Impacts. Chips 2025, 4, 12. https://doi.org/10.3390/chips4010012
Aguiar VAP, Alberton SG, Pereira MS. Radiation-Induced Effects on Semiconductor Devices: A Brief Review on Single-Event Effects, Their Dynamics, and Reliability Impacts. Chips. 2025; 4(1):12. https://doi.org/10.3390/chips4010012
Chicago/Turabian StyleAguiar, Vitor A. P., Saulo G. Alberton, and Matheus S. Pereira. 2025. "Radiation-Induced Effects on Semiconductor Devices: A Brief Review on Single-Event Effects, Their Dynamics, and Reliability Impacts" Chips 4, no. 1: 12. https://doi.org/10.3390/chips4010012
APA StyleAguiar, V. A. P., Alberton, S. G., & Pereira, M. S. (2025). Radiation-Induced Effects on Semiconductor Devices: A Brief Review on Single-Event Effects, Their Dynamics, and Reliability Impacts. Chips, 4(1), 12. https://doi.org/10.3390/chips4010012