Design and Validation of a Passive Balancer Based on Switched Shunt Resistor for Medium Power Ratings in Electrification Transportation

Abstract

This article presents the implementation of a passive balancing strategy in an energy storage network based on LiPo cells. The proposed system is intended to operate in a 5.6 kWh battery pack for two-wheeled electric vehicle applications. The battery balancer allows voltage equalization between the LiPo cells before and after the charging process, ensuring controlled charging cycle for each cell. The LiPo cell balancer uses a passive method which transforms the excess of electric energy into heat by means of a resistance described in the Joule Effect. In order to minimize energy losses, three operating modes were proposed: post-charge, pre-charge, and storage node balancing. The post-charge mode reduces the cell voltage to 4.20 V, while the voltage is set to 2.8 V in the pre-charge mode. The design and construction details of a six-cell module prototype are described in this paper, along with experimental research. The balancer system was successfully operated in the series modules of the LiPo battery pack using the proposed modes of operation.

1. Introduction

1.1. The Trend Towards Electrification Transportation

The electric vehicle (EV) market has experienced significant growth, accounting for over 20% of global vehicle sales and exceeding 17 million units sold in 2024, being mainly covered by the Chinese and United States markets [1]. Also, the main Chinese vehicle brands are planning to enter the UK market as newcomers, where prestigious and traditional brands such as Mini, BMW, and Land Rover are already established [2]. In Europe, the energy transition from internal combustion vehicles to zero-emission EVs has been greatly promoted. An example of implementation of this kind of transition is Norway, where practically only EVs are allowed in its capital, and by validating the use of these energies, they now plan to switch to electric airplanes [3]. However, this transition to EV adoption remains challenging for several countries across Europe and other regions worldwide. For example, Germany and automotive industries have expressed interest in relaxing the emission regulations established by the European Union that prohibit all new vehicles sold after 2035 from producing carbon emissions [4]. From another perspective, in Mexico, EVs have also experienced an increase in production of around 72.27% in the first quarter of 2025 compared to the same period in 2024 [5]. Furthermore, the Mexican government has promoted the creation of a new line of electric vehicles, with production due to begin in the summer of 2027 [6,7].

Such decisions arise from the challenges involved in transitioning to cleaner energies and tend to encourage technological advancements, the development of more sophisticated storage systems, achieving climate neutrality, and the preparation of larger and more stable electricity supplies to address the increasing energy demand. Current EV fleets are mainly based on battery packs as their primary energy source. Thus, technological advances in these industries have been focused on developing new energy sources. EV battery packs and supercapacitors mainly use prismatic or cylindrical Li-ion cells to provide energy [8,9]. However, some EV batteries come in pouch-type packaging [10], with multiple series and parallel connections. In particular, battery packs, which are commonly referred to as Battery Energy Storage Systems (BESSs), have been extensively studied due to their complexity and high cost, and one of the primary challenges in battery pack design is achieving proper balancing among the multiple cells within the pack.

Voltage differences between cells may occur, ranging from negligible to very pronounced voltages levels within a series or parallel arrangements. This phenomenon occurs due to the chemical composition and internal resistance of each cell, manufacturing issues, and the accuracy of charging equipment [11]. Cell balancing is often employed to counteract this effect.

1.2. Balancing Methods

To minimize this effect, two types of methods can be used to balance batteries: passive and active. Passive methods tend to use a resistor connected in parallel to each cell to transform excess voltage into heat through the Joule Effect, thereby balancing all cells with respect to the lowest voltage level [12]. The active strategy consists of moving energy from one cell to another one by averaging all those presented in the array [13,14] and utilizing DC-DC converters to carry out the balancing [15,16].

Figure 1 depicts the aforementioned balancing methods: (a) shows the natural unbalance level of cells Cell_1–4; (b) shows the passive balancing methodology turning the excess voltage of Cell₁, Cell₂, and Cell₄ into heat Q, with respect to the lowest voltage level, Cell₃; and (c) displays the active balancing strategy, where the energy is dynamically redistributed among cells Cell_1–4 with respect to the average level.

Figure 1. Balancing methods: (a) Natural tendency of cells to be unbalanced, (b) passive balancing, and (c) active balancing.

The passive balancing technique has some challenges; for example, heat and waste energy are produced when a large voltage difference is presented between the cells. However, it is often preferred for implementation in high-power battery packs, especially those with a large number of cells.

Figure 2 presents several variants of the passive and active strategies used to balance the cell voltage in battery packs. The section on active methods shows that the balancing strategies employ capacitors, inductors, or DC-DC converters. Meanwhile, with passive methods, the most convenient strategy leverages the variable or switchable resistance, which allows the voltage in the cells to be equalized by controlling the resistance [17].

Figure 2. Methodology for cell balancing.

This article presents a battery balancer intended for operation in a six-cell series (6S) module from a 5.6 kWh LiPo battery pack, which comprises 16 modules connected in series, resulting in a total of 96 cells (96S). Voltage balancing is achieved through a passive strategy based on parallel resistor switching, where activation times are adjusted according to each cell SOC, converting excess energy into heat. The major contribution of this work is the achievement of more controlled charge and discharge cycles in each cell of a LiPo battery pack. The implementation of battery cell balancing is a key issue in the electric vehicular industry, as doing so improves the performance of the battery pack while reducing maintenance requirements, and ensuring safe operation for a long time, as concluded in [18]. Such processes keep voltage levels properly balanced, thereby preventing cells with a high SOH level from degrading prematurely, for which passive balancing is considered the most effective, as mentioned in [18]. The remainder of this paper is organized as follows: First, the proposed battery pack is briefly described, along with the advantages of the passive strategy and a maximum estimate of the heat generated when using this method. Second, the design guidelines of the prototype are described, which incorporate balancing modes designed to minimize heat generation and optimize energy usage through the implementation of operation intervals intended for before and after battery pack charging. Experimental results and numerical estimates are compared to validate the operating principle described in the first section, verifying the balance with the 6S modules. Finally, this article concludes with a summary of the most relevant achievements, along with potential pathways for future research.

2. Materials and Methods

2.1. Battery Pack Proposed

Rechargeable power systems, such as battery packs or supercapacitors, are implemented in transportation electrification [19]. In this paper, a passive balancing system is intended to operate a 5.6 kWh battery pack shown in Figure 3, developed for an 83 kW electric motorbike prototype which is being designed under specifications based on international competitions, as reported in [20,21,22].

Figure 3. Photograph of the proposed battery pack. Each six-cell module of the battery pack is numbered for easy identification.

Figure 4 shows a 3D-exploded view of the battery pack used in this work. The battery pack shown in Figure 3 and Figure 4 was assembled with 16 modules, each of them comprising six pouch-type cells, leading to a total of 96 LiPo cells, whose electrical characteristics exhibit favorable performance and high gravimetric energy density [23,24]. Table 1 summarizes the electrical specifications of each cell used in this battery pack.

Figure 4. 3D-exploded view of the battery pack assembly.

Table 1. Technical specifications of LiPo cells.

Characteristics	Specifications
Nominal Voltage	3.7 V
Minimum Voltage Operation	2.75 V
Maximum Voltage Operation	4.25 V
Storage Voltage	3.8 V
Nominal Capacity	16 Ah 0.2 C discharge
Cell Dimensions	General dimensions (H × W × D) 162 mm × 70 mm × 11 mm
Charging Time	Standard Charge (5 A), 4.8 h. Fast Charge (10 A), 2.5 h.

The photograph in Figure 3 also shows the personalized metal structure for containing the 96 LiPo cells of the battery pack. This metal container was designed using a 12-gauge galvanized metal sheet. The out-of-the-box dimensions of the pack are 0.2 × 0.6 × 0.22 m. In fact, the 3D-exploded-view drawing of the constructed battery pack was used to analyze the mechanical challenges encountered during the assembly process. In the same figure are displayed the 3D-printed parts that were utilized in the bottom for maintaining the position of all cells and the copper connectors properly insulated. Moreover, this battery pack will be used in a further integration of an electric motorbike with characteristics similar to those of a mid-range internal-combustion-engine racing bike reported previously in [25,26,27].

Finally, Figure 5 depicts a block diagram of a proposed set of components for electrification transportation. This includes charging components, the active rectifier, and the battery pack, along with other subsystems, such as DC-DC converters, the motor controller, and the electric motorbike prototype, amongst others, which are beyond the scope of this article; they are intended to be integrated into a single system to achieve a certain level of cell balancing during charging.

Figure 5. Block diagram of a proposal for electrification transportation.

2.2. Passive Balancing Circuit Design

The aim of this research is to design a passive balancing circuit for each six-cell module contained in the battery pack presented in the previous section, operating at any voltage level within the series array to which it is connected, whether it is module 1 or module 16. In fact, the method selected for this purpose was the Switched Shunt Resistor (SSR), which is a method that has been little studied due to its disadvantages, but which can be applied to balance BESS systems with a larger number of cells [28,29,30]. However, the heat generated by these resistors must be managed appropriately, by calculating the amount of heat generated in each operating mode of the battery balancer and minimizing the amount of energy being dissipated as heat.

The SSR system used in this research is presented in Figure 6, where six LiPo cells, labeled from Cell₁ to Cell₆, are shown connected with the shunt resistors, ranging from R₁ to R₆, which are operated through six switches, S₁ to S₆, implemented by transistors. In this method, the balancing circuit simply closes switches of cells identified as having excess charge. The SSR system was constructed using TIP41C transistors for switches S₁ to S₆; these transistors were operated in the cutoff and saturation region. Additionally, six freewheeling diodes were implemented by six MUR420 ultrafast diodes.

Figure 6. Electric diagram for the SSR proposed.

Operation Modes

The prototype implements a multi-scenario operational framework. These modes match the operational demands of the 83 kW electric motorcycle and the physical constraints of the LiPo pouch cells:

• Mode 1, post-charge (V_ref = 4.20 V):

This mode may be activated immediately upon completion of the charge cycle to balance any residual voltage at peak pack potential. The programming code strictly limits cell voltages to 4.20 V, keeping them securely below the manufacturer’s absolute critical degradation threshold, around 4.25 V. Serving as an active protection subsystem, it prevents localized overcharging.

• Mode 2, pre-charge (V_ref = 2.75 V):

This mode in intended to operate before the fast-charging process. Due to manufacturing variations, LiPo pouch cells could exhibit different internal resistances, potentially leading to thermal and voltage imbalances during high-current fast charging (e.g., at 10 A). The algorithm initializes by discharging all cells to a nominal low threshold of 2.75 V. This pre-charge conditioning step is used to accomplish a more consistent initial voltage level across the cells before fast charging processes. Although this approach may potentially contribute to improve cell management during the subsequent charging phase, its effects on current distribution, thermal stress, and prevention of premature overvoltage conditions require further experimental validation.

• Safe storage mode (V_ref = 3.8 V):

This configuration targets prolonged periods of vehicle inactivity or battery pack transport. Storing LiPo cells at maximum charge (4.25 V) or severe discharge (2.75 V) triggers accelerated chemical degradation of the polymer electrodes and drives capacity fade. This mode selectively discharges and balances cell potentials to the optimal safe storage threshold of 3.80 V, which is specified by the manufacturer. Furthermore, this scenario provides the empirical baseline for long-term thermal characterization of the external dissipating chassis.

Table 2 lists the operating modes for the passive balancing system proposed, showing the modes, the operating range, the excess voltage difference, and the average current for each operating mode. In fact, the highest excess voltage difference occurs during a full cycle of use; meanwhile, in the post-charge mode, this difference may be neglected, since the difference is around 0.03 V in this mode.

Table 2. Proposed operation modes for the passive balancing system.

Mode	Recommended Operating Range	Excess Voltage per Cell	Average Current
Full Cycle	4.25 V to 2.75 V	1.5 V	0.81 A
1. Post-Charge Mode	4.25 V to 4.20 V	0.05 V	0.98 A
2. Pre-Charge Mode	3.3 V to 2.8 V	0.5 V	0.70 A
Storage Mode	4.25 V to 3.8 V	0.45 V	0.93 A

Note: These modes propose a reduced operating range to match the operating point of each of the 6S cells in a battery bank module. It is important to note that if the cells are already at voltage to be balanced, they will not be activated; and if they were all to be activated, the balancing time would be the same.

2.3. Prototype Construction

The electrical diagram proposed for the prototype of the SSR system is shown in Figure 7. Figure 7 depicts the implementation of the SSR for any 6S module in the battery pack, whose design is divided into two main parts: the control stage and the power circuit. Firstly, a 4N30 optocoupler was utilized for ensuring isolation between the power and control stages. The control signals used in the bases of each transistor were implemented by an Arduino GIGA R1 microcontroller, which was used as a reference level for the sensors and was powered by an external 5 V voltage supply connected to the USB-C port in a PC.

Figure 7. Electrical diagram for the SSR.

In addition, six FZ0430 voltage sensors were used to obtain the voltages of the six cells in the module, labeled as V₁ to V₆, as shown in Figure 6. Each sensor is formed by a resistive voltage divider consisting of two resistors with nominal values of 30 kΩ and 7.5 kΩ. These resistor values yield a nominal voltage division ratio of 5:1, providing an output voltage of 0.85 V when the input voltage reaches 4.25 V.

Table 3 shows the specifications of the FZ0430 voltage sensor used in each cell in the module for obtaining V₁ to V₆, as proposed in Figure 6. To assess the suitability of different ADC resolutions available in the microcontroller, 10-bit and 12-bit configurations were considered based on the post-charge mode, which exhibits the smallest hysteresis window, approximately 50 mV between cell voltage levels, as reported in Table 2. In this operating mode, the sensor output voltages are 0.850 V and 0.560 V, corresponding to a difference of 29 mV. This voltage difference highlights the need for an ADC with sufficiently resolution. Assuming a 3.3 V reference voltage, a 10-bit ADC provides a theoretical voltage step of approximately 3.22 mV at the ADC input, whereas a 12-bit ADC provides a step of approximately 0.806 mV. Therefore, a 12-bit ADC is suitable for this application because this resolution offers finer voltage discrimination without requiring the additional resolution of a 16-bit ADC, which may introduce unnecessary implementation complexity. Moreover, six operational amplifiers were configured as differential amplifiers with a unitary gain, and the output of each operational amplifier was connected to the analog inputs of the microcontroller. Meanwhile, six digital outputs from the microcontroller were used for turning on the transistors. Finally, six AP031 differential voltage probes from Teledyne LeCroy were utilized for measuring the responses during operation of the system.

Table 3. Technical specifications of FZ0430 voltage sensor.

Characteristics	Specifications
Minimum Supply Voltage	3.3 V
Maximum Input Voltage (Vcc)	25 V (5 V × 5 = 25 V) 16.5 V (3.3 V × 5 = 16.5 V)
Minimum Detection Voltage	24.41 mV
Maximum Detection Voltage	25 V
Output Type Signal	Analogue
Voltage Divider Resistors	R1 = 30 kΩ, R2 = 7.5 kΩ

The power circuit is the operator of the transistors. For these estimations, a current is required in the collector when the resistors of the SSR are used. The operating values for the balancing operation modes with an R = 4.3 Ω are listed as follows:

• Average current of Mode 1, post-charge, is 0.98 A.
• Average current of Mode 2, pre-charge, 0.70 A.
• Average current of the storage mode = 0.93 A.

The currents in the transistor are given by the following equation:

$$I_E=I_C+I_B$$

(1)

And the current I_B from the above equation must be solved in the following equation:

$$I_C=\beta I_B$$

(2)

$$I_B={\displaystyle \frac{I_C}{\beta }}$$

(3)

• I_B is the base current required to turn on the transistor.
• I_C is the current flowing through the resistor in Mode 2 ($I_{C_{\mathit{MODO}2}}=0.70\mathrm{A}$ ).
• β is value DC current gain. For the TIP41C transistor under these operating conditions, according to the graphs in the data sheet, the DC current gain is around 50.

Substituting the values into (3) yields I_B:

$$I_B={\displaystyle \frac{0.70\mathrm{A}}{50}}=14\mathrm{mA}$$

Retrieving R_B by analyzing the voltages in the power mesh and solving for the following:

$$V_{C_2}=V_{{\mathit{ce}}_{4N30}}+R_B{i}_b+V_{{\mathit{BE}}_{\mathit{TIP}41C}}$$

(4)

$$R_B={\displaystyle \frac{V_{C_2}-V_{{\mathit{ce}}_{4N30}}-V_{{\mathit{BE}}_{\mathit{TIP}41C}}}{i_b}}$$

(5)

• R_B is the resistance required to supply the current and turn on the transistor.
• $V_{C_2}$ is the minimum voltage of the LiPo cell in the series array.
• $V_{{\mathit{ce}}_{4N30}}$ is the collector–emitter voltage of the 4N30 optocoupler when it is turned on; the voltage under these conditions is 0.3 V, since it behaves as if it were a diode.
• $V_{{\mathit{BE}}_{\mathit{TIP}41C}}$ is the base–emitter voltage of the TIP41C transistor when it is turned on. The voltage in this state is 0.7 V, as this is the turn-on voltage for NPN bipolar junction transistors made of silicon.

Substituting the values into (5) yields R_B, which is used to determine the resistance value required for each balancing board in order to implement the SSR circuit:

$$R_B={\displaystyle \frac{2.75\mathrm{V}-0.3\mathrm{V}-0.7\mathrm{V}}{14\mathrm{mA}}}={\displaystyle \frac{1.75\mathrm{V}}{14\mathrm{mA}}}$$

$$R_B=125\mathrm{\Omega }$$

A commercial R_B = 120 Ω was used in the implementation of the prototype for verifying that it would operate in the saturation region:

$$I_B={\displaystyle \frac{V_{\mathit{cell}}-V_{\mathit{BE}}}{R_B}}$$

(6)

$$I_B={\displaystyle \frac{4.25\mathrm{V}-0.7\mathrm{V}}{120\mathrm{\Omega }}}$$

$$I_B=29.58\mathrm{mA}$$

The saturation current is obtained with (7):

$$I_{C_{\mathit{sat}}}={\displaystyle \frac{V_{\mathit{cell}}}{R_C}}$$

(7)

$$I_{C_{\mathit{sat}}}={\displaystyle \frac{4.25\mathrm{V}}{4.3\Omega }}=0.988\mathrm{A}$$

Using β = 50 by the datasheet in (8) yields

$${\displaystyle \frac{I_{C_{\mathit{sat}}}}{\beta }}={\displaystyle \frac{0.988\mathrm{A}}{50}}$$

(8)

$${\displaystyle \frac{I_{C_{\mathit{sat}}}}{\beta }}=19.7\mathrm{mA}$$

In order to ensure that the transistor is in the saturation region, the following condition must be addressed:

$$I_B>{\displaystyle \frac{I_{C_{\mathit{sat}}}}{\beta }}$$

$$29.58\mathrm{mA}>19.7\mathrm{mA}$$

2.4. Thermal Generation Analysis

Passive voltage equalization converts excess cell electrical energy into thermal energy via Joule heating. The instantaneous heat generation rate (${\dot{Q}}_{\mathit{gen}}$) within each shunt resistor is governed by the following:

$${\dot{Q}}_{\mathit{gen}}\left(t\right)=I{\left(t\right)}^{2}R\left(T\right)$$

(9)

where I(t) is the time-variant balancing current, and R(T) is the shunt resistance as a function of temperature. For steady-state thermal evaluation, the power dissipation per active channel (P_loss) is determined using the average balancing current ($\overline{I}=0.93\mathrm{A}$) and the nominal power resistance ($R=4.3\mathsf{\Omega }$):

$$P_{\mathit{loss}}=I^{2}R={\left(0.93\mathrm{A}\right)}^2(4.3\mathsf{\Omega })\approx 3.72\mathrm{W}$$

(10)

The cumulative thermal energy dissipated by a single shunt resistor over a complete balancing cycle of duration, t_b, is integrated as follows:

$$Q_{\mathit{total}}=I^{2}R{t}_b$$

(11)

To eliminate thermal coupling within the energy storage system, the passive balancing circuitry is designed as a modular architecture that is physically external to the main battery bank enclosure. This spatial decoupling ensures that the thermal effect generated by the shunt resistors and adjacent electronic components does not contribute to the internal thermal load of the cells. Under this design constraint, an individual balancing channel was experimentally evaluated to characterize its heat-dissipation behavior and establish a baseline for the multi-channel system. The effective thermal resistance from the resistor junction to the ambient air (R_θ,ja) under free natural convection conditions is defined by the following:

$$R_{\theta ,\mathit{ja}}={\displaystyle \frac{T_{\mathit{surf}}-T_{\mathit{amb}}}{P_{\mathit{loss}}}}$$

(12)

Operating at a controlled ambient temperature (T_amb = 25 °C), the experimental thermal curve illustrated in Figure 8 captures the transient response and peak surface temperature (T_surf) of a single resistor, which stabilizes at 64.3 °C after approximately 1000 s. This empirical boundary condition establishes the individual thermal resistance from the node to the atmosphere at

$$R_{\theta ,\mathit{ja}}={\displaystyle \frac{64.3°\mathrm{C}-25°\mathrm{C}}{P_{\mathit{loss}}}}\approx 10.56{\displaystyle \frac{°\mathrm{C}}{\mathrm{W}}}$$

(13)

Figure 8. Temperature for the discharge test of one resistor.

Regarding the thermal response of the cells, the localized heat generation produced by a 1 A balancing discharge does not introduce a critical thermal aversion within the lithium-ion polymer (LiPo) matrix. Because the 4.3 Ω resistance restricts the initial peak current to 0.988 A (I = 4.25 V/4.3 Ω) under the real peak cell potential. This variation is explicitly attributed to the initial degradation state of the experimental pouch cells, which limits full charge retention at 100% capacity relative to the nominal specification plate value (4.25 V) due to natural aging. Furthermore, cells with distinct initial voltages were intentionally selected to establish a severe voltage unbalance condition, thereby providing a robust stress test to evaluate the dynamic response of the architecture.

For further experimental validation, an IR thermal capture is reported in Figure 9, where the temperature in each shunt resistor was around 53.3 °C during operation in Mode 3. This mode was selected in order to display the six resistors operating by a period, ensuring temperature convergence. However, as shown in Figure 9, the thermal IR reveals the initial unbalance between the cells, because the resistors operate independently. In fact, in this experiment, the R₄ presented the lowest temperature because it was around the final voltage faster than the other shunt resistors.

Figure 9. IR thermal capture for the discharge test of the system.

This current configuration establishes a conservative C/16 discharge rate relative to the nominal 16 Ah cell capacity. Furthermore, a maximum discharge current of 1 A corresponds to a very low C-rate of 0.0625 C (1⁄16 C). This condition dismisses any significant thermal stress or heat generation inside the battery cells, isolating the heat management strictly to the external balancer cabinet. Finally, the thermal stress in the TIP41C transistor may be computed by power losses. The power losses in TIP41C transistors, P_BJT, may be computed in the saturation region with I_C = 1 A, while the TIP41C transistor exhibits a collector–emitter saturation voltage of V_CE(sat) = 0.2 V (according to its datasheet). Therefore, each transistor generates a maximum heat power of

$$P_{\mathit{BJT}}=V_{\mathit{CE}\left(\mathit{sat}\right)}{I}_C=\left(0.2\mathrm{V}\right)\left(1\mathrm{A}\right)=0.2\mathrm{W}$$

Considering a simultaneous operation of the six channels, the transistors would generate a total of 1.2 W per module. The amount of power losses is substantially reduced for representing a heat source in the circuit when each transistor can handle around 60 W according to the manufacturer.

2.5. Proposed GUI

The control interface intended for using the SSR system is a Graphical User Interface (GUI), with a real time selection among these three scenarios and the proposed modes by the user. This interface was developed in the Square Line Studio program [31,32,33], and then the programming code was transferred to the Arduino GIGA R1 Wi-Fi [34]. Three different options were programmed for the home screen of the GUI. The first one shows cell balancing, and three options were configured: Mode 1, post-charge; Mode 2, pre-charge; and storage mode. The second one presents a section showing voltage measures, i.e., using the balancer as a real-time voltmeter. Finally, the last one is a function for estimating the SOC through programming.

Figure 10 shows pictures of the interfaces programmed for the balancer: (a) shows the start window for selecting the device operating mode; (b) displays the Mode 1 window, which presents the operating interval for post-charging, where an equalization at 4.20 V is operated; (c) shows the Mode 2 pre-charge window, which activates the resistors of the cells that are above 3 V and up to 2.75 V; (d) shows the voltmeter window for checking the voltage of each cell in real time; and, finally, (e) shows the SOC estimation window, which shows the charge percentage using a bar and an image—this was programmed into the microcontroller according to certain voltage levels described above.

Figure 10. Windows of the modular passive balancer interface.

To ensure precise state estimation within the firmware and avoid the severe inaccuracies induced by conventional linear interpolation approximations, an approximate SOC indicator was developed using an electro-chemical look-up profile, specific to the LiPo cells used in this research, based on cell characterization trials. Figure 11 illustrates the dynamic terminal voltage (V_b) as a non-linear function of the SOC, benchmarked under a 1 C discharge rate and a 0.3125 C charge rate. The integrated dataset tabulates these empirical operating boundaries, providing the deterministic voltage-to-SOC lookup references implemented in the microcontroller code to synchronize the multi-scenario balancing thresholds with the real electrochemical state of the LiPo pouch cells. Also, Table 4 shows the values for programming the approximate SOC indicator using the voltage in 1C discharge and the discharge curve shown below.

Figure 11. Voltage vs State of Charge (SOC).

Table 4. State of Charge (SOC).

SOC (%)	Voltage Discharge at 1C (V)	Voltage Charge at 0.3125 C (V)
100	4.20	4.25
80	3.95	4.07
60	3.81	3.94
40	3.72	3.84
20	3.69	3.82
0	3.23	3.58

Note: The discharge column at 1C will be used, since the prototype achieves balance through a discharge curve.

2.6. Description of the Final Prototype

Figure 12 presents the final SSR prototype built in the laboratory and used for experimental validation, including the 5.6 kWh battery pack.

Figure 12. Photograph of the prototype.

3. Experimental Results

3.1. Mode 1, Post-Charge

For the performance evaluation of the passive balancing system in Mode 1, post-charge, experimental testing was conducted on module number 6 of the 16-module battery pack. The initial open-circuit terminal voltages revealed a high voltage unbalance across the series-connected cells: V₁ ≈ 4.21 V, V₂ ≈ 4.21 V, V₃ ≈ 4.23 V, V₄ ≈ 4.23 V, V₅ ≈ 4.26 V, and V₆ ≈ 4.15 V. Figure 13 shows the initial voltages waveforms of a module in the series-connected 5.6 kWh battery pack.

Figure 13. Waveforms of the voltages of the 6S under initial conditions of the balancing test.

The potential of Cell 5 was around 4.26 V, exceeding the maximum allowable safe operational limit of 4.25 V specified by the manufacturer and Table 2, and thus placing the cell in a critical overcharge zone with a severe risk of accelerated degradation. Nevertheless, this real desynchronization state was adopted as a stress test to validate the protection capabilities and response time of the proposed SSR system. Instead, Cell 6 remained undercharged at 4.15 V; its corresponding switch, S₆, was maintained in the off state throughout the test, demonstrating the selective control precision of the system.

Figure 14a shows the experimental waveforms of the balancing process in Mode 1 of the prototype. This result shows the corresponding balancing of the six cells: four out of six cells were maintained between 4.19 V and 4.20 V, while the other two fell below this voltage window; as mentioned above, V₆ had a voltage of 4.15 V, so the prototype was not activated for this cell. For cell 1, the voltage, V₁, was activated in one part of the process and then turned off. The voltage of this cell continued to drop on its own, and for this reason, an unusual discharge curve is presented for Cell 1. Figure 14b presents the split curves. The total balancing time was 3600 s.

Figure 14. (a) Experimental waveforms for the balancing process of Mode 1, post-charge; and (b) the balancing process, as shown in 6 different plots.

3.2. Mode 2, Pre-Charge

Figure 15 displays the initial conditions used for the Mode 2, pre-charge. In fact, the open-circuit terminal voltages revealed a low unbalance due to all the cells exhibited around 3.2 V between their terminals. Figure 16 presents the experimental results obtained under the operation of Mode 2, pre-charge. As shown in Figure 16a, Cells 1 to 6 were balanced above 3 V, ensuring the cell levels in the voltage window reference listed in Table 2. For this mode, the voltages of the cells may be balanced to 2.75 V. However, to avoid damages in the cells, the test was configured to reach around 2.8 V, keeping all the cells safe. In this operation mode, the time used for this balancing process was around 1800 s. Figure 16b shows the same results from the scope in split plots for better understanding.

Figure 15. Waveforms of the voltages of the 6S under initial conditions of the balancing test.

Figure 16. (a) Experimental waveforms for Mode 2, pre-charge; and (b) experimental results in several plots for visualization.

3.3. Storage Mode

The voltage levels used as initial conditions for the storage mode are shown in Figure 17. As shown in Figure 17, most of the cells presented 3.95 V before the operation of the storage mode. When this mode was operated, all the cells exhibited voltages of about 3.8 V after the balancing period, and the time recorded in this operation mode was approximately 9400 s, equal to 2.6 h, as shown in Figure 18a. Figure 18b shows the same results in split plots for better visualization in the scope.

Figure 17. Waveforms of the voltages of the 6S under initial conditions of the balancing test in storage mode.

Figure 18. (a) Experimental waveforms for storage mode, and (b) experimental results in several plots for visualization.

3.4. Results

Table 5 shows the results of each cell in the three operating modes, displaying the initial and the final voltage, together with ΔV_max and the balancing time corresponding to the experimental waveforms obtained in each operating mode. Moreover, the voltage spreads for each mode are presented in the same table. The voltage spread in Mode 1 is reduced, while the voltage spread in Mode 2 is substantially increased. However, the main aim of this mode is achieving a safe discharge of each cell, reaching around 2.8 V, despite revealing a higher voltage spread in contrast to the initial conditions.

Table 5. Results for the three operation modes.

Mode	Cell	Initial Voltage per Cell	Final Voltage per Cell	ΔVmax (Initial voltage − Final voltage)	Balancing Time
1. Post-Charge Mode	1	4.2040 V	4.1265 V	0.0775 V	1000 s
	2	4.2000 V	4.1924 V	0.0076 V	300 s
	3	4.2356 V	4.1963 V	0.0393 V	3500 s
	4	4.2353 V	4.1944 V	0.0409 V	3500 s
	5	4.2613 V	4.2131 V	0.0482 V	3600 s
	6	4.1557 V	4.1582 V	-	-
	Voltage Spread	0.1056 V	0.0866 V
2. Pre-Charge Mode	1	3.2324 V	2.9013 V	0.3311 V	1900 s
	2	3.2324 V	2.8105 V	0.4219 V	1700 s
	3	3.2367 V	2.8789 V	0.3578 V	1800 s
	4	3.2249 V	2.8446 V	0.3803 V	1800 s
	5	3.2705 V	2.8658 V	0.4047 V	1800 s
	6	3.2481 V	2.8387 V	0.4094 V	1800 s
	Voltage Spread	0.0456 V	0.0908 V
3. Storage Mode	1	3.9529 V	3.8963 V	0.0566 V	9300 s
	2	3.9434 V	3.8866 V	0.0568 V	9300 s
	3	3.9537 V	3.8931 V	0.0606 V	9400 s
	4	3.9701 V	3.8987 V	0.0714 V	9600 s
	5	3.9497 V	3.8810 V	0.0687 V	9500 s
	6	3.9520 V	3.8969 V	0.0551 V	9300 s
	Voltage spread	0.0267 V	0.0177 V

Note: This table presents the results from the preceding figures, organized in a tabular format for better visualization; the data was obtained from the oscilloscope data capture. The Cell₆ in post-charge mode was under low-voltage conditions for this operation mode.

4. Discussion and Study Limitations

The possibility of implementing a passive balancing network as a subsystem to protect chargers and BMS in order to achieve more controlled charge and discharge cycles is verified. The implementation of a balancing network designed to ensure that the cells operate within low-balancing thresholds is a key issue in the current electric vehicular industry, as it enhances the performance of the battery, pack as mentioned in various sources cited in this article.

Passive balancing has already been applied to various battery chemistries, such as lithium-ion [34] and lithium iron phosphate [35]. It is hypothesized that this prototype could be adapted to multi-chemistry by adjusting the reference voltage (V_Ref) thresholds within the Arduino GIGA R1 firmware. Thus, the physical platform can be optimized for alternative commercial storage technologies, such as the following:

• Lithium iron phosphate (LiFePO₄): Configured with a software threshold for storage conditioning or V_Ref = 3.65 V: for top-balancing.
• Conventional lithium-ion (V_Ref = 3.20 V): Programmed with standard thresholds of 3.6 V for low-end conditioning and 4.20 V for post-charge clipping.

Although chemistries are characterized by open-circuit voltage curves with ultra-flat plateaus in their middle operating zones (such as the voltage level of LiFePO₄), they may introduce tracking challenges for fine SOC estimation. However, different chemistries also require different SOC behaviors and other approximate indicator, balancing thresholds, and thermal limits, and it is therefore emphasized that this prototype is not directly proportional and that experimental validation is required.

Finally, making an analysis of commercial charging systems for electric vehicles in Mexico City, there are several types of charging stations, broadly divided into two main categories: those found at home and public ones. Both generally have two levels; for home use, there is a Level 1 charger at 120 V (which can charge the car in 12 h) and a Level 2 charger at 230 V (with a charging time of 6–8 h at an approximate power output of 7 kW). Public charging points, on the other hand, offer 240 V fast charging or 480 V ultra-fast chargers [36]. Considering a standard 230 V, 7 kW Level 2 home charger, as this is the most common type in the country, and bearing in mind that, on average, these stations take 7 h to charge and add a further hour for balancing in Mode 1, the vehicle’s charging time would be 8 or 9 h at most when a charging-and-balancing process is implemented.

5. Conclusions

The results of the SSR balancer system for six cells show experimental verification in the prototype for balancing the individual modules in a 5.6 kWh battery pack. The waveforms shown demonstrate the capacity to equalize the voltage of the cells at three modes. For Mode 1, post-charge takes approximately 3500 s, reaching a voltage level of 4.20 V. Nevertheless, in this case, two cells were out of this reference voltage level because of the SOH limits of the operation. In the case of Mode 2, the results exhibited a balance around 2.8 V, where the operation of the module in the pre-charge process was validated with a period of time of approximately 1800 s due to the inherent curve of the LiPo cells. Finally, for the storage mode presented in this research, all of the cells reached around 3.8 V in a long period of time, i.e., about 9300 s. However, this mode could present the largest period of time during the process, becoming relevant for applications in this sort of chemistry.

Furthermore, by quantifying the amount of heat produced by the resistor, we demonstrated that the temperature is not excessively high and that it did not affect the performance of the balancer prototype. It should be noted that the thermal analysis of the resistors was conducted without any type of cooling and still helped to validate and implement it in the six-cell prototype.

The implementation of the GUI made human–machine communication more attractive and made it easier to use the device. The combination of the Arduino GIGA R1 Wi-Fi microcontroller and the Arduino Giga Shield Display was very convenient, as it allows the user to select balancing modes with its touch screen, monitor the balancing process in real time, function solely as a voltage meter for each cell, and estimate the approximate SOC of each module in the battery pack.

The construction and preliminary design of the battery pack was favorable for implementing the passive balancing strategy, as the reconditioning of some cells and the design and construction of a new pack served as a precedent for implementing the balancer under its operating conditions. In addition, the same laboratory is developing various prototypes to validate the 83 kW electric motorcycle, such as a dynamometer to characterize the electric motor, and a charger for the 5.6 kWh bank, which lacked a balancing network. The modular prototype presented can be integrated into this charger as a protection subsystem.

Finally, further research is considered in order to achieve a system that allows for the utilization of excess energy from the cell without the need to dissipate it as heat, as well as quantifying how many additional life cycles at a high SOC this prototype can have.