A Novel Low-Complexity Four-Way Parallel MDST Algorithm for GPU and Multicore CPU Architectures

Abstract

The Modified Discrete Sine Transform (MDST) is widely used in signal-processing applications where computational efficiency, latency, and energy consumption are critical design constraints. This paper introduces a low-complexity, parallel MDST algorithm that decomposes the transform into four independent computational sections, reducing arithmetic redundancy and enabling concurrent execution on GPU and multicore CPU architectures. The proposed implementation was evaluated on NVIDIA Jetson AGX Xavier, Jetson AGX Orin, and GeForce RTX 4090 GPUs, as well as on an Intel Core i9-14900K CPU. For isolated N = 34 transforms, the proposed formulation achieved GPU speedups of 7.55–76.85 relative to the classical MDST, depending on the platform and operating frequency, while CPU speedups ranged from 6.71 to 12.13 under controlled conditions. A complementary standard Linux experiment preserved a 6.58× CPU speedup, showing that the performance advantage does not depend on specialized core isolation. Compute-only measurements on the Jetson AGX Xavier further showed an approximately 99% reduction in GPU energy per transform. Memory profiling confirmed substantial reductions in global and local memory traffic. Because a single four-section transform provides insufficient parallelism to fully utilize a modern GPU, an additional batched implementation was developed to exploit inter-transform parallelism. On the Jetson AGX Orin, throughput reached approximately 82.17 × 106 transforms/s, with 98.34% SM activity and 80.84% SM throughput, demonstrating that the proposed decomposition is particularly effective for batched, multichannel, and high-throughput workloads. These results show that the proposed MDST reformulation combines reduced arithmetic and memory complexity with efficient deployment across heterogeneous parallel architectures.

1. Introduction

The information age poses multiple technical challenges for data processing and communication. High data volumes, especially for multimedia content, can consume significant energy, reducing device runtime, while resource-constrained devices tend to be low-power and usually slow.

Addressing these technical challenges often requires a combination of efficient algorithms and parallel processing.

Many modern applications require real-time processing. Real-time multimedia applications have evolved to the point that, to meet the demanding requirements in this area, the use of VLSI technologies or parallel processing is increasingly important. Thus, the effective use of parallel processing in software implementations and the development of innovative algorithms with reduced arithmetic complexity have become crucial.

Since the MDCT and MDST are computationally intensive, it is important to develop new algorithms with reduced arithmetic complexity that can be computed in parallel.

The literature describes efficient hardware implementations for the MDCT and MDST [1,2,3,4,5]. Other existing algorithms for the MDCT and MDST are better suited for a software implementation due to their irregular and complex computations [6,7,8,9], though a few can be implemented in parallel. Most existing algorithms used in hardware or software implementations cannot be used in parallel implementations, primarily due to their recursive structure, except [4] and [5], which have been used in VLSI implementations.

The main contributions of this work are:

• a new MDST reformulation that decomposes the transform into four independent computational sections while reducing arithmetic complexity;
• CUDA and multicore CPU implementations of the proposed algorithm;
• an experimental evaluation across multiple GPU architectures and a multicore CPU platform, including execution-time, memory-access, energy-consumption, and GPU-utilization analyses; and
• a comparison with a recent state-of-the-art MDST implementation.

The remainder of the paper is organized as follows: Section 2 presents the proposed MDST reformulation. Section 3 and Section 4 describe the experimental platforms and methodology. Section 5 reports the GPU and CPU results. Section 6 discusses the results and compares them with related work. Section 7 concludes the paper.

1.1. Background and Practical Relevance of MDCT/MDST

Transform-domain processing is widely used in signal processing because it provides compact spectral representations that facilitate spectral analysis, quantization, and compression. The Modified Discrete Cosine Transform (MDCT) and Modified Discrete Sine Transform (MDST) are lapped block transforms that can be interpreted as cosine- and sine-modulated, critically sampled analysis/synthesis filter-bank structures based on time-domain aliasing cancellation (TDAC) [10,11]. In their standard formulation, adjacent input frames typically overlap by 50%. The analysis stage deliberately introduces time-domain aliasing; in an unquantized analysis/synthesis chain, this aliasing is canceled during synthesis by the overlap-add process when the analysis and synthesis windows satisfy the required perfect-reconstruction conditions [10].

This overlapping structure reduces discontinuities between successive processing blocks and mitigates blocking artifacts, making it particularly valuable for audio and speech coding. For correlated audio signals, the MDCT provides good energy compaction and a high-resolution spectral representation suitable for psychoacoustic bit allocation and coefficient quantization. Accordingly, the MDCT is used in widely deployed perceptual audio coders, including MP3, AAC, Dolby Digital (AC-3), and Enhanced AC-3 [12,13,14]. In MP3, the MDCT operates on the output of a polyphase filter bank, with long and short transform blocks selected based on the signal’s temporal characteristics, particularly around transient events [6,12]. AC-3 employs a windowed MDCT/TDAC transform to obtain spectral coefficients, which are then quantized using a psychoacoustically motivated bit-allocation procedure [13].

The MDST is closely related to the MDCT and provides the corresponding sine-modulated representation. The MDCT and MDST can be treated within a unified TDAC analysis/synthesis framework and combined in common computational structures [9,15,16]. Cosine/sine transform pairs are relevant not only to audio coding but also to subband analysis/synthesis and transform-domain signal processing. In particular, the inherent 50% overlap of MDCT/MDST frames can be advantageous in transform-domain filtering by reducing artifacts associated with independent block processing [17]. Consequently, efficient MDCT/MDST computation is of interest wherever repeated real-time or high-throughput transform processing is required.

Despite these advantages, efficient MDCT/MDST implementation remains challenging. Direct evaluation has quadratic arithmetic complexity and requires many weighted multiply–accumulate operations. Moreover, overlapping input frames can increase memory traffic unless data reuse is explicitly exploited. Practical implementations must also manage intermediate storage and the data dependencies introduced by fast or recursive formulations. These constraints are especially critical in real-time audio, embedded systems, and other resource-constrained applications, where latency, memory bandwidth, and energy consumption are constrained. Fast algorithms therefore exploit transform symmetries, matrix factorizations, recursive formulations, and common subexpressions to reduce the number of multiplications and additions [1,2,3,4,5,6,7,8,9,15,16].

Efficiently mapping such algorithms onto modern parallel processors introduces an additional challenge. Low arithmetic complexity alone does not guarantee high performance on GPUs or multicore CPUs: strong data dependencies, irregular memory-access patterns, and insufficient independent work can limit achievable parallelism. Conversely, decomposing the computation into independent sections exposes concurrency and enables more effective use of programmable parallel architectures. This trade-off motivates the four-way MDST decomposition examined in this work.

1.2. Literature Review

The existing approaches for efficient MDCT/MDST computation can be broadly grouped into three categories: (a) recursive architectures, (b) fast algorithms based on transform decomposition and factorization, and (c) dedicated VLSI/systolic-array implementations.

A first important class comprises recursive MDCT/MDST algorithms, developed primarily to reduce hardware complexity and provide regular structures suitable for VLSI implementation. Chen et al. [1] reformulated the MDCT and IMDCT using data rearrangement and Chebyshev polynomial representations, yielding regular, recursive, infinite-impulse-response structures. Their architecture was experimentally validated via an ASIC implementation, delivering improved computational throughput while maintaining a relatively simple hardware organization. Lei et al. [2] subsequently proposed a unified recursive architecture for MDCT and IMDCT based on DCT-II and DST-II kernels. Their formulation substantially reduced pre-processing operations and recursive-kernel complexity, requiring only N/8 + 1 computational cycles per output sequence, and supporting multiple transform lengths within a common hardware architecture. Lai et al. [3] extended this approach to a common architecture capable of computing MDCT, MDST, IMDCT, and IMDST. The approach employs a recursively generated DCT-IV kernel with selectable parameters and enables simultaneous computation of MDCT and MDST coefficients. For a 512-point transform, the authors reported reductions of 50.21% in multiplications and 24.97% in additions relative to an earlier recursive solution, and FPGA experiments demonstrated the feasibility of the architecture for real-time audio coding. Although recursive structures provide attractive area efficiency and regularity, their inherent data dependencies can limit the degree of fine-grained parallelism available to contemporary massively parallel processors.

A second group comprises fast computational algorithms based on transform identities, exploitation of symmetry, and matrix or signal-flow decomposition. Britanak and Rao [6] developed an efficient forward/inverse MDCT implementation for MPEG-1/2 Layer III by exploiting the even-anti-symmetry of the MDCT and reducing computation to short DCT-II/DST-II and inverse DCT-III/DST-III modules. This approach applies to transform lengths divisible by four and was specifically optimized for the 12- and 36-point transforms used in MP3 coding. Lee [7] has further reduced arithmetic complexity by first converting the forward and backward MDCT to a DCT-IV and then evaluating it via a scaled DCT-II (SDCT-II). The same SDCT-II module can be used in both directions, simplifying implementation and reducing the number of arithmetic operations. Nikolajevic and Fettweis [8] pursued a related symmetry-based decomposition tailored to MP3 block sizes. Their algorithm reduces the number of additions, removes one computational stage, and decreases the size of the largest shuffle block, characteristics particularly advantageous for DSP implementations with parallel datapaths.

Britanak and Rao [16] also investigated a unified MDCT/MDST formulation for the evenly stacked analysis/synthesis system, exploiting relationships and symmetry properties between the cosine and sine transforms to derive a common fast computational procedure. This concept was further developed by Britanak and Arriëns [15], who derived an identical computational structure for forward and backward MDCT/MDST processing based on a DCT-IV-centered formulation. The resulting regular signal-flow graph yields sparse matrix factorizations and allows the same structure to be reused in both analysis and synthesis filter banks. A related but conceptually distinct solution was introduced by Britanak [9], in which the computation is constructed exclusively from Givens–Jacobi rotations. This eliminates the need for reduced-size DFT, DCT, or DST modules and produces simple, regular computational structures that are particularly attractive for hardware realization and integer-transform implementations. These factorization-based methods achieve substantial reductions in arithmetic complexity; however, their computational graphs were primarily developed in the context of sequential DSP processing or dedicated hardware structures rather than explicitly restructuring the MDST into independent tasks intended for execution on general-purpose GPU and multicore CPU architectures.

The third category is represented by dedicated systolic-array implementations of the MDST. Chiper and Cracan [4] reformulated the MDST into two regular pseudo-cycle convolutions of identical form. Both structures can be executed on the same linear systolic array using interleaving, reducing hardware complexity while preserving the high throughput, regular local interconnections, and low I/O overhead characteristic of systolic architectures. This approach was subsequently extended in [5] through two systolic algorithms based on pseudo-circular correlations and pseudo-cycle convolutions. Because the resulting structures have identical forms and lengths, they can share a single linear systolic array; an additional formulation replaces general multipliers with constant multipliers to further reduce implementation complexity. These solutions demonstrate that restructuring the MDST into regular computational structures is highly beneficial for parallel hardware. Nevertheless, they are specifically tailored to FPGA/ASIC-oriented systolic architectures rather than programmable GPU or multicore CPU execution.

Overall, the literature shows a clear evolution from recursive, low-area architectures toward increasingly regular transform factorizations and specialized parallel hardware. Recursive approaches [1,2,3] primarily optimize hardware cost and reuse; fast-transform approaches [6,7,8,9,15,16] reduce arithmetic complexity through symmetry and mathematical decomposition; and systolic solutions [4,5] explicitly exploit concurrency in dedicated VLSI structures. A less explored direction is reformulating the MDST into independent computational sections that simultaneously reduce arithmetic and memory-access complexity and can be directly mapped onto programmable parallel architectures. This observation motivates the approach proposed in this work, in which the MDST is decomposed into four independent computational sections and evaluated on both CUDA-enabled GPUs and a modern multicore CPU.

2. A Parallel Algorithm for the Computation of 1D MDST

The 1-D MDST is defined as:

$$Y(k)=\sum _{i=0}^{N-1}x\left(i\right)\cdot \mathit{sin}[(2i+1+N/2)(2k+1)\alpha ]$$

(1)

for k = 0, …, M − 1, where M = N/2 and $\alpha ={\displaystyle \frac{\pi }{2N}}$.

In order to reformulate the basic form of the algorithm given by Equation (1), in the case where M is a prime number, we introduced some restructuring of the input sequences defined below:

$$x_S\left(i\right)=x\left(i\right)\cdot \mathit{sin}[(2i+1+N/2)\alpha ]$$

(2)

$${\mathrm{x}}_{\mathrm{a}}\left(i\right)=x_{\mathrm{S}}\left(i\right)+x_S\left(N-1-i\right)$$

(3)

$${\mathrm{x}}_{\mathrm{b}}\left(i\right)=(-1{)}^{i+1}[x_S\left(i\right)-x_S\left(N-1-i\right)]$$

(4)

and

$$x_{\mathit{ca}}(M-1)=x_a(M-1)$$

(5)

$$x_{\mathit{ca}}\left(i\right)=x_a\left(i\right)-x_{\mathit{ca}}(i+1)$$

(6)

for $i=\overline{M-2, 0}$.

$$x_{\mathit{cb}}(M-1)=x_b(M-1)$$

(7)

$$x_{\mathit{cb}}\left(i\right)=x_b\left(i\right)-x_{\mathit{cb}}\left(i+1\right)$$

(8)

for $i=\overline{M-2, 0}$.

Using these auxiliary input sequences and appropriate permutations of the indices, we can reformulate the MDST computation, as shown below.

To illustrate our method, we have chosen the prime number M = 17, which is not very large.

To express the following relations concisely, we noted:

$$C=\left[\begin{array}{ccccc}1& 1& 2& 0& -1\\ 1& -1& -1& 1& -2\\ 1& 1& -2& 0& 1\\ 1& -1& 1& -1& 2\end{array}\right]$$

(9)

$$P=\left[\begin{array}{cccc}1& 1& 1& 1\\ 1& -1& 1& -1\\ 1& 0& -1& 0\\ 1& 2& -1& -2\\ 0& 1& 0& -1\end{array}\right]$$

(10)

$$D=\left[\begin{array}{ccccc}1/4& 0& 0& 0& 0\\ 0& 1/4& 0& 0& 0\\ 0& 0& 1/4& 0& 0\\ 0& 0& 0& 1/4& 0\\ 0& 0& 0& 0& 1/2\end{array}\right]$$

(11)

Using the above auxiliary input and sub-expression sharing technique to reduce arithmetic complexity, we obtained the following equations that can be efficiently computed in parallel and have lower arithmetic complexity, enabling an efficient implementation on a GPU that is significantly faster than other existing algorithms, including the classical algorithm.

First, we computed the following auxiliary output sequences T_a(k) and Y_a(k):

$$\begin{array}{l}\left[\begin{array}{c}{T}_a(16)\\ T_a(15)\\ T_a(13)\\ T_a(9)\end{array}\right]=C\cdot D\cdot \mathit{diag}\left(P\cdot \left[\begin{array}{c}c(3)\\ c(6)\\ c(5)\\ c(7)\end{array}\right]\right)\cdot P\cdot \left[\begin{array}{c}{x}_{\mathit{ca}}(3)+x_{\mathit{ca}}(14)\\ x_{\mathit{ca}}(7)+x_{\mathit{ca}}(10)\\ x_{\mathit{ca}}(5)+x_{\mathit{ca}}(12)\\ x_{\mathit{ca}}(6)+x_{\mathit{ca}}(11)\end{array}\right]+\\ +C\cdot D\cdot \mathit{diag}\left(P\cdot \left[\begin{array}{c}c(8)\\ c(1)\\ c(2)\\ c(4)\end{array}\right]\right)\cdot P\cdot \left[\begin{array}{c}{x}_{\mathit{ca}}(8)+x_{\mathit{ca}}(9)\\ x_{\mathit{ca}}(4)+x_{\mathit{ca}}(13)\\ x_{\mathit{ca}}(2)+x_{\mathit{ca}}(15)\\ x_{\mathit{ca}}(1)+x_{\mathit{ca}}(16)\end{array}\right]\end{array}$$

(12)

where c(k) = cos(16 ⋅ kα)

And

$$Y_a\left(2\right)=\left[x_{\mathit{ca}}\left(0\right)+2\cdot T_a\left(16\right)\right]\cdot \mathit{cos}(8\cdot \alpha )$$

(13)

$$Y_a\left(4\right)=\left[x_{\mathit{ca}}\left(0\right)+2\cdot T_a\left(15\right)\right]\cdot \mathit{cos}(16\cdot \alpha )$$

(14)

$$Y_a\left(8\right)=\left[x_{\mathit{ca}}\left(0\right)+2\cdot T_a\left(13\right)\right]\cdot \mathit{cos}(32\cdot \alpha )$$

(15)

$$Y_a\left(16\right)=\left[x_{\mathit{ca}}\left(0\right)+2\cdot T_a\left(9\right)\right]\cdot \mathit{cos}(64\cdot \alpha )$$

(16)

$$Y_a(1)=-Y_a(16)$$

(17)

and also

$$\begin{array}{l}\left[\begin{array}{c}{T}_a(11)\\ T_a(12)\\ T_a(10)\\ T_a(14)\end{array}\right]=C\cdot D\cdot \mathit{diag}\left(P\cdot \left[\begin{array}{c}c(1)\\ c(2)\\ c(4)\\ c(8)\end{array}\right]\right)\cdot P\cdot \left[\begin{array}{c}{x}_{\mathit{ca}}(3)+x_{\mathit{ca}}(14)\\ x_{\mathit{ca}}(7)+x_{\mathit{ca}}(10)\\ x_{\mathit{ca}}(5)+x_{\mathit{ca}}(12)\\ x_{\mathit{ca}}(6)+x_{\mathit{ca}}(11)\end{array}\right]+\\ +C\cdot D\cdot \mathit{diag}\left(P\cdot \left[\begin{array}{c}c(3)\\ c(6)\\ c(5)\\ c(7)\end{array}\right]\right)\cdot P\cdot \left[\begin{array}{c}{x}_{\mathit{ca}}(8)+x_{\mathit{ca}}(9)\\ x_{\mathit{ca}}(4)+x_{\mathit{ca}}(13)\\ x_{\mathit{ca}}(2)+x_{\mathit{ca}}(15)\\ x_{\mathit{ca}}(1)+x_{\mathit{ca}}(16)\end{array}\right]\end{array}$$

(18)

$$Y_a\left(12\right)=\left[x_{\mathit{ca}}\left(0\right)+2\cdot T_a\left(11\right)\right]\cdot \mathit{cos}(48\cdot \alpha )$$

(19)

$$Y_a\left(10\right)=\left[x_{\mathit{ca}}\left(0\right)+2\cdot T_a\left(12\right)\right]\cdot \mathit{cos}(40\cdot \alpha )$$

(20)

$$Y_a\left(14\right)=\left[x_{\mathit{ca}}\left(0\right)+2\cdot T_a\left(10\right)\right]\cdot \mathit{cos}(56\cdot \alpha )$$

(21)

$$Y_a\left(6\right)=\left[x_{\mathit{ca}}\left(0\right)+2\cdot T_a\left(14\right)\right]\cdot \mathit{cos}(24\cdot \alpha )$$

(22)

$$Y_a(3)=-Y_a(14)$$

(23)

$$Y_a(5)=-Y_a(12)$$

(24)

$$Y_a(7)=-Y_a(10)$$

(25)

Then, we computed the next auxiliary output sequences T_b(k) and Y_b(k):

$$\begin{array}{l}\left[\begin{array}{c}{T}_b(16)\\ T_b(15)\\ T_b(13)\\ T_b(9)\end{array}\right]=C\cdot D\cdot \mathit{diag}\left(P\cdot \left[\begin{array}{c}c(3)\\ c(6)\\ c(5)\\ c(7)\end{array}\right]\right)\cdot P\cdot \left[\begin{array}{c}{x}_{\mathit{cb}}(3)+x_{\mathit{cb}}(14)\\ x_{\mathit{cb}}(7)+x_{\mathit{cb}}(10)\\ x_{\mathit{cb}}(5)+x_{\mathit{cb}}(12)\\ x_{\mathit{cb}}(6)+x_{\mathit{cb}}(11)\end{array}\right]+\\ +C\cdot D\cdot \mathit{diag}\left(P\cdot \left[\begin{array}{c}c(8)\\ c(1)\\ c(2)\\ c(4)\end{array}\right]\right)\cdot P\cdot \left[\begin{array}{c}{x}_{\mathit{cb}}(8)+x_{\mathit{cb}}(9)\\ x_{\mathit{cb}}(4)+x_{\mathit{cb}}(13)\\ x_{\mathit{cb}}(2)+x_{\mathit{cb}}(15)\\ x_{\mathit{cb}}(1)+x_{\mathit{cb}}(16)\end{array}\right]\end{array}$$

(26)

$$Y_b\left(2\right)=\left[x_{\mathit{cb}}\left(0\right)+2\cdot T_b\left(16\right)\right]\cdot \mathit{cos}(8\cdot \alpha )$$

(27)

$$Y_b\left(4\right)=\left[x_{\mathit{cb}}\left(0\right)+2\cdot T_b\left(15\right)\right]\cdot \mathit{cos}(16\cdot \alpha )$$

(28)

$$Y_b\left(8\right)=\left[x_{\mathit{cb}}\left(0\right)+2\cdot T_b\left(13\right)\right]\cdot \mathit{cos}(32\cdot \alpha )$$

(29)

$$Y_b\left(16\right)=\left[x_{\mathit{cb}}\left(0\right)+2\cdot T_b\left(9\right)\right]\cdot \mathit{cos}(64\cdot \alpha )$$

(30)

$$Y_b(1)=-Y_b(16)$$

(31)

$$\begin{array}{l}\left[\begin{array}{c}{T}_b(11)\\ T_b(12)\\ T_b(10)\\ T_b(14)\end{array}\right]=C\cdot D\cdot \mathit{diag}\left(P\cdot \left[\begin{array}{c}c(1)\\ c(2)\\ c(4)\\ c(8)\end{array}\right]\right)\cdot P\cdot \left[\begin{array}{c}{x}_{\mathit{cb}}(3)+x_{\mathit{cb}}(14)\\ x_{\mathit{cb}}(7)+x_{\mathit{cb}}(10)\\ x_{\mathit{cb}}(5)+x_{\mathit{cb}}(12)\\ x_{\mathit{cb}}(6)+x_{\mathit{cb}}(11)\end{array}\right]+\\ +C\cdot D\cdot \mathit{diag}\left(P\cdot \left[\begin{array}{c}c(3)\\ c(6)\\ c(5)\\ c(7)\end{array}\right]\right)\cdot P\cdot \left[\begin{array}{c}{x}_{\mathit{cb}}(8)+x_{\mathit{cb}}(9)\\ x_{\mathit{cb}}(4)+x_{\mathit{cb}}(13)\\ x_{\mathit{cb}}(2)+x_{\mathit{cb}}(15)\\ x_{\mathit{cb}}(1)+x_{\mathit{cb}}(16)\end{array}\right]\end{array}$$

(32)

$$Y_b\left(12\right)=\left[x_{\mathit{cb}}\left(0\right)+2\cdot T_b\left(11\right)\right]\cdot \mathit{cos}(48\cdot \alpha )$$

(33)

$$Y_b\left(10\right)=\left[x_{\mathit{cb}}\left(0\right)+2\cdot T_b\left(12\right)\right]\cdot \mathit{cos}(40\cdot \alpha )$$

(34)

$$Y_b\left(14\right)=\left[x_{\mathit{cb}}\left(0\right)+2\cdot T_b\left(10\right)\right]\cdot \mathit{cos}(56\cdot \alpha )$$

(35)

$$Y_b\left(6\right)=\left[x_{\mathit{cb}}\left(0\right)+2\cdot T_b\left(14\right)\right]\cdot \mathit{cos}(24\cdot \alpha )$$

(36)

$$Y_b(3)=-Y_b(14)$$

(37)

$$Y_b(5)=-Y_b(12)$$

(38)

$$Y_b(7)=-Y_b(10)$$

(39)

Equations (12)–(17), (18)–(24), (26)–(30) and (32)–(36) are computed in parallel on a separate processor. The number of multiplications has been significantly reduced. Thus, in the matrix operations in Equations (12), (18), (26) and (32), there are only 10 multiplications in each.

Then we computed another auxiliary output sequence T(k) as follows:

$$T\left(2k\right)=(-1{)}^k\cdot 2Y_a(k)$$

(40)

$$T(M-2k)=(-1{)}^k\cdot 2Y_b(k)$$

(41)

for $k=\overline{1,(M-1)/2}$.

Using the auxiliary output sequence T(k), we finally compute the output sequence recursively as follows:

$$Y(0)={\displaystyle \sum _{i=0}^{M-1}{x}_a(i)}$$

(42)

$$Y(k)=T(k)+Y(k-1)$$

(43)

for $k=\overline{1,(M-1)}$.

Figure 1 illustrates the execution strategy of the proposed four-way parallel MDST algorithm derived from the mathematical reformulation presented above. This organization highlights both the algorithmic decomposition and its direct mapping onto CPU and parallel GPU architectures.

Figure 1. Execution strategy of the proposed four-way parallel MDST algorithm.

3. Overview of the Development Systems Used in MDST Analysis

The experimental setup includes two embedded computing platforms (Jetson AGX Xavier and Jetson AGX Orin) and a high-end desktop based on an RTX 4090 GPU (see Table 1). These systems were selected to highlight the trade-offs among energy efficiency, computational density, and deployment flexibility in real-world applications.

Table 1. The main features of the development systems used in this research.

Platform	Compute Architecture & Technology	Parallel Processing Capability	AI/Numeric Performance	Memory Configuration	Host Processing Unit
Jetson AGX Xavier	Volta-based GPU fabricated in 12 nm (TSMC)	512 CUDA cores; 64 Tensor units	32 TOPS (INT8); 1.41 TFLOPS (FP32)	32 GB LPDDR4X, 256-bit interface, 136.5 GB/s	8-core NVIDIA Carmel (ARM v8.2), up to 2.3 GHz
Jetson AGX Orin	Ampere GPU, produced on 7–8 nm node	2048 CUDA cores; 64 Tensor units	275 TOPS (INT8); 10.6 TFLOPS (FP32)	64 GB LPDDR5, 256-bit, 204.8 GB/s	12-core ARM Cortex-A78AE, up to 2.2 GHz
Desktop (RTX 4090 GPU)	Ada Lovelace architecture, 5 nm process	16,384 CUDA cores; 512 Tensor units	1300 TOPS (INT8); 82.58 TFLOPS (FP32)	24 GB GDDR6X, 384-bit bus, ~1 TB/s bandwidth	Intel Core i9-14900K (24 cores), up to 4.4 GHz

From an energy-efficiency perspective, the embedded platforms are designed for edge deployment, where power consumption and thermal constraints are critical. The Jetson AGX Xavier, built on the Volta architecture, delivers modest computational throughput while maintaining a relatively low power envelope, making it suitable for latency-sensitive, resource-constrained scenarios. Its successor, the Jetson AGX Orin, significantly improves computing density by leveraging a newer Ampere-based design and a more advanced fabrication process. This results in a substantial increase in AI inference capability (in TOPS—Tera Operations Per Second) without a proportional rise in power consumption, thus offering a better performance-per-watt ratio compared to the Xavier platform.

In contrast, the desktop system with an RTX 4090 GPU prioritizes maximum computational performance over efficiency under strict power budgets. The Ada Lovelace architecture enables extremely high parallelism and supports a wide range of numerical precisions, including lower-bit formats optimized for AI workloads. However, these capabilities come at the cost of significantly higher power consumption and reduced suitability for embedded or mobile deployments. Such systems are therefore better suited for offline training, large-scale simulation, or high-throughput data processing tasks where energy constraints are less restrictive.

Another key distinction lies in system integration. Embedded platforms integrate CPU and GPU resources within a unified memory architecture, reducing data-transfer overhead and improving efficiency in real-time processing pipelines. By contrast, the desktop configuration relies on discrete components, which, while more powerful, introduce additional latency and energy overhead due to data movement across separate memory hierarchies.

Overall, the comparison shows that while desktop-class GPUs deliver superior raw performance, embedded systems offer a more balanced solution for mobility applications, where energy efficiency, compactness, and real-time capabilities are essential design constraints.

Overall, the architectural progress of GPUs over time demonstrates a clear shift toward enhanced precision and flexibility, allowing GPUs to better accommodate heterogeneous workload requirements. This evolution supports optimized trade-offs between computational accuracy, performance, and energy efficiency, which are critical factors in both data center and edge deployment scenarios.

4. Materials and Methods

The study detailed in this paper introduces an innovative implementation of the Modified Discrete Sine Transform (MDST), organized into four independent computational sections that operate concurrently. For benchmarking, a reference implementation based on the traditional formulation of the transform was developed in C and executed under identical conditions on all target platforms (Table 1). Furthermore, a parallel configuration was considered, in which four execution threads were mapped to distinct CUDA cores (in the first main analysis) and to CPU cores (in the second main analysis). This approach was adopted to isolate the performance enhancements attributable to the proposed algorithmic restructuring from those resulting solely from hardware scaling factors such as clock frequency or architectural improvements.

4.1. GPU Execution Time Methodology

For GPU analysis, the experimental workflow consists of three consecutive stages. First, input data is transferred from the host (CPU) memory to the device (GPU) memory. Second, the transform is computed using either the reference implementation or the proposed MDST algorithm, with four parallel sections. Finally, the resulting data is copied back from the GPU to the CPU. The reported execution times include the cumulative duration of all three stages, thereby reflecting the end-to-end processing cost. This measurement should therefore be interpreted as an end-to-end single-transform GPU offload scenario, in which host-to-device transfer, kernel execution, and device-to-host transfer are all included. For such a small transform, these fixed transfer and launch overheads may account for a significant fraction of the total latency; the high-throughput batched regime is analyzed separately in Section 5.3. The computational component encompasses both arithmetic operations executed on CUDA cores and the memory access operations required by the algorithm.

To complement the GPU-based evaluation, an additional set of experiments was conducted on the CPU. In this case, the same algorithmic structure was implemented with multi-threaded execution, enabling a direct comparison between GPU acceleration and CPU parallelization in terms of execution time and scalability.

The input samples were generated pseudo-randomly at the beginning of each measurement sequence using the standard C library rand() function. The pseudo-random number generator was initialized with srand(time(NULL)); therefore, the seed was determined by the system time at the beginning of each execution. For a transform length of N = 34, 34 input samples were generated according to:

$$x\left[i\right]={\displaystyle \frac{\mathit{rand}\left(\right)}{\mathit{RAND}\_\mathit{MAX}}}, i=0,\dots ,33,$$

(44)

resulting in input values distributed over the interval [0, 1]. Consequently, different measurement sequences generally used different input data. The exact numerical input sequence did not need to be identical across experiments because the objective of the measurements was to evaluate execution time rather than the numerical response to a specific input dataset. Moreover, because GPU execution relies on SIMD (Single Instruction, Multiple Data) principles, the implementation uses fused multiply–add operations at the hardware level. These operations execute with constant latency, independent of operand values, so the statistical distribution of the input data does not significantly affect execution time.

In all experiments, the proposed MDST implementation was evaluated with an input transform length of N = 34 samples, yielding M = N/2 = 17 output coefficients; see relation (1). The same transform size was used for all CPU and GPU measurements unless otherwise specified.

Each reported measurement is the average of 10,000 consecutive execution cycles. For statistical robustness, 100 independent measurement sets were collected for each tested configuration. From these datasets, descriptive statistics, including the mean, standard deviation, and the minimum and maximum execution times, were computed. All experiments were conducted with the GPU and CPU operating at their minimum frequencies to evaluate algorithmic efficiency under constrained conditions and to approximate worst-case performance scenarios while maintaining reduced power consumption. In addition to the minimum-frequency evaluation, all experiments were repeated with both the GPU and CPU operating at their maximum supported frequencies to assess peak performance and analyze the impact of frequency scaling on execution time.

The GPU implementations were deployed as CUDA kernels, with each parallel section of the MDST algorithm mapped to a distinct CUDA core. The proposed CUDA kernel was launched using a grid of four blocks, with one thread per block (<<<4,1>>>). Each thread executed one of the four independent computational sections of the proposed MDST decomposition. Unless otherwise specified, all data structures, including inputs, outputs, and intermediate variables, were allocated in global memory. Memory allocation and CUDA context initialization were performed before the timed region and were therefore excluded from the reported execution times. The timed interval included host-to-device transfer, kernel launch and execution, and device-to-host transfer.

GPU timing measurements were performed using the CUDA event mechanism, which provides sub-microsecond resolution [18]. Specifically, event-based synchronization primitives were used to accurately capture the elapsed time between kernel invocation and completion. This approach is widely recognized as a reliable method for evaluating GPU performance and is commonly used in many papers [19,20,21,22,23,24].

All applications were compiled with the NVIDIA CUDA compiler (nvcc), which is included in the JetPack software (version 6.2) development kit. To ensure optimal performance, architecture-specific compilation flags were used for each target platform, enabling the generated binaries to fully exploit the underlying hardware. The general compilation command follows this structure: nvcc source_file.cu -o executable_name -arch=sm_xx.

For the execution-time comparison, both implementations used double-precision arithmetic and were compiled with the same NVIDIA nvcc toolchain and exactly the same compilation options on each platform. The architecture identifier (sm_xx) corresponds to the compute capability of the target GPU: sm_72 for the Volta architecture, sm_87 for the Ampere architecture, and sm_89 for the Ada Lovelace architecture. No additional optimization flags, such as -O3, --use_fast_math, or implementation-specific compiler options, were applied to either implementation. Consequently, both algorithms were subject to the same compiler optimization and instruction-generation policy, including any FMA fusion performed automatically by the compiler. No FMA-related option was selectively enabled or disabled for either implementation.

4.2. GPU Energy-Consumption Measurement Methodology

Energy consumption was included as a complementary evaluation criterion because execution time alone does not fully characterize the efficiency of an algorithm intended for embedded and resource-constrained systems. A reduction in execution time does not necessarily imply a proportional reduction in energy consumption, since higher computational activity or operating frequency may increase instantaneous power. Therefore, an energy analysis was conducted to determine whether the execution-time improvements achieved by the proposed four-section decomposition are accompanied by a reduction in the electrical energy required to perform the transform.

This distinction is particularly relevant for embedded and edge-computing platforms, where the available power budget, thermal constraints, and battery capacity may be as important as execution latency. The purpose of the present energy analysis is therefore primarily algorithmic: it evaluates the energy consequences of replacing the classical MDST formulation with the proposed implementation under identical hardware and operating conditions. It is not intended as a cross-platform energy ranking of the evaluated GPU and CPU architectures. Such a comparison would require equivalent power-measurement boundaries and instrumentation on all platforms.

The compute-only GPU energy consumption of the two CUDA implementations was measured on the NVIDIA Jetson AGX Xavier platform using the onboard INA3221 power-monitoring circuitry. The objective of this analysis was to quantify exclusively the electrical energy drawn from the GPU power rail during active CUDA kernel execution for the classical single-section algorithm (given by relation (1)) and the novel four-section implementations of the MDST algorithm. Accordingly, the measurement boundary was restricted to GPU computation. Host-side pre-processing, host-to-device memory transfers, device-to-host transfers, and all other CPU-side operations were performed outside the monitored interval and were therefore excluded from the reported energy values.

This measurement strategy was intentionally adopted to isolate the energy cost of the computational phase executed on the GPU and to enable a direct comparison between the two CUDA implementations, independent of data transfer and host processing overheads. Consequently, all energy quantities reported in this analysis should be interpreted as compute-only GPU-rail energy metrics, rather than as end-to-end energy consumption of the complete processing pipeline.

During each experiment, the GPU supply voltage and current were periodically sampled from the INA3221 monitoring interface. For the i-th sample, the instantaneous GPU power was determined from the measured voltage and current as:

$$P_i=V_i·I_i$$

(45)

where P_i denotes the instantaneous GPU power, V_i the GPU supply voltage, and I_i the corresponding current. Because the voltage and current values provided by the monitoring interface are expressed in millivolts and milliamperes, respectively, the instantaneous power in watts was computed as:

$$P_i\left[W\right]=V_i\left[\mathit{mV}\right]·I_i\left[\mathit{mA}\right]/{10}^6$$

(46)

Power samples were acquired by an independent monitoring thread at a nominal sampling interval of 5 ms throughout the CUDA computation interval. Since the actual acquisition instants are not assumed to be perfectly uniform, the time stamps associated with individual measurements were retained explicitly. The total compute-only GPU energy was then obtained by numerical integration of the measured power profile using the trapezoidal rule:

$$E_{\mathit{GPU}}={\displaystyle \sum _{i=1}^{M-1}}\left[\left({\displaystyle \frac{P_i+P_{i+1}}{2}}\right)·\left(t_{i+1}-t_i\right)\right]$$

(47)

Here, M denotes the total number of power samples acquired, and t_i is the timestamp associated with the i-th sample. The resulting quantity, E_GPU, is expressed in joules and represents the electrical energy supplied exclusively to the GPU power rail over the interval during which the CUDA workload was executed.

Because the duration of an individual kernel invocation is considerably shorter than the sampling period of the power-monitoring circuitry, each CUDA kernel was executed repeatedly within a single monitored interval. N_iter (equal to 2,000,000) denotes the number of kernel invocations performed during one measurement. The compute-only GPU energy normalized to a single kernel invocation was therefore calculated as:

$$E_{\mathit{compute}/\mathit{kernel}}={\displaystyle \frac{E_{\mathit{GPU}}}{N_{\mathit{iter}}}}$$

(48)

This normalization provides a directly comparable, implementation-level energy metric and is independent of the number of repeated kernel invocations required to achieve a sufficiently long, stable measurement interval. In the Section 5, this quantity is reported in microjoules per kernel invocation (µJ/kernel).

The mean GPU power during active CUDA computation was calculated as:

$$P_{\mathit{avg}}={\displaystyle \frac{E_{\mathit{GPU}}}{T_{\mathit{meas}}}}$$

(49)

where T_meas denotes the complete duration of the monitored CUDA execution interval. This quantity represents the mean electrical power drawn by the GPU rail during the compute-only measurement window.

In addition to the total compute-only GPU energy, a baseline-corrected estimate was derived in order to distinguish the incremental energy associated with active CUDA processing from the baseline power required to maintain the GPU in its operating state. Prior to each workload measurement, the mean GPU idle power, P_idle, was determined when no CUDA kernel was executing. The baseline energy corresponding to the same measurement duration was estimated as:

$$E_{\mathit{idle}}=P_{\mathit{idle}}{·T}_{\mathit{meas}}$$

(50)

The incremental, or dynamic, compute-only GPU energy was subsequently calculated as:

$$E_{\mathit{dynamic}}=E_{\mathit{GPU}}{-P_{\mathit{idle}}·T}_{\mathit{meas}}$$

(51)

The corresponding baseline-corrected energy per kernel invocation was determined as:

$$E_{\mathit{dynamic}/\mathit{kernel}}={\displaystyle \frac{E_{\mathit{GPU}}{-P_{\mathit{idle}}·T}_{\mathit{meas}}}{N_{\mathit{iter}}}}$$

(52)

Two complementary compute-only energy metrics were therefore retained. The first, E_{compute/kernel}, represents the total energy drawn from the GPU power rail during CUDA computation, normalized to one kernel invocation. This quantity includes the baseline electrical power required to keep the GPU operational during the monitored interval. The second metric, E_{dynamic/kernel}, represents the incremental GPU-rail energy above the measured idle level and provides a baseline-corrected estimate of the additional electrical energy associated with active CUDA computation. This quantity should be interpreted as an incremental device-level energy metric.

For quantitative comparison of the two implementations, the relative reduction in compute-only GPU energy achieved by the four-section implementation relative to the single-section implementation was calculated as:

$$R_E=\left(1-{\displaystyle \frac{E_{\mathit{compute}/\mathit{kernel},4}}{E_{\mathit{compute}/\mathit{kernel},1}}}\right)·100\%$$

(53)

Here, E_{compute/kernel,1} and E_{compute/kernel,4} denote the compute-only GPU energy per kernel invocation for the single- and four-section CUDA implementations, respectively.

An analogous metric was used for the energy with baseline correction:

$$R_{E,\mathit{dyn}}=\left(1-{\displaystyle \frac{E_{\mathit{dynamic}/\mathit{kernel},4}}{E_{\mathit{dynamic}/\mathit{kernel},1}}}\right)·100\%$$

(54)

The relative energy-efficiency gain was also expressed through the energy ratio:

$$F_E={\displaystyle \frac{E_{\mathit{compute}/\mathit{kernel},1}}{E_{\mathit{compute}/\mathit{kernel},4}}}$$

(55)

Values of FE greater than unity indicate that the four-section implementation requires less compute-only GPU energy per kernel invocation than the single-section implementation, and larger values indicate proportionally greater energy savings.

During all energy measurements, the GPU operating frequency was explicitly locked at the investigated value and maintained constant throughout the complete monitored workload interval. This eliminated GPU dynamic frequency transitions as a source of variability between the implementations being compared.

For each operating condition, the Section 5 reports the mean idle GPU power, the mean GPU power during active CUDA execution, the compute-only GPU energy per kernel invocation, and the corresponding baseline-corrected dynamic energy per kernel invocation.

The execution-time results are analyzed separately, as presented in the Section 4.1, and are intentionally omitted from the energy-consumption tables.

4.3. The CPU Execution Time Methodology

Although the proposed MDST algorithm was primarily designed for execution on GPUs, whose massively parallel architecture is inherently well-suited for this type of computation, an additional evaluation was intentionally conducted on a multi-core CPU platform. This complementary analysis was not intended to replace the GPU-oriented implementation, but rather to provide a deeper understanding of the intrinsic computational behavior of the algorithm when deployed on a fundamentally different hardware architecture. By assessing its performance on a modern multi-core CPU, it becomes possible to better characterize the algorithm’s scalability, parallel efficiency, and architectural adaptability beyond the GPU environment for which it was originally conceived.

To enable precise and reproducible evaluation of the proposed MDST algorithm, which is designed to run in parallel on four CPU cores, a dedicated system-level configuration was implemented (Table 2). The objective was to isolate cores 28–31 of an Intel Core i9 processor and eliminate any potential interference from the operating system, background processes, or hardware-level mechanisms.

Table 2. System-level optimizations for CPU core isolation to achieve a deterministic MDST evaluation.

Optimization Action	Implementation Details	Purpose/Effect
CPU frequency locking	Set scaling_governor = performance for cores 28–31	Forces a constant frequency, eliminates dynamic underclocking
Disable energy-aware bias	Set energy_performance_preference = performance	Prevents Intel power-saving heuristics from affecting performance
Core isolation (scheduler level)	isolcpus = 28–31 in GRUB	Prevents the Linux scheduler from assigning tasks to isolated cores
Tick and kernel activity removal	nohz_full = 28–31, rcu_nocbs = 28–31	Eliminates periodic scheduler ticks and offloads RCU callbacks
Interrupt (IRQ) migration	Modified/proc/irq/*/smp_affinity via script	Moves hardware interrupts to cores 0–27
Workqueue CPU restriction	Set/sys/devices/virtual/workqueue/cpumask = 0fffffff	Prevents kernel workqueues from executing on isolated cores
Disable CPU idle states	intel_idle.max_cstate = 0, processor.max_cstate = 0	Eliminates C-states, ensuring zero-latency wake-up

First, to prevent dynamic frequency scaling effects, the CPU frequency governor for the selected cores was set to performance mode [25]. This configuration ensures that cores 28–31 run continuously at their maximum configured frequency, eliminating latency variations caused by frequency transitions.

Second, the Energy Performance Preference (EPP) was set to performance for the same cores [26], prioritizing computational performance over energy efficiency despite Intel’s energy-aware scheduling in high-performance modes.

To achieve complete isolation from the Linux scheduler, the GRUB boot configuration was updated to include the isolcpus = 28–31 parameter [27]. This prevents the scheduler from assigning user-space tasks to the designated cores. Additional parameters, namely nohz_full = 28–31 and rcu_nocbs = 28–31, were added to eliminate periodic scheduler ticks and offload Read-Copy-Update (RCU) callbacks to non-isolated cores (0–27) [27,28]. These modifications effectively remove kernel-level interruptions and background activities from the isolated cores.

Hardware interrupts (IRQs) were moved away from the isolated cores by modifying the smp_affinity configuration files for each interrupt in the/proc/irq/directory [29]. A dedicated script assigned all movable interrupts to cores 0–27. Although some critical interrupts cannot be reassigned due to kernel constraints, most were successfully relocated, significantly reducing asynchronous disturbances.

Kernel work queues were reconfigured at runtime to restrict CPU affinity to cores 0–27 [28], keeping background workers (e.g., kworker threads) off isolated cores. Though listed as processes, these workers remain idle, using no CPU or causing context switches. Low-level monitoring (e.g., mpstat), rather than process inspection alone, confirmed no measurable activity on cores 28–31 without user applications.

Finally, to eliminate latency introduced by power management, deep CPU idle states (C-states) were disabled using the GRUB parameters intel_idle.max_cstate = 0 and processor.max_cstate = 0 [27]. This forces the processor to keep all cores in an active C0 state, avoiding wake-up delays and ensuring deterministic execution.

After applying all configurations and rebooting the system, cores 28–31 operate as dedicated computational units, free from scheduler interference, kernel activity, interrupt handling, and power-management-induced variability. This controlled execution environment ensures that the performance evaluation of the MDST algorithm reflects its intrinsic computational characteristics rather than artifacts introduced by the underlying system.

5. Results

To ensure a reliable and consistent evaluation of the proposed MDST algorithm, a series of experiments was conducted on both CPU and GPU architectures under controlled execution conditions [30,31]. The testing environment was carefully configured to prevent interference from other processes, allowing the computational resources to be dedicated entirely to the implementations under analysis. Each version of the testing environment was optimized for the target platform, accounting for differences between CPU and GPU parallel processing.

The results are summarized in the following tables and presented using relevant statistical metrics, including mean execution time (Mean ± SD) and the minimum and maximum recorded values for each experimental setup corresponding to the evaluated hardware configurations. To ensure consistency and enable a fair comparison across platforms, all implementations used double-precision floating-point arithmetic.

5.1. GPU Results

A rigorous evaluation of the proposed MDST algorithm (code available at the link in the Supplementary Materials) was conducted across multiple GPU architectures under tightly controlled conditions, ensuring that no concurrent workload interfered with execution. For each platform, both the classical implementation and the parallel version (structured into four independent segments) were executed using double-precision arithmetic. The reported metrics include the mean execution time, standard deviation, and the observed minimum and maximum runtimes, providing a comprehensive characterization of performance stability and variability (Table 3 and Table 4).

Table 3. Performance outcomes of executing the two MDST algorithms (the conventional algorithm and the parallel implementation with four segments) across various GPU architectures, with each GPU operating at its minimum accepted frequency.

Processing Parameters	Jetson AGX Xavier (114 MHz)		Jetson AGX Orin (306 MHz)		GeForce RTX 4090 (210 MHz)
	Classical Implementation	Parallel Implementation	Classical Implementation	Parallel Implementation	Classical Implementation	Parallel Implementation
Mean [ms]	5.429	0.240	2.184	0.0759	3.009	0.0392
SD [ms]	0.044	0.010	0.052	0.0004	0.033	0.0002
Min. [ms]	5.410	0.227	2.130	0.0747	2.988	0.0384
Max. [ms]	5.727	0.259	2.579	0.0769	3.192	0.0397
Overall speedup:	22.58		28.75		76.85

Table 4. Performance outcomes for executing the two MDST computational algorithms (the conventional algorithm and the parallel implementation with four segments) across various GPU architectures, each operating at its maximum supported frequency.

Processing Parameters	Jetson AGX Xavier (1400 MHz)		Jetson AGX Orin (1300 MHz)		GeForce RTX 4090 (2700 MHz)
	Classical Implementation	Parallel Implementation	Classical Implementation	Parallel Implementation	Classical Implementation	Parallel Implementation
Mean [us]	510.247	67.605	542.228	59.825	244.136	20.713
SD [us]	1.547	4.067	10.499	0.178	1.813	0.041
Min. [us]	505.690	64.494	525.525	58.883	243.461	20.509
Max. [us]	513.583	91.937	593.639	59.994	254.073	20.784
Overall speedup:	7.55		9.06		11.79

Table 3 and Table 4 summarize the results under two distinct operating regimes: minimum and maximum GPU frequencies, respectively. In all cases, the classical implementation, executed on a single computational stream, served as the baseline reference, while the parallel version leveraged concurrent execution across multiple processing units. The performance gain was quantified as the ratio of the average execution time of the classical approach to that of the parallel implementation.

According to Table 3, where all GPUs operate at their lowest supported frequencies, the parallel MDST algorithm delivers substantial acceleration across all tested platforms. The speedup ranges from 22.58 on the Jetson AGX Xavier system to 76.85 on the GeForce RTX 4090. These results indicate that the benefits of parallelization are particularly pronounced under constrained frequency conditions, where efficient workload distribution and reduced computational redundancy are critical. Moreover, the relatively low standard deviations in the parallel implementation suggest a high degree of temporal stability, which is essential for reproducible performance evaluation.

In contrast, Table 4 reports results at maximum operating frequencies. Although absolute execution times decrease across all implementations, the relative speedup factors range from 7.55 to 11.79. This behavior can be attributed to the fact that, at higher frequencies, the classical implementation already benefits from increased raw computational throughput, thereby narrowing the relative advantage of parallel decomposition. Nevertheless, the parallel algorithm consistently outperforms the classical approach, maintaining a clear performance advantage across all architectures.

Those speed-up factors are achieved through a combination of factors in the proposed algorithm: minimizing the number of memory accesses, using precomputed and stored constants, minimizing the number of multiplications, and utilizing the subexpression sharing technique. To better understand the speed-up of the proposed algorithm, Table 5 presents the number of operations executed by the classical and proposed MDST algorithms.

Table 5. The number of operations executed by the classical and proposed MDST algorithms.

Algorithm	Multiplications	Additions/Subtractions	Parallel Sections
Classical MDST	1734	2312	1
Proposed MDST	90 (34 serial and 56 in parallel—14 × 4)	427	4

The operation counts in Table 5 represent algorithm-level arithmetic complexity before compiler optimization; consequently, they are independent of compiler-generated instruction fusion, such as FMA. The measured execution-time improvements also reflect differences in memory-access behavior and parallel execution, as analyzed in Table 6.

Table 6. Number of requests from global, local, and shared memory generated by the classical and proposed algorithms.

Memory Type and Access Type	Memory Access [Number of Requests]
	Classical Implementation	4 Sections in Parallel
Global	5220	152
Local	578	0
Shared	0	181

As illustrated in Table 3 and Table 4, the speed improvement exceeds 4 (the level of parallelism) due to fewer operations, especially multiplications, as shown in Table 5. These advantages can be extended to larger values of M, for example, M = 137 or M = 2017.

Modern GPU architectures include several types of memory, each designed to optimize performance and the efficiency of parallel execution. Global memory is the largest memory space on the GPU and can be accessed by all GPU threads and the host CPU. Although it provides high storage capacity, it also has the highest access latency. Shared memory is located directly on each Streaming Multiprocessor (SM) and offers significantly faster access speeds, but it can be accessed only by threads within the same thread block. Local memory is an extension of the register space and is used when the number of variables exceeds the available register capacity. Although it appears private to each thread, it is physically stored in global memory and therefore has similar latency characteristics.

Table 6 presents the number of accesses to local, global, and shared memory for each evaluated algorithm. These measurements were obtained using the NVIDIA Nsight Compute profiling tool.

It should be noted that the present CUDA implementation was designed primarily to evaluate the impact of the proposed algorithmic restructuring rather than to exhaustively optimize the GPU memory hierarchy. The principal input, output, and intermediate arrays are therefore predominantly maintained in global memory, while shared memory is selectively employed where data reuse within the parallel sections is advantageous. Nevertheless, the memory-access profile in Table 6 shows that the proposed formulation strongly reduces global-memory traffic, from 5220 requests in the classical implementation to only 152 requests, while introducing 181 shared-memory accesses and eliminating the observed local-memory traffic.

Register accesses are not explicitly quantified in Table 6 because scalar variables may be automatically allocated to registers by the CUDA compiler. Conversely, local memory is generally used when thread-private data cannot be maintained in registers. Therefore, the absence of local-memory requests in the proposed implementation indicates that no measurable local-memory traffic was generated during the profiled execution, but it should not be interpreted as a direct measurement of register usage.

More aggressive memory-hierarchy optimization, for example by retaining additional intermediate values in registers or shared memory and by exploiting constant memory for read-only coefficients, could potentially further improve execution time and energy efficiency. Thus, the reported results characterize the proposed algorithm under the investigated memory-mapping strategy and should not be considered the absolute hardware-specific optimum. At the same time, the substantial reduction in global-memory traffic demonstrates that the proposed mathematical restructuring itself improves not only arithmetic complexity but also the effective memory-access behavior.

A notable trend across both Table 3 and Table 4 is the proposed algorithm’s superior scalability on more advanced GPU architectures. In particular, the GeForce RTX 4090 consistently delivers the highest acceleration factors, especially in the low-frequency regime. The RTX 4090’s superior acceleration stems from several architectural features that directly favor the execution pattern of the proposed parallel MDST algorithm. The RTX 4090 benefits from a substantially more advanced warp scheduling mechanism. Modern NVIDIA schedulers can issue instructions from multiple warps simultaneously while aggressively hiding arithmetic and memory-access latencies. The proposed MDST algorithm contains numerous short arithmetic sequences with strong data locality. Such workloads are particularly well-suited to Ada Lovelace warp schedulers, which can rapidly alternate among ready warps while maintaining high execution efficiency, even for fine-grained computational kernels. Consequently, pipeline stalls are minimized, and the arithmetic units remain active for a larger fraction of the execution time.

Another important factor is the RTX 4090’s significantly improved memory hierarchy. The architecture incorporates: (a) larger L2 cache capacity, (b) higher cache bandwidth, (c) lower effective memory-access latency, and (d) substantially higher global memory throughput. The proposed MDST implementation repeatedly accesses compact intermediate vectors and shared computational data structures. In general, the proposed MDST algorithm performs significantly fewer memory accesses, as illustrated in Table 6. This reduction is one of the primary factors contributing to the increased execution speed compared to the classical algorithm. Moreover, on the RTX 4090, a larger proportion of these accesses can be satisfied directly through the cache, thereby reducing expensive global memory transactions. Furthermore, the Ada Lovelace architecture provides extremely high memory bandwidth through its GDDR6X subsystem (Table 1), approaching 1 TB/s. Although the proposed MDST algorithm is primarily arithmetic-oriented, memory movement still contributes to the overall execution cost, especially during host-to-device and device-to-host transfers and during intermediate vector manipulations. The high-bandwidth memory subsystem reduces these transfer bottlenecks and contributes to the lower overall runtime observed experimentally.

Consequently, the proposed approach not only benefits from parallel execution but also aligns with the architectural evolution of contemporary GPUs.

Overall, the results demonstrate that the proposed MDST implementation delivers significant performance gains over the classical method, with gains that depend on both hardware characteristics and operating frequency. The combination of parallel decomposition, reduced computational complexity, and efficient resource utilization underpins these gains, confirming the algorithm’s suitability for high-performance computing environments.

To assess the sensitivity of execution-time measurements to the numerical values of the input samples and to improve experimental reproducibility, an additional analysis was conducted using deterministic input sequences. Three pseudo-random input sequences were generated with fixed seeds (12,345, 23,451, and 34,512), along with five deterministic patterns: an all-zero sequence, a constant sequence (x[n] = 5.0), a ramp (x[n] = n/33), an alternating sequence (x[n] = 0, 1, 0, 1, …), and an impulse sequence defined by (x [0] = 1 and x[n > 0] = 0). The same input sequence was supplied to both the classical and proposed MDST implementations for each test. The timing methodology and execution conditions were kept identical to those used in the main benchmark. The sequence generated with the fixed seed 12,345 was selected as the reference, and the relative timing variation was calculated as:

$$\Delta T_i={\displaystyle \frac{T_i-T_{\mathit{ref}}}{T_{\mathit{ref}}}}·100\%$$

(56)

Table 7 summarizes the resulting mean execution times and their relative deviations from the reference input.

Table 7. Sensitivity of MDST execution time to different input data patterns and fixed pseudo-random seeds.

Input Pattern Type	Implementation	Classical Alg. Mean [us]	ΔTclassical [%]	Proposed Alg. [us]	ΔTproposed [%]
Fixed random	rand (), seed = 12,345	523.395	0	59.307	0
	rand (), seed = 23,451	524.608	+0.232	60.049	+1.251
	rand (), seed = 34,512	527.361	+0.758	59.683	+0.634
Zero	x[n] = 0	524.709	+0.251	59.957	+1.096
Constant	x[n] = 5.0	522.872	−0.100	59.607	+0.506
Ramp	x[n] = n/33	526.731	+0.637	59.617	+0.523
Alternating	x[n] = 0, 1, 0, 1,…	524.101	+0.135	59.993	+1.157
Impulse	x[0] = 1, x[n > 0] = 0	526.349	+0.564	60.106	+1.347

The results show only a small sensitivity of execution time to the numerical input pattern. For the classical implementation, the relative deviation from the reference sequence ranges from −0.100% to +0.758%, whereas for the proposed implementation it ranges from 0% to +1.347%. The largest deviation for the proposed algorithm was observed with the impulse input, while the largest deviation for the classical implementation occurred with the pseudo-random sequence generated with seed 34,512. Moreover, changing the pseudo-random seed produced variations below 0.76% for the classical implementation and below 1.26% for the proposed implementation. These results indicate that the measured execution times are only weakly sensitive to the numerical values and structure of the input data. Thus, although cache state, memory-system activity, and other low-level execution effects may introduce small timing variations, the performance advantage reported for the proposed MDST implementation is not dependent on a particular pseudo-random input realization.

5.2. GPU Energy-Consumption Results

The compute-only energy characteristics of the two CUDA implementations are summarized in Table 8, while the relative energy savings achieved by the novel four-section implementation are reported in Table 9. The measurements were obtained from 2,000,000 repeated kernel invocations per configuration, ensuring sufficiently long acquisition intervals for the onboard power-monitoring circuitry. Consistent with the measurement boundary defined in the Section 4, the reported values characterize only the GPU computation phase.

Table 8. Compute-only GPU power and energy characteristics of the two CUDA implementations on the Jetson AGX Xavier.

GPU Frequency	CUDA Implementation	Idle GPU Power, Pidle [W]	Average Compute Power, Pavg [W]	Compute-Only GPU-Rail Energy per Kernel, Ecompute/kernel [μJ]	Baseline-Corrected GPU Energy per Kernel, Edynamic/kernel [μJ]
114 MHz	Classical MDST	0.317	0.482	2574.27	884.05
	Proposed MDST	0.290	0.481	21.625	8.618
1.4 GHz	Classical MDST	1.343	3.836	1706.14	1108.86
	Proposed MDST	0.991	3.631	17.338	12.606

Table 9. Relative compute-only GPU energy improvement of the four-section CUDA implementation with respect to the single-section implementation.

GPU Frequency	GPU Energy Reduction, RE [%]	Baseline-Corrected Energy Reduction, RE,dyn [%]	Energy Reduction Factor, FE
114 MHz	99.16	99.03	119.04
1.4 GHz	98.98	98.86	98.40

The results demonstrate a substantial reduction in compute-only GPU energy consumption for the four-section implementation at both investigated GPU frequencies. At 114 MHz, the GPU-rail energy per kernel invocation decreases from 2574.27 µJ for the single-section implementation to 21.63 µJ for the four-section implementation, corresponding to a 99.16% energy reduction and an energy-efficiency factor of approximately 119×. Notably, the average GPU power remains nearly unchanged between the two implementations (0.4823 W versus 0.4813 W), indicating that the primary improvement is in the energy required per kernel invocation rather than in the average power level.

A similar improvement is observed at 1.4 GHz, where compute-only GPU energy decreases from 1706.14 µJ to 17.34 µJ per kernel invocation. This corresponds to a 98.98% reduction and an energy-efficiency factor of approximately 98.4×. At this frequency, the four-section implementation also shows lower average GPU power, dropping from 3.8361 W to 3.6310 W. The baseline-corrected results confirm the same overall trend, with dynamic-energy reductions of 99.03% at 114 MHz and 98.86% at 1.4 GHz. Overall, the measurements consistently show that the four-section CUDA implementation consumes approximately two orders of magnitude less compute-only GPU energy than the single-section implementation, and that this advantage is preserved across the investigated GPU operating frequencies.

Therefore, the reported compute-only energy values inherently include the energy associated with device-memory accesses occurring during kernel execution; consequently, alternative mappings of intermediate data to registers, shared memory, or constant memory could modify the absolute energy values, although such memory-specific optimization was outside the scope of the present algorithm-oriented comparison.

It is important to emphasize that the power-monitoring procedure does not attempt to resolve the energy consumption of an individual kernel invocation in the time domain. The duration of a single CUDA kernel is considerably shorter than the approximately 5 ms monitoring interval. Instead, the kernel was executed 2,000,000 times consecutively to generate a long, approximately stationary computational workload. The total GPU-rail energy was integrated over this complete interval and subsequently divided by the number of kernel invocations. Consequently, E_{compute/kernel} represents an ensemble-averaged energy per kernel invocation rather than a direct temporally resolved measurement of a single kernel.

Because the duration of an individual CUDA kernel invocation is considerably shorter than the nominal power-sampling interval, an additional validation experiment was performed to evaluate whether the selected monitoring granularity affects the estimated energy per kernel. The complete energy-measurement procedure was independently repeated using nominal sampling intervals of approximately 5, 10, 20, and 50 ms. For all validation experiments, the same CUDA implementations, workload definition, number of kernel invocations, energy-integration procedure, and controlled GPU operating conditions were maintained. The GPU operating frequency was explicitly locked during the measurements in order to suppress workload-dependent frequency scaling and frequency-transition effects.

For each experiment, the instantaneous GPU-rail power was calculated from the measured voltage and current samples, while the total GPU energy was obtained by timestamp-based trapezoidal integration. The resulting energy was subsequently normalized by the number of kernel invocations, as defined by Equation (48).

Table 10 summarizes the resulting energy-per-kernel values obtained for the different nominal monitoring intervals.

Table 10. Sensitivity of the estimated GPU energy per kernel to the nominal power-sampling interval—the GPU operating frequency was locked at 1.4 GHz.

Implementation	5 ms	10 ms	Deviation	20 ms	Deviation	50 ms	Deviation
Classical MDST [µJ]	1669.60	1669.14	−0.028%	1669.05	−0.033%	1669.33	−0.016%
Proposed MDST [µJ]	17.365	17.423	+0.334%	17.391	+0.150%	17.478	+0.651%

The validation results show that the estimated energy per kernel is highly stable over the selected monitoring interval. For the classical MDST implementation, the maximum absolute deviation relative to the 5 ms reference measurement is only 0.033%. For the proposed MDST implementation, the maximum deviation is 0.651%, observed for the 50 ms sampling interval. Consequently, even when the nominal sampling interval is increased by a factor of ten, the resulting energy estimate remains within 1% of the 5 ms reference value for both CUDA implementations.

These results indicate that the reported energy metric is not critically dependent on the approximately 5 ms sampling granularity. This robustness results from the measurement strategy in which a large number of identical kernel invocations are executed consecutively, and the GPU-rail energy is integrated over the complete workload interval before normalization. Thus, the power monitor is not required to temporally resolve every individual kernel invocation in order to obtain a stable estimate of the mean energy per invocation.

Nevertheless, the finite temporal response of the INA3221 remains an intrinsic limitation of the measurement approach. Sub-millisecond power fluctuations associated with individual CUDA kernel executions cannot be reconstructed from the acquired samples, and short-duration transients may be attenuated or aliased by the monitoring circuitry. Therefore, the validation demonstrates the robustness of the integrated average energy estimate, but it should not be interpreted as evidence that the instantaneous power waveform of an individual kernel is temporally resolved.

From a system-design perspective, these results provide information that cannot be obtained from execution-time measurements alone. First, they demonstrate that the substantial acceleration achieved by the proposed decomposition is not obtained at the expense of increased GPU energy consumption. On the contrary, the reduction in arithmetic complexity, execution time, and memory activity results in a substantial reduction in the compute-only energy required per transform. This is particularly relevant when the MDST is repeatedly executed in battery-powered, thermally constrained, or continuously operating embedded systems.

Second, the measurements illustrate the trade-off associated with the GPU operating point. For the proposed implementation, increasing the GPU frequency from 114 MHz to 1.4 GHz reduces the total compute-only GPU-rail energy per kernel from 21.625 to 17.338 µJ, while the baseline-corrected dynamic energy increases from 8.618 to 12.606 µJ/kernel. Thus, the most appropriate operating point depends on the system-level optimization objective. A latency-constrained application may benefit from operation at the higher frequency, which also reduces the total rail energy associated with the shorter execution interval, whereas a design primarily concerned with the incremental energy attributable to active computation may favor a different operating point. These results demonstrate why both execution time and energy should be considered when selecting the operating conditions of the algorithm.

The present energy measurements should not, however, be interpreted as identifying the most energy-efficient processor among the Jetson AGX Xavier, Jetson AGX Orin, GeForce RTX 4090, and Intel Core i9 platforms. Energy was measured only on the Jetson AGX Xavier and only for the GPU-computation phase. A rigorous platform-selection study would require equivalent compute-only or end-to-end energy measurements on all candidate architectures. The cross-platform experiments presented in this work therefore establish performance portability and execution-time scalability, whereas the Xavier measurements provide a controlled assessment of the energy consequences of the proposed algorithmic restructuring.

5.3. GPU Parallelism Scalability Through Batched MDST Processing

The performance analysis presented in the previous sections considers the parallel decomposition of a single MDST into four independent computational sections. For an individual transform with N = 34, however, the amount of intrinsic parallelism is necessarily limited. In particular, the initial CUDA mapping described in Section 4.1, in which the four computational sections were executed concurrently, was intentionally designed to expose the parallelism introduced by the mathematical reformulation rather than to saturate the execution resources of a massively parallel GPU. A single transform therefore represents a latency-oriented execution scenario and provides too little independent work to achieve high Streaming Multiprocessor (SM) utilization on a modern GPU.

To investigate whether the proposed four-section decomposition can also benefit from the massive parallelism available on GPU architectures, an additional experiment was conducted by processing multiple MDSTs concurrently. This experiment introduces a second level of parallelism (code available at the link in the Supplementary Materials). The decomposition proposed in this paper provides intra-transform parallelism, since each MDST is divided into four independent computational sections, whereas the simultaneous processing of multiple input windows provides inter-transform parallelism. The combination of these two levels allows the amount of available GPU work to increase substantially without modifying the mathematical formulation of the proposed MDST algorithm.

A practical example of such a workload is the processing of a long time series. Let x[n] denote the input signal. For the transform length used throughout this paper, N = 34, consecutive analysis windows can be extracted with a 50% overlap, corresponding to a hop size of:

$$H=N/2=17.$$

(57)

The b-th analysis window is therefore defined as:

$$x^b\left[n\right]=x\left[n+b·H\right],n=0,\dots ,33,$$

(58)

where b = 0,…, B − 1, and B denotes the number of transforms available for concurrent processing. A set of B overlapping windows requires an input sequence of:

$$L=34+17·(B-1)$$

(59)

samples. Although neighboring windows share 17 input samples, their forward MDST computations do not depend on each other’s outputs. Once the corresponding samples are available, the B transforms can therefore be evaluated concurrently.

It is important to distinguish this throughput-oriented scenario from a strictly latency-constrained single-stream application. Accumulating many windows from a single real-time stream would introduce buffering latency. Consequently, B should be interpreted more generally as the amount of independent transform work simultaneously available to the processor. Such parallelism can originate from buffered segments of a long signal, multiple independent channels, multiple concurrent data streams, or offline/batched signal-processing workloads. For a single isolated transform with stringent latency requirements, a few-core CPU or a dedicated streaming architecture may represent a more natural implementation target. The purpose of the present experiment is therefore to determine how the proposed algorithm behaves when sufficient inter-transform parallelism is available for exploitation on a GPU architecture.

For this additional experiment, a conventional CUDA execution configuration was developed instead of extending the original single-transform configuration by simply launching additional one-thread blocks. Each CUDA block contains 128 threads, corresponding to four complete warps. The four warps are associated with the four independent computational sections of the proposed MDST decomposition:

• warp 0 executes Section 1 for up to 32 independent transforms;
• warp 1 executes Section 2 for the same set of transforms;
• warp 2 executes Section 3;
• warp 3 executes Section 4.

Within each warp, the lane index identifies the transform being processed. Consequently, one 128-thread block processes up to 32 independent MDST instances, and the number of CUDA blocks required for a batch of B transforms is

$$N_{\mathit{blocks}}=\lceil {\displaystyle \frac{B}{32}}\rceil$$

(60)

This mapping has two advantages. First, all threads belonging to the same warp execute the same computational section, avoiding branch divergence between the four MDST sections. Second, adjacent lanes operate on different transforms but on equivalent coefficients. The input and intermediate arrays were therefore stored using a coefficient-major, transform-minor organization, allowing adjacent lanes to access contiguous memory locations and promoting coalesced global-memory transactions.

The kernel was compiled for the Ampere architecture of the Jetson AGX Orin. The compiler reported using 40 registers per thread, with no register spilling and no static shared-memory allocation. The CUDA occupancy API indicated that the kernel resource requirements permit up to 12 resident 128-thread blocks per SM. This value represents the theoretical resource limit for an individual SM and must not be confused with the occupancy actually obtained by a finite grid. For this reason, the experimental analysis below uses the achieved occupancy measured directly by NVIDIA Nsight Compute, rather than relying only on theoretical occupancy estimates. The scalability experiment was performed for B equal to 1, 32, 128, 256, 512, 1024, 2048, 3072, 4096, 6144, 8192, 12,288, and 16,384.

All measurements in this section were obtained with the GPU of the Jetson AGX Orin locked at its maximum frequency of 1.3 GHz, i.e., the same operating point as in Table 4, and all computations were performed in double precision (FP64), as in the rest of this study.

For each value of B, the kernel execution time was measured using CUDA events. Twenty preliminary kernel launches were used as warm-up operations, followed by 1000 timed launches. The mean kernel execution time per batch was divided by B to obtain the average kernel execution time per transform,

$$T_{\mathit{MDST}}={\displaystyle \frac{T_{\mathit{batch}}}{B}}$$

(61)

while the processing throughput was calculated as

$$R_{\mathit{MDST}}={\displaystyle \frac{B}{T_{\mathit{batch}}}}$$

(62)

Because the objective of this experiment is specifically to characterize GPU parallelism and SM utilization, the performance values in Table 11 refer to the CUDA-kernel execution interval. Host-to-device transfers, device-to-host transfers, and host-side final reconstruction were measured separately and were not included in the GPU-utilization metrics.

Table 11. Scalability and GPU-utilization characteristics of the batched four-section MDST implementation on the Jetson AGX Orin.

B	CUDA Blocks	Kernel Time/Transform [µs]	Throughput [106 Transforms/s]	Achieved Occupancy [%]	SM Active [%]	SM Throughput [%]
1	1	8.567	0.117	10.07	5.23	3.10
32	1	0.323	3.093	10.05	5.37	3.11
128	4	0.0812	12.309	9.76	20.53	11.67
256	8	0.0428	23.390	9.84	40.67	23.14
512	16	0.0191	52.355	10.02	81.55	45.85
1024	32	0.0200	49.997	17.26	86.18	59.02
2048	64	0.0152	65.600	27.66	91.89	68.62
3072	96	0.0139	72.085	37.12	93.97	72.64
4096	128	0.0145	68.800	45.61	95.35	75.07
6144	192	0.0133	75.064	63.78	97.23	78.27
8192	256	0.0128	78.439	71.13	97.30	79.19
12,288	384	0.0122	82.167	80.49	98.34	80.84
16,384	512	0.0122	82.033	84.89	98.74	81.60

Hardware utilization was profiled independently for each value of B using NVIDIA Nsight Compute. Three complementary metrics were retained: achieved occupancy, which characterizes the average number of active warps relative to the architectural limit; SM active percentage, which characterizes the fraction of the execution interval during which the SMs perform active work; and SM throughput, which indicates the achieved SM processing rate relative to the sustained architectural capability.

The results clearly reveal two distinct execution regimes. For a single transform, B = 1, the GPU is strongly underutilized. Only one CUDA block is launched, and the achieved occupancy is 10.07%, the SM-active metric is only 5.23%, and the measured SM throughput is 3.10%. The corresponding kernel execution time is 8.57 µs per transform. These measurements confirm that the amount of parallel work exposed by one N = 34 transform is insufficient to efficiently utilize the massively parallel resources of the Jetson AGX Orin.

Comparing B = 1 and B = 32 is instructive: both use one 128-thread CUDA block and achieve nearly identical occupancy and SM-active values. Yet at B = 1, only one lane per warp computes; at B = 32, all 32 lanes transform independently. Throughput therefore rises from about 0.117 × 10⁶ to 3.09 × 10⁶ transforms/s—a 26.5-fold increase—with no additional resident warps. This highlights the value of exposing inter-transform parallelism within each MDST, as well as its four-way decomposition.

As B increases further, the grid contains enough blocks to distribute work across an increasing number of SMs. For B = 128, four blocks are available, and the SM-active percentage increases to 20.53%. At B = 256, eight blocks increase SM activity to 40.67%, while B = 512 produces 16 blocks, corresponding to one block for each of the 16 SMs of the evaluated Jetson AGX Orin. At this point, the SM-active value reaches 81.55%, and the throughput increases to approximately 52.36 × 10⁶ transforms/s.

Increasing B beyond 512 enables multiple blocks per SM, raising active SMs and resident warps. Occupancy rises from 17.26% at B = 1024 to 45.61% at 4096, 63.78% at 6144, and 80.49% at 12,288. Across this range, SM activity approaches its practical maximum (86.18% to 98.34%), and throughput grows from 59.02% to 80.84%. Application throughput peaks at B = 12,288, reaching approximately 82.17 × 10⁶ transforms/s.

Increasing batch size to B = 16,384 raises occupancy from 80.49% to 84.89% and SM throughput from 80.84% to 81.60%. Yet transform throughput falls slightly, from 82.17 to 82.03 million transforms/s, while execution time remains about 0.0122 µs per transform. Thus, this implementation reaches practical throughput saturation around B = 12,288–16,384; larger batches add queued work without meaningfully improving application throughput.

Minor non-monotonic variations are visible at some intermediate batch sizes, for example between B = 3072 and B = 4096. Nevertheless, the overall trend is unambiguous: increasing the amount of independent work progressively increases SM activity, achieved occupancy, and throughput until the GPU approaches saturation.

Relative to the single-transform case, the maximum measured throughput increases from 0.117 × 10⁶ to approximately 82.17 × 10⁶ transforms/s, corresponding to a 704-fold increase. This factor should not be interpreted as an algorithmic speedup relative to the classical MDST implementation. Instead, it quantifies the improvement in GPU throughput efficiency obtained by increasing the amount of concurrently available independent work.

The experiment clarifies when the proposed MDST decomposition is well-suited to GPUs. A single N = 34 transform has only four coarse, independent sections, offering too little parallelism to efficiently use a modern GPU. For this latency-oriented workload, a few-core CPU or dedicated streaming hardware may be a better fit. With multiple simultaneous transforms, however, intra-transform decomposition combines with inter-transform parallelism. This throughput-oriented approach scales to hundreds of CUDA blocks, reaches approximately 99% SM activity and over 80% measured SM throughput, and processes about 82 million MDSTs per second on the Jetson AGX Orin.

These results demonstrate that the suitability of the proposed algorithm for GPU execution depends on the structure of the application workload rather than on the four-way decomposition alone. The original four-section formulation provides the basic intra-transform concurrency, whereas batched, multichannel, or windowed signal processing supplies the inter-transform concurrency required to exploit a massively parallel GPU architecture. Accordingly, the proposed MDST implementation supports two complementary deployment regimes: low-latency processing on a small number of execution resources when only one or a few transforms are available, and high-throughput GPU processing when a sufficiently large number of independent transforms can be executed concurrently.

5.4. CPU Results

In the era of hybrid architectures such as the Intel Core i9-14900K, performance can no longer be treated as an intrinsic, fixed hardware metric. Instead, it arises from the complex interaction between software and hardware, mediated by the compiler [32,33]. To assess MDST efficiency, the algorithm was tested on a CPU architecture with four compiler-critical optimizations.

First, the test was conducted without any code optimization (−O0 compiler flag). This establishes a baseline for the algorithm’s raw performance. Running the code in its most literal form establishes a “worst-case scenario” performance floor, ensuring the fundamental logic is sound before the compiler masks inefficiencies in the implemented code with automated optimizations.

Secondly, -march=native optimizes hardware utilization by directing the compiler to use the host-specific CPU’s instruction set. On a high-performance processor, this process clarifies whether the code can exploit advanced features such as AVX2 or specialized cache architectures, and assesses the MDST’s adaptability to the efficient-core topology.

Third, enabling O3 optimizations pushes the limits of code throughput by allowing the compiler to perform aggressive transformations, such as loop unrolling and function inlining [34]. This test stage is crucial for determining how much “hidden” performance can be extracted through purely mathematical and logical reorganization, regardless of the specific hardware generation.

Fourth, combining -O3 with -march=native pairs aggressive logic optimization with specialized hardware instructions. Testing is the only way to assess the processor’s true potential, revealing how the system’s Thread Director handles high-density, vectorized code and whether the software can achieve the hybrid architecture’s theoretical peak performance [35].

The results of all these analyses are presented in Table 12. All system-level optimizations listed in Table 2 were applied to CPU cores 28, 29, 30, and 31 to isolate these cores and free them from all system and user threads, yielding performance results attributable solely to the MDST algorithm. The classical MDST implementation was executed on core 28, and the parallel implementation on cores 28, 29, 30, and 31.

Table 12. MDST performance, executed in parallel on four CPU cores running at 800 MHz.

Optimization	Processing Parameters	CPU I9-14900K
		Classical Implementation	Parallel Implementation
−No (−O0)	Mean [us]	49.277	6.212
	SD [us]	5.438	0.533
	Min. [us]	20.416	6.108
	Max. [us]	51.725	11.510
	Overall speedup	7.93
−march=native	Mean [us]	75.164	6.198
	SD [us]	7.966	0.467
	Min. [us]	46.205	6.087
	Max. [us]	78.509	10.842
	Overall Speedup	12.13
−O3	Mean [us]	41.677	6.131
	SD [us]	0.6284	0.556
	Min. [us]	14.324	5.922
	Max. [us]	47.373	11.627
	Overall Speedup	6.80
−O3 -march=native	Mean [us]	41.291	6.154
	SD [us]	6.230	0.761
	Min. [us]	13.630	5.957
	Max. [us]	45.997	13,573
	Overall speedup	6.71

The performance results in Table 12 provide insight into the behavior of the novel MDST algorithm when executed on four isolated CPU cores of an Intel i9-14900K operating at a fixed frequency of 800 MHz. The comparison between the classical implementation and the parallel version highlights both the impact of compiler optimizations and the inherent advantages of parallel execution.

Across all tested configurations, the parallel implementation consistently outperforms the classical implementation, achieving speedups ranging from 6.71 to 12.13. Even without compiler optimizations (−O0), the parallel algorithm still delivers a substantial 7.93 speedup, demonstrating that its performance gains are driven primarily by algorithmic parallelism rather than compiler-assisted optimizations. This confirms that the proposed decomposition into four concurrent segments is effective even with non-optimized compilation.

A particularly interesting observation concerns the effect of the -march=native flag when used in isolation. While this option is typically expected to improve performance by enabling architecture-specific optimizations, the results show an increase in the execution time of the classical implementation (from 0.049277 ms to 0.075164 ms). In contrast, the parallel implementation remains largely unaffected, maintaining a nearly constant execution time (~0.0062 ms). As a result, the computed speedup reaches a maximum of 12.13 in this configuration. This behavior suggests that at such low frequencies, the overhead of initializing and managing complex, architecture-specific instructions outweighs the benefits of executing them, effectively penalizing code that attempts to use advanced hardware features without logical optimization.

When higher optimization levels are enabled (−O3 and −O3 combined with −march=native), the execution time of the classical algorithm decreases to approximately 0.041 ms. However, the performance of the parallel implementation remains nearly constant across all configurations, fluctuating only slightly between 0.0061 and 0.0062 ms. As a result, the relative speedup decreases to approximately 6.7–6.8. This reduction does not indicate degradation of the parallel algorithm but rather an improvement in the efficiency of the classical implementation due to aggressive compiler optimizations such as loop unrolling, vectorization, and instruction scheduling [34].

Another important aspect is the stability of execution times. The standard deviation for the parallel implementation is consistently very low (on the order of 10⁻⁴–10⁻³ ms), indicating highly deterministic behavior. In contrast, the classical implementation shows higher variability. This difference suggests that parallel execution benefits not only from reduced execution time but also from improved temporal predictability, which is essential in performance-critical applications.

To evaluate whether the CPU performance observed under the isolated and deterministic configuration translates to a more conventional multi-core Linux environment, an additional experiment was performed using a standard Linux configuration. In this experiment, the CPU frequency was maintained at 800 MHz and the computational threads were pinned to the same CPU cores (28, 29, 30, and 31) used in the isolated configuration, so that processor frequency and core placement did not introduce additional confounding factors. The classical and proposed implementations were both compiled using -O3 -march=native.

For the standard Linux configuration, the system-level isolation mechanisms used in the deterministic benchmark were removed: isolcpus, nohz_full, and rcu_nocbs were disabled; IRQ affinity and kernel workqueues were left under their default Linux management; CPU C-states were enabled; and the normal operating-system processes and background services remained active. Thread affinity was nevertheless retained to ensure that the same physical CPU cores executed the corresponding computational sections in both configurations. By keeping the CPU frequency fixed at 800 MHz and using the same CPU cores in both configurations, differences in execution time can be attributed primarily to operating-system activity, interrupts, kernel workqueues, background processes, and CPU idle-state transitions rather than to changes in processor frequency or core placement.

In addition to the mean execution time and standard deviation, the coefficient of variation (CV) was used to quantify the relative timing variability:

$$\mathit{CV}={\displaystyle \frac{\mathit{SD}}{\overline{T}} \times 100\%}$$

(63)

where $\overline{T}$ is the mean execution time and SD is its standard deviation. The CV provides a normalized measure of timing variability, allowing the execution-time stability of the two CPU environments to be compared independently of their different mean execution times. Lower CV values indicate more deterministic execution; see Table 13.

Table 13. CPU execution-time performance and variability under isolated/deterministic and standard Linux configurations.

CPU Environment	Mean of the Classical Alg. [µs]	SD [µs]	CV	Mean of the Proposed Alg. [µs]	SD [µs]	CV	Speedup
Isolated/ deterministic	41.291	6.230	15.08%	6.154	0.761	12.36%	6.71
Standard Linux	42.022	9.099	21.65%	6.386	1.302	20.39%	6.58

Table 13 compares CPU performance in isolated/deterministic and standard Linux environments. Removing operating system isolation modestly increases mean execution time: from 41.291 µs to 42.022 µs (1.77%) for classical MDST, and from 6.154 µs to 6.386 µs (3.77%) for the proposed implementation.

Standard Linux primarily increases execution-time variability, not mean time. The classical implementation’s CV rises from 15.08% in isolation to 21.65%; the proposed implementation’s rises from 12.36% to 20.39%. This reflects OS scheduling, interrupts, kernel workqueues, background services, CPU idle states, and other asynchronous activity suppressed in the deterministic configuration.

The proposed algorithm’s performance advantage is largely preserved: the speedup decreases only from 6.71 in isolation to 6.58 under standard Linux (about 1.94%). Thus, the MDST decomposition’s substantial acceleration is not due to core isolation, which primarily improves measurement stability and reproducibility by reducing operating-system-related timing variability.

These results indicate that the proposed implementation retains its computational advantage in a conventional multi-core Linux environment. The isolated configuration should therefore be viewed as a controlled benchmarking environment for characterizing the algorithm’s intrinsic execution behavior, rather than as a prerequisite for practical deployment. On typical Linux workstations or compute nodes, somewhat higher execution-time variability can be expected, but the relative performance benefit of the proposed parallel decomposition remains essentially unchanged.

Overall, the results demonstrate that the proposed parallel MDST algorithm delivers significant and consistent performance improvements on CPU architectures, regardless of compiler optimization levels. While compiler optimizations can reduce the gap by improving the classical implementation, they do not substantially affect the parallel version, which already operates near its optimal performance due to efficient workload distribution across the four cores and an efficient algorithm implementation.

6. Discussion

In [5], two novel systolic-array-based algorithms and VLSI architectures were proposed for the efficient implementation of the 1-D Modified Discrete Sine Transform (MDST). The primary objective of the research was to reduce hardware complexity and increase execution speed through a highly regular, modular hardware organization. The authors start from the classical formulation of the MDST and reformulate the transform into forms that can be efficiently mapped into a VLSI architecture. To achieve this, several auxiliary input sequences are introduced, as in the approach presented in this paper. These transformations allow the original MDST computation to be reformulated as matrix-vector products with highly regular, repetitive structures, which are particularly well-suited to parallel hardware implementation [5]. The second proposed algorithm in [5] reformulates the problem in a way that allows the replacement of general-purpose multipliers with constant multipliers. The same approach was also used in this research.

Due to the major similarity between the two approaches (the one presented in [5] and the proposed algorithm in this paper), which is given by the use of auxiliary input sequences and intermediate reformulations of the original MDST expression, the transformation of regular computational patterns into reduced arithmetic redundancy, and the exploitation of symmetry properties of the MDST to reduce the number of operations and improve execution efficiency, the following state-of-the-art algorithm [5] was selected to be evaluated against the algorithm presented in this paper.

As a direct result, the algorithm from [5] was implemented and evaluated under the same conditions as those used to test the algorithm described in this paper. This algorithm decomposes the MDST into two sections that operate concurrently. Another distinction is the number of processed samples. More specifically, the implementation described in [5] uses 26 samples, whereas the algorithm proposed in this paper operates on 34 samples.

The results are presented in Table 14 and Table 15. The results in Table 14 were obtained using the Jetson AGX Xavier development board. In Table 15, the results are based on the Jetson AGX Orin development board.

Table 14. Performance analysis of a state-of-the-art MDST algorithm versus the proposed MDST algorithm (done on the Jetson AGX Xavier development board).

Frequency [MHz]	Algorithm	Mean Execution Time [ms]		Speedup Factor
		Classical Implementation	Parallel Implementation
114	Algorithm presented in [5]	5.429319	0.309560	17.54
	Proposed Algorithm	5.429319	0.240464	22.58
1400	Algorithm presented in [5]	0.510247	0.074177	6.88
	Proposed algorithm	0.510247	0.067605	7.55

Table 15. Performance analysis of a state-of-the-art MDST algorithm versus the proposed MDST algorithm (done on the Jetson AGX Orin development board).

Frequency [MHz]	Algorithm	Mean Execution Time [ms]		Speedup Factor
		Classical Implementation	Parallel Implementation
306	Algorithm presented in [5]	2.183558	0.080197	27.23
	Proposed Algorithm	2.183558	0.075940	28.75
1300	Algorithm presented in [5]	0.542228	0.062553	8.67
	Proposed algorithm	0.542228	0.059825	9.06

The comparative evaluation against the state-of-the-art MDST implementation proposed in [5] demonstrates that the algorithm introduced in this paper consistently achieves superior execution performance across all tested GPU platforms and operating frequencies. Although both approaches rely on auxiliary input-sequence reformulation and exploit the symmetry properties of the MDST to reduce arithmetic complexity, the proposed implementation introduces a more efficient computational decomposition by dividing the transform into four independent parallel sections rather than two. This finer-grained parallelism improves workload distribution across CUDA cores and Streaming Multiprocessors, thereby increasing the achievable degree of concurrency and reducing overall execution latency.

The results presented in Table 11 and Table 12 show that the proposed algorithm consistently achieves higher acceleration factors than the implementation from [5]. On the Jetson AGX Xavier platform, the proposed method improves the speedup from 17.54 to 22.58 at minimum frequency and from 6.88 to 7.55 at maximum frequency. Similarly, on the Jetson AGX Orin platform, the speedup increases from 27.23 to 28.75 at minimum frequency and from 8.67 to 9.06 at maximum frequency. These results clearly indicate that the proposed restructuring provides measurable performance benefits regardless of the target GPU architecture or operating regime.

An important aspect of this comparison is that the proposed algorithm processes a larger input dataset than the implementation from [5]. More specifically, the state-of-the-art algorithm operates on 26 samples, whereas the proposed implementation processes 34 samples. Despite this increased computational workload, the proposed method still achieves lower execution times. This behavior confirms that the reduction in arithmetic redundancy, the improved memory-access efficiency, and the enhanced parallel decomposition effectively compensate for the increased volume of data processed.

Overall, the comparative analysis validates the effectiveness of the proposed MDST decomposition strategy and demonstrates that increasing the degree of parallel segmentation from two sections to four sections constitutes a highly efficient approach for modern GPU architectures. The obtained results confirm that the proposed implementation offers better scalability, improved hardware utilization, and higher computational efficiency than the current state-of-the-art solution presented in [5].

The experimental results support the main contributions outlined in the Introduction. The proposed mathematical reformulation reduces the arithmetic complexity of the MDST and reveals four independent computational sections. GPU and CPU evaluations confirm that this decomposition can be efficiently mapped to different parallel architectures, although the GPU experiments also show that a single transform does not provide sufficient parallelism to fully utilize a modern GPU. The additional batched analysis demonstrates that high GPU utilization is achieved when the four-way intra-transform parallelism is combined with sufficient inter-transform parallelism. Furthermore, memory-access and energy measurements confirm that the performance gains are associated not only with parallel execution but also with reduced arithmetic and memory-access complexity.

7. Conclusions

This paper introduces a novel parallel implementation of the Modified Discrete Sine Transform (MDST) by decomposing the original transform into four independent computational sections that can execute concurrently. The proposed reformulation significantly reduces arithmetic complexity by minimizing the number of multiplications and memory-access operations while improving workload distribution across parallel processing units. Compared to the classical MDST formulation, the proposed approach achieves substantially lower execution times and improved computational efficiency on both GPU and CPU architectures.

The evaluation across multiple GPU platforms, including the Jetson AGX Xavier, Jetson AGX Orin, and GeForce RTX 4090, demonstrated that the proposed algorithm consistently delivers substantial performance gains under both low- and maximum-frequency operating conditions. Depending on the platform and frequency regime, the proposed implementation achieved acceleration factors ranging from 7.55 to 76.85 relative to the classical MDST implementation. These results confirm that the proposed decomposition strategy is highly effective for massively parallel architectures and remains efficient even under constrained operating conditions.

Furthermore, compute-only GPU energy measurements on the Jetson AGX Xavier showed that the four-section implementation reduced GPU energy consumption by approximately two orders of magnitude at both investigated GPU frequencies, demonstrating a substantial improvement in energy efficiency. This energy analysis complements the execution-time evaluation by demonstrating that the performance improvement is accompanied by a substantial reduction in the energy required for GPU computation. Accordingly, energy-per-transform provides an additional design metric for selecting the operating conditions of the proposed algorithm in power- and thermally constrained systems. The reported energy results are specific to the Jetson AGX Xavier and are not intended as a cross-platform energy ranking.

The memory-access analysis further demonstrated that the proposed implementation drastically reduces global and local memory transactions while efficiently exploiting shared memory and cache hierarchies. The reduction in memory-access overhead, combined with the algorithm’s lower arithmetic complexity, directly contributes to the observed improvements in execution speed. Moreover, the experimental results showed that modern GPU architectures with advanced cache systems, higher memory bandwidth, and improved warp schedulers particularly benefit the proposed execution model, with the Ada Lovelace architecture providing the highest acceleration factors among all evaluated platforms.

An additional contribution of this work is the complementary CPU-based evaluation conducted on isolated cores of an Intel Core i9-14900K processor. Although the algorithm was primarily designed for GPU execution, the CPU experiments showed that the proposed decomposition also scales efficiently on multi-core architectures, achieving speedups of 6.71 to 12.13, depending on the compiler optimization strategy. Furthermore, the low standard deviation values for the parallel implementation indicate highly deterministic temporal behavior, which is particularly important for real-time and embedded processing applications.

Future work will investigate FP32, mixed-precision, and fixed-point implementations, including batched reformulations suitable for Tensor Core execution, with particular emphasis on the trade-off between throughput, energy efficiency, and numerical accuracy.

The comparative analysis of the state-of-the-art MDST implementation presented in [5] confirmed the superiority of the proposed algorithm. Despite processing more input samples, the proposed implementation consistently achieved lower execution times and higher acceleration factors due to its improved four-section parallel decomposition and reduced memory-access overhead.

Overall, the results demonstrate that the proposed MDST algorithm is an efficient and scalable solution for high-performance signal-processing applications. The combination of reduced arithmetic complexity, optimized memory utilization, explicit parallel decomposition, and portability across GPU and CPU architectures makes the implementation particularly suitable for modern embedded systems, edge AI platforms, and high-performance computing environments.