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28 October 2026

54 Pages

FPGA Implementation Based on the Short-Memory Principle: Analysis of a Lorenz-Type Systems Family

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Department of Electronics, Instituto Nacional de Astrofísica, Óptica y Electrónica (INAOE), Luis Enrique Erro No. 1, Santa María Tonantzintla, San Andrés Cholula 72840, Puebla, Mexico
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Author to whom correspondence should be addressed.

Abstract

Fractional differential equations and fractional-order chaotic systems are attractive for secure communications, but the nonlocal memory of the Caputo derivative makes their digital implementation costly, so iterative methods are preferred for developing digital implementations of physical systems. This paper characterizes seven members of the Lorenz family (Lorenz, Chen, Burke–Shaw, Liu, Shimizu–Morioka, Lü, and Yang) and implements them on an FPGA using the short-memory principle. Starting from rectangular (REC) and predictor–corrector (PC) product-integration rules, we derive incremental iterative forms with a finite memory window suited to digital hardware. Largest Lyapunov exponent maps and bifurcation diagrams over fractional order and memory duration identify chaotic regimes for the Caputo case that, to our knowledge, have not been reported; for most systems, they stabilize once the window exceeds about 2 s. On a Cyclone V FPGA with a common Q1.11.20 fixed-point format, each architecture lets you select any of the seven systems and a memory depth of 1–1000 samples without resynthesis. For a 2 s window, REC uses fewer resources (3258 ALMs, 60 DSP blocks), whereas PC, thanks to its larger time step, reaches a higher estimated state-generation rate (330,457 versus 291,839 state vectors/s). Finally, 8-bit pseudorandom sequences extracted from the Lorenz system (1 Gbit per architecture) pass NIST SP 800-22 and the TestU01 Rabbit, Alphabit, and BlockAlphabit batteries. In addition, we present numerical simulations and their digital implementation to validate the numerical schemes.

1. Introduction

Fractional calculus studies the differentiation and integration of non-integer order, where the order may be rational, real, or complex [1,2,3]. Its origins date back to a 1695 correspondence between Leibniz and L’Hôpital, in which they first proposed the concept of a fractional derivative [4]. Although fractional calculus remained primarily theoretical for centuries, Fractional-Order Systems (FOSs) have received significant attention in recent decades because of their capacity to model memory phenomena and nonlocal behavior [5,6]. Compared with integer-order models, FOSs bring additional degrees of freedom that allow a flexible description of complex physical phenomena, and they have been applied in bio-inspired robotics, oscillator design, control theory, cryptography, and chaotic systems [7,8,9,10,11].
Chaotic systems are nonlinear dynamical systems characterized by strong sensitivity to initial conditions, topological mixing, and deterministic behavior that appears random [12,13,14]. Since Lorenz introduced his butterfly attractor in 1963 to model atmospheric convection [15], many chaotic systems have been proposed, including the Chen and Lü systems and hyperchaotic and memristive extensions [16,17,18,19]. Their unpredictability has been exploited in secure communications, Pseudorandom Number Generation (PRNG), neural networks, and Internet of Things (IoT) security [20,21,22].
Combining these fields yields fractional-order chaotic systems, where the derivative is commonly defined using the Caputo, Grünwald–Letnikov (GL), or Riemann–Liouville (RL) formulations [23]. Because these operators are nonlocal, the current state depends on the full history of previous states, making the computational cost considerably higher than for integer-order systems [24]. The short-memory principle mitigates this cost by truncating the history to a finite window of length L, assuming distant states contribute little; the resulting error can be bounded in terms of L and the fractional order α [25,26]. The window length therefore directly trades off accuracy and storage. Several numerical schemes compatible with this principle have been proposed, including the GL method and modified product-integration (PI) rules, such as the rectangular, trapezoidal, and predictor–corrector variants, where some numerical methods are described algebraically to express them as iterative methods of the form x n + 1 = x n + f ( · ) to facilitate the digital implementation [27].
In addition, extending classical chaotic systems to the fractional domain enriches their dynamics, with more complex bifurcation structures, enhanced ergodicity, and improved sensitivity, making them attractive for encryption and PRNG design [28]. Researchers have traditionally built chaotic systems with analog circuits based on operational amplifiers and discrete components, which are convenient for observing nonlinear dynamics [29,30]. Digital implementations, in contrast, offer better reproducibility, stability, and integration. Among digital platforms, field-programmable gate arrays (FPGAs) stand out for their parallelism, reconfigurability, and energy efficiency, which suit the repetitive arithmetic and memory accesses of fractional-order operators and enable real-time execution that general-purpose processors struggle to achieve.
Research on chaos in fractional-order systems and its applications in FPGAs is diverse. Ref. [31] presents GL-based operators as reusable hardware blocks with a short-memory window for several families of fractional-order oscillators on a Cyclone IV FPGA, using RAM/ROM blocks, resource-sharing control logic, and 32-bit fixed-point arithmetic. Later designs include GL integrators and differentiators using LUT- and quadratic- or piecewise-linear-based approximations, reducing the maximum absolute error by up to 91% over previous methods [32]; a complete GL differ-integral on a Virtex-5 with multiple window sizes is presented in [33]. Similar studies present a generic reconfigurable GL core on Artix-7 for four-wing systems [34] and an enhanced core whose fractional order, step size, and system parameters can be tuned at runtime, validated on a variable-order chaotic oscillator [35].
Another important line of research targets high-dimensional memristive and multi-scroll systems. Examples include a 5D memristive hyperchaotic system with coexisting attractors implemented on a Xilinx XC7Z020 FPGA with 32-bit floating-point [36], a 5D multi-wing system with hidden attractors [37], and a 4D memristive Hopfield neural network [38]. Recently, ref. [39] also proposed a piecewise-linear decomposition that avoids explicit Adomian polynomials for multi-scroll systems and targets ARM processors and FPGAs. In all of them, FPGA phase portraits agree with numerical simulations.
Several studies embed fractional chaos directly into application-specific designs, mostly for encryption. GL-based multi-scroll and memristive systems have been combined with CORDIC cores to generate PRNG sequences for image ciphers, with the sequences validated by NIST SP 800-22 [40,41]. A 1D time-delay fractional memristive system, modeled with the Caputo definition, has been implemented on an FPGA using a short-memory scheme and applied to a multilevel image-encryption algorithm [42]; ref. [43] explores randomness and image encryption using a memristive dual-wing fractional-order Hopfield neural network.
Many studies have developed diverse numerical schemes to simulate and implement fractional-order chaotic systems on FPGAs, formulating novel short-memory-based methods to use available hardware resources. Inspired by the aforementioned research, this paper aims for the dynamic characterization of seven chaotic systems that are members of the Lorenz family. We employ classical numerical methods to simulate fractional systems with the Caputo derivative. Using algebraic procedures, we derive simple iterative forms for the rectangular (REC) and predictor–corrector (PC) methods to compute dynamic characteristics of the Lorenz family—such as Lyapunov exponents and bifurcation diagrams—while accounting for the short-memory principle. This analysis identifies ranges of α and memory durations associated with chaotic behavior in the Lorenz family modeled with a Caputo derivative, which have not been reported previously.
The FPGA implementations complement this characterization through configurable model selection and memory depth. Within each REC or PC bitstream, any of the seven systems and a memory depth between 1 and 1000 samples can be selected through configuration inputs. Changing these settings requires a reset, without modifying the HDL code or resynthesizing the design. The work also quantitatively compares both implementations on the same FPGA platform using a common fixed-point representation, reporting resource consumption, update latency, maximum operating frequency, and estimated power under the specified configurations. A systematic comparison of fixed-point formats against double-precision references supports the selection of Q1.11.20 for the evaluated operating conditions.
Each implementation also supports a PRNG application using the state variables of the selected Lorenz-family model. Statistical evaluation is performed in the Lorenz configuration for both REC and PC. The resulting bitstreams satisfy the reported acceptance criteria of NIST SP 800-22 and the Rabbit, Alphabit, and BlockAlphabit batteries of TestU01. These results support the statistical quality of the evaluated streams under the specified conditions; potential cryptographic applications require further cryptanalytic assessment.
The paper is organized as follows. Section 2 presents the Riemann–Liouville integral and its numerical approximation. Section 3 discusses fractional-order derivatives and the theoretical basis of the short-memory principle. Section 4 analyzes numerical methods for solving fractional differential equations. In Section 5, we make the corresponding modifications to obtain iterative forms ready for implementation in digital systems. Section 6 introduces the generalized Lorenz family under study and reports numerical simulations to validate our approach; it also presents the FPGA experimental results and their application in PRNG. Finally, Section 7 concludes the work with the main results.

2. The Riemann–Liouville Integral and Its Numerical Approximation

In this section, we present an intuitive derivation of the Riemann–Liouville integral and several numerical methods for computing it. First, consider the well-known n-fold integral in Definition 1. Integral (1) simplifies n repeated integrals associated with one function to only one calculation. In this sense, the values of n considered by the operator in (1) are restricted to the natural numbers, as shown on the left-hand side of Figure 1.
Figure 1. Sets associated with the order of the Cauchy formula (Equation (1)) and the Riemann–Liouville integral (Equation (4)). Each arrow indicates that n is mapped to a natural number, whereas when generalized to an arbitrary value α , it is mapped to an arbitrary positive real number instead.
Definition 1
([44]). Let f : [ a , t ] → R be a continuous function, n ∈ N . The n-th repeated integral of f (the Cauchy formula for repeated integration or n-fold integral) is given by
I t n a f ( t ) = ∫ a t ∫ a τ 1 … ∫ a τ n − 1 ︸ n − times f τ n d τ n … d τ 2 d τ 1 ︸ n − times = 1 ( n − 1 ) ! ∫ a t t − τ n − 1 f ( τ ) d τ .
Now, we can ask what happens if the order of the n-fold integral is n = α ∈ R + , as shown on the right-hand side of Figure 1. The answer to this question requires the following special function.
Definition 2
([45]). Let α ∈ R + . The function
Γ ( α ) = ∫ 0 ∞ t α − 1 e − t d t = lim τ → ∞ ∫ 0 τ t α − 1 e − t d t ,
whenever the limit exists (as a finite number) is called the gamma function.
The gamma function generalizes the factorial function. In fact, by interpolating the factorial values, we can obtain the graphical representation of Function (2). Analytically, their relationship is straightforward; we can prove it by mathematical induction, i.e.,
Γ ( n ) = n − 1 ! ∀ n ∈ N ,
so the following operator is obtained [46,47].
Definition 3
([44,48]). Let α ∈ R + . The operator defined on L 1 [ a , b ] by
I R L a + α f ( t ) = 1 Γ ( α ) ∫ a t ( t − τ ) α − 1 f ( τ ) d τ ,
for a ≤ t ≤ b , is called the Riemann–Liouville fractional integral operator of order α.
One essential part of applied math is the computational implementation of equations, such as Integral (4). Let f ( t ) ∈ C ( I ) be the function of interest analyzed in the interval I = [ 0 , T ] . If the interval is divided into N R ∈ N subintervals, then the step size is
h = T − 0 N R = T N R ,
so the interval has N = N R + 1 points where the function could be evaluated with the algorithm. If the step size is smaller, the number N increases, i.e., there will be more points where the numerical algorithm is evaluated, improving the numerical estimation. Figure 2 shows a uniform grid in the interval I = [ 0 , T ] with N = N R + 1 equispaced nodes t k = k h with k = 0 , 1 , … , N R , i.e.,
0 = t 0 < t 1 < t 2 < … < t N R = T .
At the node t n with 0 ≤ n ≤ N R , regarding Definition 3, we get
I R L 0 + α f ( t ) | t = t n = 1 Γ ( α ) ∫ 0 t n ( t n − τ ) α − 1 f ( τ ) d τ = 1 Γ ( α ) ∫ t 0 t 1 ( t n − τ ) α − 1 f ( τ ) d τ + ∫ t 1 t 2 ( t n − τ ) α − 1 f ( τ ) d τ + ∫ t 2 t 3 ( t n − τ ) α − 1 f ( τ ) d τ + … + ∫ t n − 1 t n ( t n − τ ) α − 1 f ( τ ) d τ .
In summary, for  t = t n ,
I R L 0 + α f ( t ) | t = t n = 1 Γ ( α ) ∑ k = 0 n − 1 ∫ t k t k + 1 ( t n − τ ) α − 1 f ( τ ) d τ .
Equation (7) can be simplified if we can evaluate the integral. Considering the arbitrary subinterval t k , t k + 1 shown in Figure 3, and given that we do not have a fixed value for f ( t ) , we can take as a first approximation the corresponding evaluation at the infimum and supremum of the subinterval, thus approximating f ( t ) by a constant.
Figure 2. Visualization of the lattice associated with f ( t ) ∈ C ( I ) to determine numerically the Riemann–Liouville integral in (4).
Figure 3. Visualization of the k-th subinterval of f ( t ) ∈ C ( I ) .
Case (a) Evaluating the function at the infimum, we get
f ( t ) | [ t k , t k + 1 ) ≈ f ( t k ) .
Substituting and simplifying Expression (7), it follows that
I R L 0 + α f ( t ) | t = t n = 1 Γ ( α ) ∑ k = 0 n − 1 ∫ t k t k + 1 ( t n − τ ) α − 1 f ( τ ) d τ ≈ 1 Γ ( α ) ∑ k = 0 n − 1 ∫ t k t k + 1 ( t n − τ ) α − 1 f ( t k ) d τ = 1 Γ ( α ) ∑ k = 0 n − 1 f ( t k ) ∫ t k t k + 1 ( t n − τ ) α − 1 d τ .
According to the uniform distribution of the nodes, t k = k h , then
∫ t k t k + 1 ( t n − τ ) α − 1 d τ = 1 α ( t n − t k ) α − ( t n − t k + 1 ) α = 1 α n h − k h α − n h − ( k + 1 ) h α = h α α ( n − k ) α − ( n − k − 1 ) α .
so the Riemann–Liouville integral in (4) at time t n is approximated by
I R L 0 + α f ( t ) | t = t n ≈ h α Γ ( α + 1 ) ∑ k = 0 n − 1 f ( t k ) ( n − k ) α − ( n − k − 1 ) α .
Defining
Λ j ( β ) = ( j + 1 ) β − j β Γ ( β + 1 ) ,
the approximation (9) can be written more compactly as the left-fractional rectangular method
I R L 0 + α f ( t ) | t = t n = 1 Γ ( α ) ∫ 0 t n ( t n − τ ) α − 1 f ( τ ) d τ ≈ h α ∑ k = 0 n − 1 f ( t k ) Λ n − k − 1 ( α ) .
Case (b) Evaluating the function at the supremum, we get
f ( t ) | ( t k , t k + 1 ] ≈ f ( t k + 1 ) .
Substituting (12) into (7) and performing a similar simplification to the previous case allows us to obtain the right-fractional rectangular method
I R L 0 + α f ( t ) | t = t n = 1 Γ ( α ) ∫ 0 t n ( t n − τ ) α − 1 f ( τ ) d τ ≈ h α ∑ k = 0 n − 1 f ( t k + 1 ) Λ n − k − 1 ( α ) .
Remark 1.
Algorithms (11) and (13) consist of a finite sum of rectangles. In particular, if  α = 1 , then Λ n − k − 1 ( 1 ) = 1 and
I R L 0 + 1 f ( t ) | t = t n = ∫ 0 t n f ( τ ) d τ ≈ h ∑ k = 0 n − 1 f ( t k ) ,
recovering the classical sum of areas of rectangles (rectangle method) to compute the numerical approximation for the definite integral [49].
Case (c) Using the two-step Lagrange polynomial interpolation [49], the function f ( t ) can be approximated as
f ( t ) | [ t k , t k + 1 ] ≈ t k + 1 − t t k + 1 − t k f ( t k ) + t − t k t k + 1 − t k f ( t k + 1 ) .
Graphically, Equation (15) represents the linear approximation on the interval [ t k , t k + 1 ] , that is, the secant line from point ( t k , f ( t k ) ) to point ( t k + 1 , f ( t k + 1 ) ) (see Figure 3). Substituting (15) into (7) with h = t k + 1 − t k , it follows that
I R L 0 + α f ( t ) | t = t n = 1 Γ ( α ) ∑ k = 0 n − 1 ∫ t k t k + 1 ( t n − τ ) α − 1 f ( τ ) d τ ≈ 1 Γ ( α ) ∑ k = 0 n − 1 ∫ t k t k + 1 ( t n − τ ) α − 1 t k + 1 − τ h f ( t k ) + τ − t k h f ( t k + 1 ) d τ = 1 h Γ ( α ) ∑ k = 0 n − 1 f ( t k ) I 1 + f ( t k + 1 ) I 2 ,
where
I 1 = ∫ t k t k + 1 ( t n − τ ) α − 1 t k + 1 − τ d τ ,
I 2 = ∫ t k t k + 1 ( t n − τ ) α − 1 τ − t k d τ .
Integrals (17) and (18) are solved using the tabular method for integration by parts as follows [50]: Fractalfract 10 00753 i001 Calculating the corresponding diagonal products between the functions connected by the corresponding arrows and their corresponding signs, one obtains
I 1 = − 1 α t n − τ α t k + 1 − τ + ( t n − τ ) α + 1 α ( α + 1 ) | t k t k + 1 = 1 α ( α + 1 ) t n − t k + 1 α + 1 − t n − t k α − α t k + 1 − t k − t k + 1 + t n = h α + 1 α ( α + 1 ) ( n − k − 1 ) α + 1 − ( n − k ) α ( n − k − 1 − α ) ,
I 2 = − 1 α t n − τ α τ − t k − ( t n − τ ) α + 1 α ( α + 1 ) | t k t k + 1 = 1 α ( α + 1 ) t n − t k α + 1 + t n − t k + 1 α t k + 1 − t n − ( α + 1 ) t k + 1 − t k = h α + 1 α ( α + 1 ) ( n − k ) α + 1 + ( n − k − 1 ) α ( k − n − α ) .
Substituting the previous results into (16) allows us to obtain
I R L 0 + α f ( t ) | t = t n ≈ h α Γ ( α + 2 ) ∑ k = 0 n − 1 f ( t k ) ( n − k − 1 ) α + 1 − ( n − k ) α ( n − k − 1 − α ) + f ( t k + 1 ) ( n − k ) α + 1 + ( n − k − 1 ) α ( k − n − α ) .
Remark 2.
The trapezoidal method is obtained by evaluating (19) with α = 1 , i.e.,
I R L 0 + 1 f ( t ) | t = t n = ∫ 0 t n f ( τ ) d τ ≈ h 2 ∑ k = 0 n − 1 f ( t k ) + f ( t k + 1 ) .
The numerical method in (19) explicitly shows how each segment of the function contributes to the fractional operator’s memory; however, it evaluates the contribution of f ( t k ) twice in consecutive loops. To improve computational efficiency, the first step is to expand (19) as follows:
I R L 0 + α f ( t ) | t = t n ≈ h α Γ ( α + 2 ) f ( t 0 ) ( n − 1 ) α + 1 − n α ( n − 1 − α ) + Σ 1 + Σ 2 + f ( t n ) ,
where
Σ 1 = ∑ k = 1 n − 1 f ( t k ) ( n − k − 1 ) α + 1 − ( n − k ) α ( n − k − 1 − α ) ,
and
Σ 2 = ∑ k = 0 n − 2 f ( t k + 1 ) ( n − k ) α + 1 + ( n − k − 1 ) α ( k − n − α ) = ∑ k = 0 n − 2 f ( t k + 1 ) [ n − ( k + 1 ) + 1 ] α + 1 + [ n − ( k + 1 ) ] α [ − n − α + ( k + 1 ) − 1 ] = ∑ k = 0 + 1 n − 2 + 1 f ( t k + 1 − 1 ) [ n − ( k + 1 − 1 ) + 1 ] α + 1 + [ n − ( k + 1 − 1 ) ] α [ − n − α + ( k + 1 − 1 ) − 1 ] Σ 2 = ∑ k = 1 n − 1 f ( t k ) ( n − k + 1 ) α + 1 + ( n − k ) α ( k − 1 − n − α ) .
By grouping the sums and simplifying,
Σ 1 + Σ 2 = ∑ k = 1 n − 1 f ( t k ) ( n − k − 1 ) α + 1 − ( n − k ) α ( n − k − 1 − α ) + ( n − k + 1 ) α + 1 + ( n − k ) α ( k − 1 − n − α ) = ∑ k = 1 n − 1 f ( t k ) ( n − k + 1 ) α + 1 + ( n − k − 1 ) α + 1 − 2 ( n − k ) α + 1 ,
so that (19) is rewritten as
I R L 0 + α f ( t ) | t = t n ≈ h α Γ ( α + 2 ) { f ( t 0 ) ( n − 1 ) α + 1 − n α ( n − 1 − α ) + f ( t n ) + ∑ k = 1 n − 1 f ( t k ) ( n − k + 1 ) α + 1 + ( n − k − 1 ) α + 1 − 2 ( n − k ) α + 1 } .
Defining
W j ( β ) = ( j + 1 ) β + 1 + ( j − 1 ) β + 1 − 2 j β + 1 ,
Ω j ( β ) = ( j − 1 ) β + 1 − j β ( j − 1 − β ) ,
Equation (21) is expressed as the fractional trapezoidal method
I R L 0 + α f ( t ) | t = t n = 1 Γ ( α ) ∫ 0 t n ( t n − τ ) α − 1 f ( τ ) d τ ≈ h α Γ ( α + 2 ) f ( t 0 ) Ω n ( α ) + ∑ k = 1 n − 1 f ( t k ) W n − k ( α ) + f ( t n ) .
Remark 3.
According to [51], the following equation holds for any whole number r:
∑ k = m p a k = ∑ k = m + r p + r a k − r .
In the previous analysis, the simplification of Σ 2 follows from (25).
Remark 4.
The coefficients belonging to the same value of f ( t k ) are grouped together in Method (24), reducing the round-off error and the inaccuracies we get by taking a certain number of decimal places instead of taking the entire number [52]. Since the weight vector in (22) depends only on the difference n − k , when performing the numerical simulation, the vector W n − k ( α ) is pre-calculated, and the calculation at each step reduces to a dot product between the function history vector and the weight vector W n − k ( α ) , resulting in greater computational speed.

3. Fractional-Order Derivatives and the Short-Memory Principle

In this section, we contrast the Riemann integral with the fractional derivative and the short-memory principle, which we use to optimize the numerical methods in the next section. Readers interested in delving deeper into fractional calculus may consult [44,48,53,54].
Definition 4.
Let α ∈ R + and n = α = min k ∈ N ∣ k ≥ α . The operator defined by
D R L a + α f ( t ) = D n I R L a + n − α f ( t ) = 1 Γ ( n − α ) d n d t n ∫ a t t − τ n − α − 1 f ( τ ) d τ ,
is called the Riemann–Liouville fractional differential operator of order α, with  D n = d n d t n the n-th derivative of integer order.
Definition 5.
Let α ∈ R + and n = ⌈ α ⌉ = min k ∈ N ∣ k ≥ α . For  D n f ( t ) = f ( n ) ∈ L 1 [ a , b ] , the operator defined by
D C a + α f ( t ) = I R L a + n − α D n f ( t ) = 1 Γ ( n − α ) ∫ a t t − τ n − α − 1 f ( n ) ( τ ) d τ ,
is called the Caputo fractional differential operator of order α.
For practical purposes, consider 0 < α ≤ 1 , so that Operator (27) reduces to
D C a + α f ( t ) = I R L a + 1 − α f ′ ( t ) = 1 Γ ( 1 − α ) ∫ a t t − τ − α f ′ ( τ ) d τ .
As we can see from Operators (26) and (27), the calculation of each derivative at time t involves all the information from the initial time t 0 = a . From a computational point of view, we see later that this has significant repercussions due to resource constraints, such as memory. That is why we must look for ways to reduce the computational cost. One way to address this situation is through the well-known short-memory principle, which relates the approximation error to the memory length L.
(i) 
Riemann–Liouville derivative of order 0 < α < 1 . Let Δ ( t ) be the error between D R L a α f ( t ) and D R L t − L α f ( t ) in a + L ≤ t ≤ b ; then,
Δ ( t ) = D R L a α f ( t ) − D R L t − L α f ( t ) = 1 Γ ( 1 − α ) d d t ∫ a t − L t − τ − α f ( τ ) d τ = 1 Γ ( 1 − α ) { ∫ a t − L ∂ ∂ t t − τ − α f ( τ ) d τ + ( t − τ ) − α f ( τ ) | τ = t − L d ( t − L ) d t − ( t − τ ) − α f ( τ ) | τ = a d a d t } Δ ( t ) = − α Γ ( 1 − α ) ∫ a t − L t − τ − α − 1 f ( τ ) d τ + L − α Γ ( 1 − α ) f ( t − L )
If M = ∥ f ∥ ∞ = sup | f ( t ) | , t ∈ ( a , b ) , then
| Δ ( t ) | = − α Γ ( 1 − α ) ∫ a t − L t − τ − α − 1 f ( τ ) d τ + L − α Γ ( 1 − α ) f ( t − L ) ≤ − α Γ ( 1 − α ) ∫ a t − L t − τ − α − 1 f ( τ ) d τ + L − α Γ ( 1 − α ) f ( t − L ) ≤ 1 Γ ( − α ) ∫ a t − L t − τ − α − 1 | f ( τ ) | d τ + L − α Γ ( 1 − α ) | f ( t − L ) | ≤ M Γ ( − α ) ∫ a t − L t − τ − α − 1 d τ + L − α M Γ ( 1 − α ) = M Γ ( − α ) 1 − α ( t − a ) − α − L − α + L − α M Γ ( 1 − α ) = M Γ ( 1 − α ) ( t − a ) − α − M L − α Γ ( 1 − α ) + L − α M Γ ( 1 − α ) = M Γ ( 1 − α ) ( t − a ) − α
Finally, considering a + L ≤ t , it follows that L ≤ t − a , which implies L α ≤ ( t − a ) α , i.e.,  ( t − a ) − α ≤ L − α . Therefore, the following bound is obtained:
| Δ ( t ) | ≤ M Γ ( 1 − α ) ( t − a ) − α ≤ M Γ ( 1 − α ) L − α .
Remark 5.
Inequality (29) can be used to determine memory length L providing the required precision ε 1 . Then, to ensure | Δ ( t ) | < ε 1 (the estimation error), the memory length should satisfy
M ϵ 1 Γ ( 1 − α ) 1 / α ≤ L ,
in order to satisfy the short-memory principle
D R L a α f ( t ) ≈ D R L t − L α f ( t ) .
(ii) 
Caputo derivative of order 0 < α < 1 . In a similar manner to the previous case, the error is given by
Δ C = D C a α f ( t ) − D C t − L α f ( t ) = 1 Γ ( 1 − α ) ∫ a t − L t − τ − α f ′ ( τ ) d τ .
From Equation (32), define
u = 1 Γ ( 1 − α ) ( t − τ ) − α , d u = α Γ ( 1 − α ) ( t − τ ) − α − 1 d τ d v = f ′ ( τ ) d τ , v = f ( τ )
Then, one has
Δ C = 1 Γ ( 1 − α ) ( t − τ ) − α f ( τ ) | a t − L − α Γ ( 1 − α ) ∫ a t − L t − τ − α − 1 f ( τ ) d τ = 1 Γ ( 1 − α ) ( t − τ ) − α f ( τ ) | τ = t − L − ( t − τ ) − α f ( τ ) | τ = a − α Γ ( 1 − α ) ∫ a t − L t − τ − α − 1 f ( τ ) d τ = 1 Γ ( 1 − α ) L − α f ( t − L ) − ( t − a ) − α f ( a ) − α Γ ( 1 − α ) ∫ a t − L t − τ − α − 1 f ( τ ) d τ .
Considering the bound M = ∥ f ∥ ∞ = sup | f ( t ) | , t ∈ ( a , b ) and the triangle inequality, it is possible to conclude
| Δ C | ≤ M Γ ( 1 − α ) L − α + ( t − a ) − α + α M Γ ( 1 − α ) ∫ a t − L t − τ − α − 1 d τ = M Γ ( 1 − α ) L − α + ( t − a ) − α + α M Γ ( 1 − α ) L − α α − ( t − a ) − α α = 2 M L − α Γ ( 1 − α ) .
When | Δ C | < ε 2 holds, the memory length must satisfy
2 M ϵ 2 Γ ( 1 − α ) 1 / α ≤ L ,
to fulfill the short-memory principle
D C a α f ( t ) ≈ D C t − L α f ( t ) .
Remark 6
([48]). The above result was expected since, for absolutely continuous functions f ∈ A C 1 [ a , b ] and 0 < α < 1 , the following relation holds:
D R L a α f ( t ) = D C a α f ( t ) + f ( a ) Γ ( 1 − α ) ( t − a ) − α .
Figure 4 illustrates the general idea behind the short-memory principle: the classical derivative (of order n) is a local operator because it depends only on the function’s behavior at the evaluation point f ( t ^ ) . In contrast, the fractional derivative is a non-local operator, since the value of the derivative at the point t ^ depends on the entire history of the function from an initial point a. Equation (34) states that, when t ^ is large, the contribution of the values of f ′ ( τ ) near the lower limit a becomes negligible in the calculation of the derivative at t ^ , that is, we can define a memory window L to approximate the fractional derivative by considering only the recent interval. This reduces the computational load, since computing an integral over the entire history of a system (a to t) requires memory and processing time that grow indefinitely as t ^ increases. By limiting the calculation to a window L, the computational cost becomes constant and manageable [55,56].
Figure 4. Visualization of the short-memory principle.

4. Numerical Solution of Fractional Differential Equations

A fractional differential equation (FDE) can be defined similarly to ordinary or partial differential equations, i.e., equations that involve fractional-order derivatives of a dependent variable with respect to another independent variable, such as time. Assuming the existence and uniqueness of solutions, this section presents numerical methods based on successive approximations to solve FDE. The idea of successive approximations is simple [57,58,59]; recall that the function x ( t ) is a solution to the initial value problem x ˙ = f ( t , x ( t ) ) , x a = x ( a ) if and only if it is a solution to Volterra’s integral equation
x ( t ) = x a + ∫ a t f ( τ , x ( τ ) ) d τ .
Let us now see how to formulate the integral equation problem and the solution method for FDEs.

4.1. Fractional Differential Equations with Caputo Derivative

Let m − 1 < α < m be the fractional-order; the function x ( t ) is a solution of
D C a α x ( t ) = f ( t , x ( t ) ) , d ℓ x d t ℓ | t = a = x a ( ℓ ) , ℓ = 0 , 1 , … , m − 1 ,
if and only if it is a solution of Volterra’s integral equation
x ( t ) = ∑ ℓ = 0 m − 1 ( t − a ) ℓ ℓ ! x a ( ℓ ) + I R L a α f ( t , x ( t ) )
whose solution can be constructed using the method of successive approximations [44,48]. Evidently, if  α = 1 , we recover the classical initial value problem and its integral—Equation (36). In particular, for  0 < α ≤ 1 , Volterra’s integral in Equation (38) takes the following form:
x ( t ) = x a + 1 Γ ( α ) ∫ a t ( t − τ ) α − 1 f ( τ , x ( τ ) ) d τ .
In contrast to the general exposition of FDE from an analytical point of view, using different valuable methods to determine explicit forms associated with the solution sought in various problems, multiple studies have been carried out to analyze numerical methods to solve FDEs, including error analysis and computational implementation [60,61,62,63,64]. Evaluating Volterra’s integral in Equation (38) at time t = t n + 1 with initial time a = 0 ,
x ( t n + 1 ) = ∑ ℓ = 0 m − 1 t n + 1 ℓ ℓ ! x 0 ( ℓ ) + I R L 0 α f ( t , x ( t ) ) | t = t n + 1 .
Based on the left-fractional rectangular method in (11), it follows Approximation (40) x ( t n + 1 ) = x n + 1 can be determined as
x n + 1 = ∑ ℓ = 0 m − 1 t n + 1 ℓ ℓ ! x 0 ( ℓ ) + h α ∑ k = 0 ( n + 1 ) − 1 f ( t k , x k ) Λ ( n + 1 ) − k − 1 ( α ) .
Reducing terms, we have, for  m − 1 < α < m ,
x n + 1 = ∑ ℓ = 0 m − 1 t n + 1 ℓ ℓ ! x 0 ( ℓ ) + h α ∑ k = 0 n f ( t k , x k ) Λ n − k ( α ) , Λ n − k ( α ) = ( n − k + 1 ) α − ( n − k ) α Γ ( α + 1 ) .
Similarly, now using the right-fractional rectangular method in (13), the solution can be approximated for m − 1 < α < m as
x n + 1 = ∑ ℓ = 0 m − 1 t n + 1 ℓ ℓ ! x 0 ( ℓ ) + h α ∑ k = 0 n f ( t k + 1 , x k + 1 ) Λ n − k ( α ) , Λ n − k ( α ) = ( n − k + 1 ) α − ( n − k ) α Γ ( α + 1 ) .
Finally, based on the fractional trapezoidal formula in (24), it is straightforward to verify for m − 1 < α < m
x n + 1 = ∑ ℓ = 0 m − 1 t n + 1 ℓ ℓ ! x 0 ( ℓ ) + h α Γ ( α + 2 ) f ( t 0 , x 0 ) Ω n + 1 ( α ) + f ( t n + 1 , x n + 1 ) + ∑ k = 1 n f ( t k , x k ) W n − k + 1 ( α ) , Ω n + 1 ( α ) = n α + 1 − ( n + 1 ) α ( n − α ) , W n − k + 1 ( α ) = ( n − k + 2 ) α + 1 + ( n − k ) α + 1 − 2 ( n − k + 1 ) α + 1 .
In particular, if  0 < α < 1 , Algorithms (41), (42) and (43) take the form of product integration (PI) rules to solve FDEs [61,65]:
  • Explicit PI rectangular rule (fractional forward Euler method):
    x n + 1 = x 0 + h α ∑ k = 0 n f ( t k , x k ) Λ n − k ( α ) , Λ n − k ( α ) = ( n − k + 1 ) α − ( n − k ) α Γ ( α + 1 ) ,
  • Implicit PI rectangular rule (fractional backward Euler method):
    x n + 1 = x 0 + h α ∑ k = 0 n f ( t k + 1 , x k + 1 ) Λ n − k ( α ) , Λ n − k ( α ) = ( n − k + 1 ) α − ( n − k ) α Γ ( α + 1 ) ,
  • Implicit-type trapezoidal rule:
    x n + 1 = x 0 + h α Γ ( α + 2 ) f ( t 0 , x 0 ) Ω n + 1 ( α ) + f ( t n + 1 , x n + 1 ) + ∑ k = 1 n f ( t k , x k ) W n − k + 1 ( α ) , Ω n + 1 ( α ) = n α + 1 − ( n + 1 ) α ( n − α ) , W n − k + 1 ( α ) = ( n − k + 2 ) α + 1 + ( n − k ) α + 1 − 2 ( n − k + 1 ) α + 1 .
Remark 7.
We obtain classical numerical methods from Algorithms (44) and (45) if α = 1 . In both cases, the coefficient Λ n − k ( 1 ) = 1 , which implies
x n + 1 = x 0 + h ∑ k = 0 n f ( t k , x k ) ,
and
x n + 1 = x 0 + h ∑ k = 0 n f ( t k + 1 , x k + 1 ) .
Methods (47) and (48) represent the classical forward Euler and backward Euler methods, respectively [49,66]. On the other hand, considering α = 1 in (46), one has Ω n + 1 ( 1 ) = 1 and W n − k + 1 ( 1 ) = 2 , so that
x n + 1 = x 0 + h 2 f ( t 0 , x 0 ) + f ( t n + 1 , x n + 1 ) + 2 ∑ k = 1 n f ( t k , x k ) = x 0 + h 2 f ( t 0 , x 0 ) + f ( t n + 1 , x n + 1 ) + ∑ k = 1 n f ( t k , x k ) + ∑ k = 0 + 1 ( n − 1 ) + 1 f ( t ( k + 1 ) − 1 , x ( k + 1 ) − 1 ) .
Applying Property (25) to the last term of the above equation, it follows that
x n + 1 = x 0 + h 2 f ( t 0 , x 0 ) + f ( t n + 1 , x n + 1 ) + ∑ k = 1 n f ( t k , x k ) + ∑ k = 0 n − 1 f ( t k + 1 , x k + 1 ) = x 0 + h 2 f ( t 0 , x 0 ) + ∑ k = 1 n f ( t k , x k ) + f ( t n + 1 , x n + 1 ) + ∑ k = 0 n − 1 f ( t k + 1 , x k + 1 ) = x 0 + h 2 ∑ k = 0 n f ( t k , x k ) + ∑ k = 0 n f ( t k + 1 , x k + 1 ) .
By grouping the two previous sums, we arrive at the trapezoidal method for solving ordinary differential equations [49,66]:
x n + 1 = x 0 + h 2 ∑ k = 0 n f ( t k , x k ) + f ( t k + 1 , x k + 1 ) .
The calculation of x n + 1 in (45) and (46) depends on itself. However, the solution can be estimated in two phases: the predictor step with Equation (44), which provides an initial estimate of the solution, and later the corrector step with (46), which refines the initial estimate. These ideas allow us to obtain the predictor–corrector (PC) scheme (see [67] for an in-depth discussion regarding the error analysis of this numerical method):
x n + 1 P = x 0 + h α ∑ k = 0 n f ( t k , x k ) Λ n − k ( α ) , x n + 1 = x 0 + h α Γ ( α + 2 ) f ( t 0 , x 0 ) Ω n + 1 ( α ) + f ( t n + 1 , x n + 1 P ) + ∑ k = 1 n f ( t k , x k ) W n − k + 1 ( α ) .

4.2. Fractional Differential Equations with Riemann–Liouville Derivative

Consider the Riemann–Liouville operator in (26) with m − 1 < α < m , and the nonlinear model
D R L a α x ( t ) = f ( t , x ( t ) ) , D R L a α − ℓ x ( a + ) = b ℓ , ℓ = 1 , … , m ,
where D R L a α − ℓ x ( a + ) represents the limit at almost all the points of the right-hand side neighborhood of a, i.e., in the set ( a , a + ϵ ) , ϵ > 0 :
D R L a α − ℓ x ( a + ) = lim t → a + D R L a α − ℓ x ( t ) , ℓ = 1 , … , m − 1 , D R L a α − m x ( a + ) = lim t → a + I R L a + m − α x ( t ) , α ≠ m D R L a 0 x ( a + ) = x ( a ) , α = m
According to [44,48], x ( t ) is a solution of (51) if and only if it is a solution of the Volterra equation
x ( t ) = ∑ ℓ = 1 m b ℓ Γ ( α − ℓ + 1 ) ( t − a ) α − ℓ + 1 Γ ( α ) ∫ a t ( t − τ ) α − 1 f ( τ , x ( τ ) ) d τ .
Evaluating Equation (53) at t = t n + 1 with a = 0 , we obtain
x ( t n + 1 ) = ∑ ℓ = 1 m b ℓ Γ ( α − ℓ + 1 ) t n + 1 α − ℓ + I R L 0 + α f ( t , x ( t ) ) | t = t n + 1 .
Now, considering numerical Method (11) with t n + 1 = ( n + 1 ) h , it follows that
x n + 1 = ∑ ℓ = 1 m b ℓ Γ ( α − ℓ + 1 ) ( ( n + 1 ) h ) α − ℓ + h α ∑ k = 0 n f ( t k , x k ) Λ n − k ( α ) , Λ n − k ( α ) = ( n − k + 1 ) α − ( n − k ) α Γ ( α + 1 ) .
For systems of order 0 < α ≤ 1 , the corresponding integral in Equation (53) is reduced to
x ( t ) = b 1 Γ ( α ) ( t − a ) α − 1 + 1 Γ ( α ) ∫ a t ( t − τ ) α − 1 f ( τ , x ( τ ) ) d τ ,
with
b 1 = D R L a α − 1 x ( a + ) = lim t → a + I R L a + 1 − α x ( t ) .
Taking x 0 = b 1 h α − 1 Γ ( α ) and a = 0 , the Explicit PI-RL rectangular rule is given as
x n + 1 = ( n + 1 ) α − 1 x 0 + h α ∑ k = 0 n f ( t k , x k ) Λ n − k ( α ) , Λ n − k ( α ) = ( n − k + 1 ) α − ( n − k ) α Γ ( α + 1 ) .

5. Practical Aspects for FPGA Implementation of Numerical Methods

The numerical methods presented in the previous section are based on simple operations, which allow us to determine closed forms for computing the n-th iteration of the solution of an FDE. However, each iteration depends on a finite sum that must be computed at each instant, which imposes a considerable computational burden. In this section, we make a small modification to the algorithms to obtain equivalent forms with greater computational advantage, which we use to implement dynamic systems in embedded systems [68].

5.1. Modified Explicit PI Algorithm

According to (44), it is straightforward to obtain the sample n
x n = x 0 + h α ∑ k = 0 n − 1 f ( t k , x k ) Λ n − k − 1 ( α ) , Λ n − k − 1 ( α ) = ( n − k ) α − ( n − k − 1 ) α Γ ( α + 1 ) .
From (59), the initial condition is expressed as x 0 = x n − h α ∑ k = 0 n − 1 f ( t k , x k ) Λ n − k − 1 ( α ) , so that Equation (44) can be written as
x n + 1 = x n − h α ∑ k = 0 n − 1 f ( t k , x k ) Λ n − k − 1 ( α ) + h α ∑ k = 0 n f ( t k , x k ) Λ n − k ( α ) = x n + h α ∑ k = 0 n − 1 f ( t k , x k ) Λ n − k ( α ) − Λ n − k − 1 ( α ) + h α f ( t n , x n ) Λ 0 ( α ) .
Then, after some elementary simplifications, an iterative method for n ≥ 1 is obtained, i.e.,
x n + 1 = x n + h α Γ ( α + 1 ) f ( t n , x n ) + ∑ k = 0 n − 1 f ( t k , x k ) W n − k ( α − 1 ) .
It is essential to mention that the iteration for n = 0 is obtained directly from Algorithm (44) to complete the calculations. Considering that the sum must be performed from k = 0 to k = n − 1 at each iteration of Algorithm (60), we employ the short-memory principle in (34) to reduce the computational cost and physical limitations of embedded systems. Then, for  n ≥ L + 1 , the iterations of (60) are recalculated as
x n + 1 = x n + h α Γ ( α + 1 ) f ( t n , x n ) + ∑ k = n − 1 − L n − 1 f ( t k , x k ) W n − k ( α − 1 ) .
Defining j = n − k as a new variable yields k = n − j . Then, (60) and (61) are rewritten as
x n + 1 = x n + h α Γ ( α + 1 ) f ( t n , x n ) + ∑ j = 1 n f ( t n − j , x n − j ) W j ( α − 1 )
and
x n + 1 = x n + h α Γ ( α + 1 ) f ( t n , x n ) + ∑ j = 1 L + 1 f ( t n − j , x n − j ) W j ( α − 1 ) ,
respectively. Finally, by setting the initial value x 0 , use Algorithm (44) for n = 0 , so that the modified explicit PI algorithm for FPGA implementations has the recursive equation
x 1 = x 0 + h α Γ ( α + 1 ) f ( t 0 , x 0 ) x n + 1 = x n + h α Γ ( α + 1 ) f ( t n , x n ) + ∑ j = 1 ν f ( t n − j , x n − j ) W j ( α − 1 ) ,
with
ν = n , 1 ≤ n ≤ L L + 1 , n ≥ L + 1
Remark 8.
In particular, for  α = 1 , one has W j ( 0 ) = 0 , so we get the classical Euler’s numerical method
x n + 1 = x n + h f ( t n , x n ) .

5.2. Modified Explicit PC Algorithm

In a similar manner to the previous case, from (46), we get x n and solve for the value of x 0 given by
x 0 = x n − h α Γ ( α + 2 ) f ( t 0 , x 0 ) Ω n ( α ) + f ( t n , x n ) + ∑ k = 1 n − 1 f ( t k , x k ) W n − k ( α ) .
Substituting the above equation into (50) yields
x n + 1 = x n + h α Γ ( α + 2 ) { f ( t 0 , x 0 ) Ω n + 1 ( α ) − Ω n ( α ) + f ( t n + 1 , x n + 1 P ) + f ( t n , x n ) W 1 ( α ) − 1 + ∑ k = 1 n − 1 f ( t k , x k ) W n − k + 1 ( α ) − W n − k ( α ) } .
Combining with the explicit rule in (60) and performing the corresponding simplifications, for  n ≥ 2 , we obtain the following numerical method:
x n + 1 P = x n + h α Γ ( α + 1 ) f ( t n , x n ) + ∑ k = 0 n − 1 f ( t k , x k ) W n − k ( α − 1 ) x n + 1 = x n + h α Γ ( α + 2 ) [ f ( t 0 , x 0 ) γ n ( α ) + ∑ k = 1 n − 1 f ( t k , x k ) δ n − k ( α ) + f ( t n + 1 , x n + 1 P ) + ( 2 α + 1 − 3 ) f ( t n , x n ) ] ,
where
γ n ( α ) = Ω n + 1 ( α ) − Ω n ( α ) = n α ( 2 n − 1 − α ) − ( n + 1 ) α ( n − α ) − ( n − 1 ) α + 1 ,
and
δ n − k ( α ) = W n − k + 1 ( α ) − W n − k ( α ) = ( n − k + 2 ) α + 1 + 3 ( n − k ) α + 1 − 3 ( n − k + 1 ) α + 1 − ( n − k − 1 ) α + 1 .
Remark 9.
If α = 1 , we obtain γ n ( α ) = 0 and δ n − k ( α ) = 0 . Numerical Method (67) is reduced to the classical predictor–corrector method
x n + 1 P = x n + h f ( t n , x n ) x n + 1 = x n + h 2 f ( t n , x n ) + f ( t n + 1 , x n + 1 P )
According to the short-memory principle, one has
x n + 1 P = x n + h α Γ ( α + 1 ) f ( t n , x n ) + ∑ k = n − 1 − L n − 1 f ( t k , x k ) W n − k ( α − 1 ) x n + 1 = x n + h α Γ ( α + 2 ) [ f ( t 0 , x 0 ) γ n ( α ) + ∑ k = n − L n − 1 f ( t k , x k ) δ n − k ( α ) + f ( t n + 1 , x n + 1 P ) + ( 2 α + 1 − 3 ) f ( t n , x n ) ] ,
where n ≥ L + 2 . To further simplify the algorithms and obtain a more computationally efficient implementation, let us again consider the change of variables j = n − k , which implies k = n − j . Then, Algorithms (67) and (71) are rewritten as
x n + 1 P = x n + h α Γ ( α + 1 ) f ( t n , x n ) + ∑ j = 1 n f ( t n − j , x n − j ) W j ( α − 1 ) x n + 1 = x n + h α Γ ( α + 2 ) [ f ( t 0 , x 0 ) γ n ( α ) + ∑ j = 1 n − 1 f ( t n − j , x n − j ) δ j ( α ) + f ( t n + 1 , x n + 1 P ) + ( 2 α + 1 − 3 ) f ( t n , x n ) ]
and
x n + 1 P = x n + h α Γ ( α + 1 ) f ( t n , x n ) + ∑ j = 1 L + 1 f ( t n − j , x n − j ) W j ( α − 1 ) x n + 1 = x n + h α Γ ( α + 2 ) [ f ( t 0 , x 0 ) γ n ( α ) + ∑ j = 1 L f ( t n − j , x n − j ) δ j ( α ) + f ( t n + 1 , x n + 1 P ) + ( 2 α + 1 − 3 ) f ( t n , x n ) ]
respectively.
Finally, we can establish a recursive equation for the modified explicit PC algorithm by setting the initial value x 0 , and using Algorithms (44), (62) for n = 0 and n = 1 , respectively, that is,
x 1 = x 0 + h α Γ ( α + 1 ) f ( t 0 , x 0 ) x 2 = x 1 + h α Γ ( α + 1 ) f ( t 1 , x 1 ) + ( 2 α − 2 ) f ( t 0 , x 0 ) x n + 1 P = x n + h α Γ ( α + 1 ) f ( t n , x n ) + ∑ j = 1 ν f ( t n − j , x n − j ) W j ( α − 1 ) x n + 1 = x n + h α Γ ( α + 2 ) [ f ( t 0 , x 0 ) γ n ( α ) + ∑ j = 1 ν ¯ f ( t n − j , x n − j ) δ j ( α ) + f ( t n + 1 , x n + 1 P ) + ( 2 α + 1 − 3 ) f ( t n , x n ) ]
with
ν = n , 2 ≤ n ≤ L L + 1 , n ≥ L + 1 ν ¯ = n − 1 , 2 ≤ n ≤ L L , n ≥ L + 1
Remark 10.
Consider the function γ n ( α ) in (68) for n ≥ 2 . By direct substitution, one gets γ n ( 0 ) = γ n ( 1 ) = 0 . If  0 < α < 1 , then lim n → ∞ γ n ( α ) = 0 for all n ≥ 2 . The most significant value always occurs in iteration n = 2 , i.e.,  γ 2 ( α ) > γ n ( α ) for all n ≥ 3 . In addition, the minimum possible value always occurs when α ≈ 0.649824 (see Appendix B for details). Then, for practical purposes, from algorithm (74), let
x ^ n + 1 = x n + h α Γ ( α + 2 ) ∑ j = 1 ν ¯ f ( t n − j , x n − j ) δ j ( α ) + f ( t n + 1 , x n + 1 P ) + ( 2 α + 1 − 3 ) f ( t n , x n ) ,
for ∥ γ n ( α ) ∥ < ε ˜ from a determined n ^ . Then, considering M = ∥ f ∥ ∞ = sup | f ( t ) | , t ∈ ( a , b ) , one has that
∥ x n + 1 − x ^ n + 1 ∥ = h α Γ ( α + 2 ) ∥ f ( t 0 , x 0 ) γ n ( α ) ∥ ≤ h α M Γ ( α + 2 ) ε ˜
for n ^ ≤ n , and  ∥ x n + 1 − x ^ n + 1 ∥ → 0 as n → ∞ . This simplification reduces resource use, such as embedded system memory.
Remark 11.
Numerical Methods (64) and (74) consider the short-memory principle. However, because they are expressed as difference equations, L is expressed in terms of the number of samples. With a window memory time T m e m and step size h, we have L = T m e m h . The pseudocode provided by Algorithms A1 and A2 describes each numerical method.

6. Numerical and Experimental Results

Fractional-order derivatives introduce a memory effect that captures long-range temporal dependencies, enabling the more accurate modeling of real-world phenomena than integer-order approaches [69]. In chaotic systems, this intrinsic memory enhances dynamical complexity, ergodicity, and the emergence of hidden attractors, making fractional-order models particularly attractive for a wide range of applications.
Despite these advantages, the numerical solution of fractional-order differential equations is considerably more demanding than in the integer-order case. Each state depends on the entire history of previous states, leading to high computational and memory requirements. Numerical methods based on definitions such as Caputo, Grünwald–Letnikov (GL), or Riemann–Liouville (RL) involve convolution-like operations that are inefficient for real-time execution on general-purpose processors or microcontrollers [70].
To alleviate this burden, the short-memory principle is often employed, which assumes that the influence of distant past states becomes negligible beyond a finite time window. By truncating the memory length, the computational and storage requirements can be significantly reduced, at the cost of a controlled approximation error [25,26]. This trade-off is especially relevant in practical implementations where bounded resources are a constraint.
In this section, we validate the numerical algorithms from the previous section to characterize a family of chaotic systems. We also present numerical results for each family member, along with experimental implementation results on FPGA boards and a PRNG application.

6.1. Generalized Lorenz Family

The generalized Lorenz family consists of a 3-dimensional dynamical system given by
x ˙ = f L x .
The explicit form of (77) is
x ˙ 1 = a 11 x 1 + a 12 x 2 + d 1 x ˙ 2 = a 21 x 1 + a 22 x 2 + γ x 1 x 3 + d 2 x ˙ 3 = μ x 1 2 + δ x 2 x 1 + a 33 x 3 + d 3
where a 11 , a 12 , a 21 , a 22 , a 33 , d 1 , d 2 , d 3 , γ , δ , and  μ are parameters, and their choice allows us to obtain a different chaotic system. Table 1 lists the parameter sets that define the dynamical system family in (78) for d 1 = d 2 = 0 .
Table 1. Parameters of the generalized Lorenz family in (78) considering d 1 = d 2 = 0 .
The analysis of Family (78) was presented in [77] using the Grünwald–Letnikov (GL) derivative approach. However, the GL and Caputo derivatives have different properties; therefore, applying parameters from [77] or those associated with integer order does not guarantee that Family (78) will exhibit chaotic behavior. To characterize Family (78) with the Caputo operator, consider two key aspects:
(1) 
A system with n state variables possesses n Lyapunov exponents λ , each corresponding to a direction in state space. The largest Lyapunov exponent (LLE) quantifies the rate at which two initially close trajectories diverge or converge. If  λ < 0 , nearby trajectories converge, and the system tends toward an equilibrium or stable state. If  λ = 0 , trajectories neither converge nor diverge, as in a limit cycle. If  λ > 0 , nearby trajectories diverge while remaining bounded, as in a chaotic attractor.
(2) 
A bifurcation represents a qualitative change in system behavior when a parameter surpasses a critical value. The bifurcation diagram illustrates the transition to chaos and reveals the structure of the parameter region. A single curve in the diagram indicates that the system settles into an equilibrium or a stable fixed point. A curve that successively splits into two, four, and eight branches demonstrates period-doubling behavior. A dense cloud of points indicates chaotic behavior, where the trajectory never repeats.
The bifurcation diagram depicts the long-term states as a parameter varies, while the LLE quantifies the degree of chaos in those states. These metrics are typically plotted against the same parameter and compared. A dense cloud in the diagram corresponds to a positive LLE, whereas a single curve or periodic window corresponds to a negative or zero LLE. The consistency between these indicators strengthens the validity of numerical results, while discrepancies often indicate insufficient simulation time, unremoved transients, or numerical problems.
According to [78,79], Algorithms A1 and A2 calculate the LLE for each system in family (78). Figure 5 and Figure 6 (Algorithm A1) and Figure 7 and Figure 8 (Algorithm A2) show how the fractional order α and the short-memory window T m e m affect the LLE in each system. In the two-dimensional map of the LLE over α and T m e m , a black contour marks the level λ = 0 , the border between regular dynamics ( λ < 0 ) and chaotic regime ( λ > 0 ). For clarity, the LLE surface shows a gray plane at λ = 0 , indicating where the surface crosses from negative to positive values. In contrast to the LLE calculation, we show a 3D point cloud of the state variable x 1 against α and T m e m , with bifurcation diagrams stacked along the memory-window axis. Each horizontal slice is the bifurcation diagram for one T m e m .
Figure 5. Based on Algorithm A1, we quantitatively analyzed the Largest Lyapunov Exponent (LLE), comparing the effects of fractional order α and the memory window T m e m to assess the short-memory principle. The results correspond to Lorenz system (a–c), the Chen system (d–f), the Burke–Shaw system (g–i), and the Liu system (j–l), respectively.
Figure 6. Based on Algorithm A1, we quantitatively analyzed the Largest Lyapunov Exponent (LLE), comparing the effects of fractional order α and the memory window T m e m to assess the short-memory principle. The results correspond to Shimizu–Morioka system (a–c), the Lü system (d–f), and the Yang system (g–i), respectively.
Figure 7. Based on Algorithm A2, we quantitatively analyzed the Largest Lyapunov Exponent (LLE), comparing the effects of fractional order α and the memory window T m e m to assess the short-memory principle. The results correspond to Lorenz system (a–c), the Chen system (d–f), the Burke–Shaw system (g–i), and the Liu system (j–l), respectively.
Figure 8. Based on Algorithm A2, we quantitatively analyzed the Largest Lyapunov Exponent (LLE), comparing the effects of fractional order α and the memory window T m e m to assess the short-memory principle. The results correspond to Shimizu–Morioka system (a–c), the Lü system (d–f), and the Yang system (g–i), respectively.
In all systems, the sign of the LLE changes at a critical α that depends only weakly on T m e m once the window is long enough. For the Lorenz system, the transition under Algorithm A1 is near α ≈ 0.955 (Figure 5a–c). Chaotic behavior ( λ up to ≈0.9) appears above it. Chen and Liu have thresholds near α ≈ 0.82 (Figure 5d–f,j–l). The Chen system shows a second contour at α ≈ 1 . The Liu system has a second boundary near α ≈ 0.90 with an irregular contour. This points to alternating regular/chaotic windows rather than a single transition. Burke–Shaw has one near α ≈ 0.89–0.90 (Figure 5g–i). Lü and Yang systems (Figure 6d–i) have several vertical contours and bands at α ≈ 1 showing multiple transitions between regular and chaotic behavior. In the Shimizu–Morioka system (Figure 6a–c), the transition is more gradual, and the LLE is small (LLE < 0.1 ), with a much longer window time than in the other systems ( T m e m ≈ 10   s , α ≈ 0.91 ). The contour shows a sink in the point cloud around the transition. The results associated with Algorithm A2 (Figure 7 and Figure 8) shift to higher α : for the Lorenz system, the transition is near α ≈ 0.967 ; for Chen, it shifts to α ≈ 0.845 ; for Burke–Shaw, α ≈ 0.915 ; and, for Liu, the first boundary is near α ≈ 0.84 .
For small T m e m , the contour oscillates strongly in α . The oscillations appear as ripples in the 3D surfaces and as striped patterns in the negative-LLE region. Once T m e m exceeds approximately 2 s, the contour becomes almost vertical, and the LLE stabilizes. This indicates that a truncated memory window is enough to reproduce the dynamics, which is the central point of the short-memory principle.
The chaotic region appears as two separate blocks of points in x 1 . A gap separates them and corresponds to the attractor’s two symmetric wings. The cloud preserves its shape as T m e m increases, so the bifurcation structure does not depend on the window length for sufficiently large T m e m . Checking that the LLE map and the bifurcation diagram agree, and that both are stable for large T m e m , provides evidence that the short-memory scheme is reliable.
To determine the Lyapunov exponents and bifurcation diagrams described above, we used the parameters from Table 2 in conjunction with Algorithms A1 and A2. For all systems, we used an initial condition x ( 0 ) = ( 0.1 , 0.5 , 0.1 ) and a simulation time of 300 s to analyze the effect of 0.1 ≤ T m e m ≤ 8 s. The only exception is the Shimizu–Morioka system; due to its slow dynamics, we used a simulation time of 2500 s, with  0.1 ≤ T m e m ≤ 50 s for Algorithms A1 and A2.
Table 2. Specific parameters of System (78) with d 1 = d 2 = 0 .
The preceding analysis allows for the characterization of Family (78) modeled by Caputo Derivative (27). Each system uses the parameters in Table 2, with  h = 0.004 ( h = 0.04 for the Shimizu–Morioka system), a simulation time of 300 s ( 2500 s for the Shimizu–Morioka system), the memory window T m e m = 2 s ( T m e m = 20 s for the Shimizu–Morioka system), and the fractional dynamics governed by α = 0.97 . All systems share the same initial condition, x ( 0 ) = ( 0.1 , 0.5 , 0.1 ) . Using Algorithm A1, we obtained the results shown in Figure 9 and Figure 10, which depict the phase-plane projections ( x 1 – x 2 , x 1 – x 3 , x 2 – x 3 ) and the corresponding chaotic attractor. For Algorithm A2, we used a shorter simulation time for Chen, Burke–Shaw, and Liu ( 100 s); for Lorenz, Lü, and Yang, we used 150 s. For the Shimizu–Morioka system, we used the same parameters as in Algorithm A1. In both cases, L = T m e m h = 500 . Figure 11 and Figure 12 show the simulation results obtained with Algorithm A2.
Figure 9. Simulation results considering Algorithm A1 applied to Family (78), showing the phase plane projections and the chaotic attractor of Lorenz system (a,b), the Chen system (c,d), the Burke–Shaw system (e,f), and the Liu system (g,h).
Figure 10. Simulation results considering Algorithm A1 applied to Family (78), showing the phase plane projections and the chaotic attractor of Shimizu–Morioka system (a,b), the Lü system (c,d), and the Yang system (e,f).
Figure 11. Simulation results considering Algorithm A2 applied to Family (78), showing the phase plane projections and the chaotic attractor of Lorenz system (a,b), the Chen system (c,d), the Burke–Shaw system (e,f), and the Liu system (g,h).
Figure 12. Simulation results considering Algorithm A2 applied to Family (78), showing the phase plane projections and the chaotic attractor of Shimizu–Morioka system (a,b), the Lü system (c,d), and the Yang system (e,f).

6.2. FPGA Experiments

Field-Programmable Gate Arrays (FPGAs) offer an effective alternative because their inherent parallelism and reconfigurability suit accelerating the repetitive operations and memory accesses associated with fractional operators. Before implementing a system on an FPGA, you must analyze how its variables and parameters are represented numerically. Floating-point is the usual alternative to fixed-point, but it generally costs more in area, power consumption, and design complexity. Fixed-point arithmetic stores real numbers as scaled integers, so it maps directly onto adders and multipliers, whereas floating-point arithmetic needs operations such as exponent alignment and normalization, which add latency and hardware [80]. Comparative studies report 20–30% gains and considerable logic savings when replacing floating-point with an optimized fixed-point representation [81], and FPGA implementations of fractional-order systems based on product integration commonly adopt fixed-point formats for this reason. The cost is that the word length and scaling must be chosen carefully to avoid overflow and maintain sufficient precision, which precision-tuning and error-analysis techniques can address systematically [82,83].
To experimentally validate the proposed algorithms, the rectangular (REC) and predictor–corrector (PC) methods, based on the Caputo derivative, are implemented on FPGAs and applied to the Lorenz family models in (78), with the parameters indicated in the previous subsection, except for the integration steps. In the implementation, h = 0.004 (0.04 for Shimizu–Morioka) is used for the rectangular method, and h = 0.01 (0.1 for Shimizu–Morioka) for the predictor–corrector method. This is because the predictor–corrector method allows the use of larger integration steps without losing the stability of the algorithm or the chaotic properties of the dynamic models. Both implementations use Q1.11.20, a 32-bit signed fixed-point format with 1 sign bit, 11 integer bits and 20 fractional bits. The integer part holds the state variables and the stored vector-field evaluations without overflow in all fourteen system–method combinations evaluated. The fractional part gives a spacing of 2 − 20 ≈ 9.54 × 10 − 7 between representable values. The vector-field evaluations are the right-hand sides (RHSs) of the system equations, and they are stored for the memory calculations.
Since finite precision can change the dynamics of digitally implemented chaotic systems [84,85], the fractional part is assessed quantitatively. All seven systems are simulated with both methods, using α = 0.97 and a memory duration T m e m = 2 s, except for Shimizu–Morioka, where T m e m = 20 s. Representations Q1.11.F, with total word length W = 12 + F from 16 to 64 bits, are compared against double-precision implementations of the same finite-memory algorithms. Every comparison uses the same nominal initial conditions, parameters, timestep and memory window. The fixed-point simulations reproduce the hardware truncation and the widened intermediate arithmetic, including the quantization of initial values and stored constants.
Short-time trajectory agreement, shown in Figure 13a, is measured with the normalized root-mean-square error (NRMSE)
E traj ( Q ) = 100 ∑ n = 0 N s ∥ X n ( Q ) − X n ( D ) ∥ 2 2 ∑ n = 0 N s ∥ X n ( D ) ∥ 2 2 ,
where X n ( Q ) and X n ( D ) are the state vectors ( x n , y n , z n ) from the fixed-point and double-precision simulations at the same sampling instant, and  N s represents the final sample index. The metric expresses the RMS distance between the trajectories as a percentage of the reference trajectory’s RMS magnitude.
Figure 13. Accuracy versus fractional precision for Q1.11.F. (a) Maximum short-time NRMSE across seven systems for each method. (b) Aggregate relative L 1 error of each complete ROM bank. Errors are percentages on logarithmic axes; points denote evaluated formats and connecting lines guide the eye. Bands mark Q1.11.20 (32 bits); annotations give its largest errors across methods in (a) and coefficient banks in (b).
The comparison covered the first 1 s ( 10 s for the Shimizu–Morioka system), corresponding to 250 REC steps or 100 PC steps. This metric measures short-time agreement, including initial-state quantization and subsequent arithmetic errors. Chaotic sensitivity can amplify these perturbations and produce fluctuating trajectory differences; therefore, we did not interpret the metric as a measure of long-time attractor preservation. Figure 13a shows decreasing errors across the evaluated precisions: the maximum NRMSE among the fourteen cases decreased from 41.0 % at Q1.11.12 to 0.0649 % at Q1.11.20. Within the Q1.11.20 comparison windows, the largest instantaneous state-vector difference, normalized by the reference RMS state-vector magnitude, was 0.2811 % .
Memory-coefficient accuracy, shown in Figure 13b, was evaluated using the aggregate relative L 1 error:
E mem ( Q ) = 100 ∑ k ∈ K | w ^ k − w k | ∑ k ∈ K | w k | ,
where w k and w ^ k are the original and quantized history coefficients. These coefficients weight the contributions of past vector-field evaluations. The metric measures the total absolute coefficient discrepancy relative to the total original coefficient magnitude; it is an aggregate bank error, not the largest error of an individual coefficient. Since the hardware supports any memory length 1 ≤ M ≤ 1000 , the analysis covers the complete ROM coefficient tables instead of only the coefficients used for a particular M. Each bank stores the coefficients for lags 1–999 and one zero padding entry, which is left out of the evaluation by restricting the lags to K = { 1 , … , 999 } . REC and PC share the predictor-history coefficients, and PC also stores the interior and boundary corrector coefficients. The PC interior coefficient at lag 999 is stored but never used; it is still counted in the physical-ROM analysis because it occupies memory. At each precision, the coefficients are regenerated and rounded to the nearest representable value.
The largest aggregate error among the three banks is shown in Figure 13b to decrease from 26.7051 % at Q1.11.12 to 0.1252 % at Q1.11.20. At Q1.11.12, 796 predictor, 607 PC interior and 799 PC boundary coefficients were rounded to zero, out of 999 entries per bank. An accessed coefficient that is rounded to zero contributes nothing to the corresponding memory calculation. No nonzero coefficients were rounded to zero at Q1.11.20. This analysis covers the full supported coefficient range, whereas the trajectory accuracy and overflow results apply only to the operating memory windows specified above.
Finite-time surrogate largest Lyapunov exponent (LLE) estimates were used as supplementary dynamical diagnostics (Figure 14, with REC in panel (a) and PC in panel (b)). A tangent vector, representing an infinitesimal state perturbation, was propagated through the finite-memory recurrence using the smooth vector-field Jacobian along the simulated trajectory. After discarding the transient and a memory-window warm-up, the estimate was calculated as
λ ^ sur = 1 T meas ∑ r = 1 R ln ∥ η r − ∥ 2 δ 0 ,
where η r − is the tangent vector before renormalization, δ 0 = 1 is its prescribed norm afterward, R is the number of retained renormalization intervals, and  T meas is their total duration. Both the tangent vector and its retained RHS history were rescaled at each renormalization. The accumulated logarithmic growth measures the average perturbation expansion rate in the smooth surrogate model.
Figure 14. Finite-time smooth-surrogate LLE estimates for the seven systems: (a) REC and (b) PC, with identical vertical scales. Markers show evaluated fixed-point formats, connecting lines guide the eye, and dashed horizontal lines show double-precision references. Hollow black squares flag constant post-transient trajectories. Bands mark Q1.11.20 (32 bits). Positive surrogate estimates alone do not establish chaotic stored trajectories.
At Q1.11.20, all fourteen estimates were positive, with maximum absolute differences from double precision of 0.1391 s−1 for REC and 0.1251 s−1 for PC. Unlike the errors in Figure 13, the estimates in Figure 14 do not vary monotonically with fractional precision, and, since they omit rounding discontinuities and are not classical LLEs of the quantized map, they are taken only as supplementary information about dynamical sensitivity. Positive estimates were even obtained for some constant Shimizu–Morioka trajectories at low precision, so positivity alone does not establish chaotic behavior of the stored trajectories. Overall, Q1.11.20 is supported as a practical common 32-bit representation for the evaluated operating conditions: overflow was avoided by its integer range, and close short-time trajectory agreement and low coefficient errors were obtained with its fractional precision, without any nonzero ROM coefficient being rounded to zero. Wider formats reduced the errors further, but at the cost of longer words.
The RTL architecture shown in Figure 15 implements the fractional-order Lorenz-family systems with Caputo’s incremental rectangular algorithm (Equation (64)). Its arithmetic datapath evaluates the functions f x , f y and f z . A configuration block selects the model parameters listed in Table 2 and the precomputed integration factor C α = h α / Γ ( α + 1 ) , while a global input sets the length M of the short-memory window. The fractional order is fixed at α = 0.97 and the time step is h = 0.004 s, except for the Shimizu–Morioka system, where h = 0.04 s.
Figure 15. Simplified RTL architecture of the rectangular Caputo algorithm.
The short-memory module, shown in Figure 16, stores the previous function evaluations in a banked circular RAM. Like the rest of the datapath, it works in Q1.11.20, and intermediate products and sums keep extra bits that are rescaled and truncated only when they are stored. The depth of the memory is set directly by the number of samples M. If the memory is specified as a nominal duration T m e m , M is obtained outside the hardware from the integration step h:
M = max 1 , round T m e m h .
Figure 16. Short-memory module of the rectangular architecture.
The hardware does not perform this conversion. The selected value of M is maintained during operation, and changing M or the system requires a reset. At iteration n, the history contains m n = min ( n , M − 1 ) previous evaluations, while the current function evaluation is processed separately. The implementation supports M max = 1000 and uses 10 RAM banks of 100 words, each 96 bits wide to store the three 32-bit function evaluations. Circular addressing updates the history without shifting stored samples.
To accommodate the limited DSP resources of the DE1-SoC FPGA, a multiply–accumulate architecture evaluates the short-memory sums. Ten multiplier lanes process the history in batches of up to ten terms. A coefficient ROM supplies the weights, while bank-selection logic aligns the corresponding samples and coefficients. The same lanes are reused across batches and sequentially for the three functions, keeping the multiplier count independent of M. A reduction tree combines the ten products, and the resulting sums are accumulated in three registers. The final batch sets unused lanes to zero.
A local controller manages memory access and accumulation. The main finite-state machine (FSM) starts the short-memory calculation and updates the state register only after the historical sums are ready. At the same update edge, the held current function evaluations are written into RAM for the next numerical step. The history-validity counter is cleared during reset so that uninitialized RAM contents are ignored.
The synthesized memory capacity is determined by M max , whereas the computation time depends on the selected M. Thus, changing M ≤ M max changes the number of processed history terms without changing the allocated RAM, ROM, or multiplier resources. For 32-bit samples and coefficients, with  M max a multiple of 10, the nominal storage is
B RAM = 96 M max bits , B ROM , REC = 32 M max bits ,
giving a total of 128 M max bits. The coefficient ROM contains M max / 10 rows of 320 bits, including one unused coefficient position.
With a fully populated memory window and M ≥ 2 , each step uses M − 1 previous evaluations per function. For the pipelined controller, the interval between successive state updates is
N clk , REC = 5 M − 1 10 + 11 .
The five cycles per batch account for memory access, batch loading, and the processing of the three function sums; the additional cycles cover the pipelined function evaluation, controller sequencing, and state update. During initialization, the shorter available history m n reduces the required number of batches. At clock frequency f clk , the computation time per numerical step is
T step = N clk f clk .
The architecture was described in VHDL and synthesized using Intel Quartus Prime. The resulting RTL schematic, shown in Figure 17, illustrates the shared equation evaluator, parameter-selection logic, short-memory module, controller, and state registers.
Figure 17. Quartus-generated RTL schematic of the rectangular architecture.
On the other hand, the predictor–corrector (PC) topology described in Equation (74) extends the rectangular architecture. First, the circuit computes the predicted state x n + 1 P and subsequently the corrected state x n + 1 . The same pipelined equation evaluator is reused to calculate the nonlinear functions at the current and predicted states.
Figure 18 shows the PC architecture, and Figure 19 details the short-memory module. The history RAM retains the same 10-bank organization as REC. A shared ten-lane multiply–accumulate unit sequentially calculates the three predictor and three corrector history sums, using their respective coefficient sets. For the corrector, the coefficient associated with the oldest retained evaluation is selected separately, as required by the short-memory formulation. The same integration-factor multipliers are also reused in the predictor and corrector updates.
Figure 18. Simplified RTL architecture of the Caputo predictor–corrector algorithm.
Figure 19. Short-memory module of the predictor–corrector architecture.
A Moore FSM coordinates the evaluation of the current functions, short-memory sums, prediction, evaluation at the predicted state, and correction. The corrected state and the current function evaluations are then stored for the next step. The additional predictor registers and arithmetic increase hardware utilization, but no second ten-multiplier short-memory unit is required.
The PC coefficient ROM stores three 32-bit coefficients per history position, organized as M max / 10 rows of 960 bits. The nominal RAM storage remains 96 M max bits, while the ROM requires 96 M max bits, giving 192 M max bits in total. With a full memory window and M ≥ 2 , the pipelined PC controller requires
N clk , PC = 8 M − 1 10 + 15
clock cycles per state update. Each batch includes two memory-access/loading cycles and six cycles for the predictor and corrector history sums. The additional cycles correspond to equation evaluations and the prediction/correction updates. The Quartus-generated RTL schematic of the PC architecture is shown in Figure 20.
Figure 20. Quartus-generated RTL schematic of the predictor–corrector architecture.
Regarding resource consumption, Table 3 summarizes the Quartus Prime post-fit results for both architectures on the Cyclone V 5CSEMA5F31C6 FPGA. For a common nominal short-memory duration of T m e m = 2 s ( 20 s for the Shimizu–Morioka system), Equation (82) gives M = 500 for REC and M = 200 for PC. Once these windows are filled, Equations (84) and (86) give 261 and 175 clock cycles per state update, respectively.
Table 3. Post-fit FPGA resource utilization, estimated state-generation rates for fully populated short-memory windows, and estimated thermal power for Lorenz at 50 MHz. Percentages refer to available Cyclone V resources.
The state-generation rates are theoretical estimates calculated as
R state = F max N clk ,
using the worst-case post-fit F max and full-window latency. Each generated state vector contains the simultaneous values ( x , y , z ) = ( x 1 , x 2 , x 3 ) ; these rates describe the computational architectures rather than the external visualization hardware. Although PC requires more DSP and memory resources and has a lower F max , its larger selected integration step reduces the number of history terms required for the same nominal memory duration, yielding a higher estimated state-generation rate under the reported configurations.
The short-memory module uses 30 DSP blocks in each architecture, while the common function evaluator uses 24. The state-update datapath requires 6 DSP blocks for REC and 15 for PC. The logical memory requirements correspond to 38 and 54 physical M10K blocks, respectively, after Quartus mapping.
Power was estimated using the Quartus Power Analyzer with activity from functional simulation supplemented by vectorless estimation. These estimates correspond to a common 50 MHz clock, typical device characteristics, and a 25 °C ambient temperature; HPS power is excluded, and both estimates are classified as low confidence by Quartus. Under these configurations, PC’s estimated core dynamic power is 10.8% higher than REC’s, while its estimated total thermal power is only 1.1% higher. The smaller relative difference in total power reflects the dominant core static component, approximately 412 mW in both architectures.
Table 4 comparatively provides an overview of the proposed architectures for FPGA implementations of fractional-order dynamic systems reported in the literature. Previous work has explored various numerical and architectural strategies, including integration schemes based on rectangular and trapezoidal approximations, the Grünwald–Letnikov methods, reconfigurable implementations, and frequency-domain approximations. Taken together, these studies demonstrate the feasibility of implementing fractional-order systems in programmable hardware and of adjusting certain numerical or configuration parameters. However, the comparison also shows that implementation characteristics are not always documented consistently, particularly with regard to memory usage, clock cycles per update, maximum frequency, power consumption, and specific selection and reconfiguration mechanisms. In addition, this comparison positions the proposed work within the context of integrating diverse models, configuring short-term memory, and evaluating two numerical schemes using explicit implementation metrics. Unlike previous studies in which some of these indicators are unavailable or cannot be verified, the characterization presented here allows for a joint analysis of resource utilization, maximum frequency, update latency, and estimated power consumption. However, since the studies considered use different devices, arithmetic representations, algorithms, and evaluation conditions, these results do not allow us to conclude that the proposed architectures are universally more efficient. Their main comparative value lies in providing a reproducible characterization of two implementation alternatives and demonstrating how the choice of numerical method affects the trade-off between hardware resources and temporal performance.
Table 4. Comparative hardware analysis of the proposed FPGA implementations of fractional-order chaotic systems. NR: not reported or not verifiable from the original paper.
Figure 21 shows the experimental setup used to visualize the FPGA-generated chaotic attractors through a 16-bit digital-to-analog converter (DAC) and a digital oscilloscope.
Figure 21. Experimental setup with the DE1-SoC FPGA, 16–bit DAC, and oscilloscope.
The experimental chaotic time series of each system of the Lorenz family in (78), obtained with the parameters described previously and numerical Method (64), are presented in Figure 22 and Figure 23. The oscilloscope allows the phase plane projections to be obtained, which validate the chaotic attractors previously determined numerically. In contrast, the experimental results associated with numerical Method (74) are shown in Figure 24 and Figure 25.
Figure 22. Experimental results considering Rectangular Algorithm (64) applied to Family (78), showing the temporal series ( x 1 ( t ) , x 2 ( t ) ), ( x 1 ( t ) , x 3 ( t ) ) and the phase plane projections x 1 – x 2 , x 1 – x 3 , and x 2 – x 3 of Lorenz system (a–e), the Chen system (f–j), the Burke–Shaw system (k–o), and the Liu system (p–t).
Figure 23. Experimental results considering Rectangular Algorithm (64) applied to Family (78), showing the temporal series ( x 1 ( t ) , x 2 ( t ) ), ( x 1 ( t ) , x 3 ( t ) ) and the phase plane projections x 1 – x 2 , x 1 – x 3 , and x 2 – x 3 of Shimizu–Morioka system (a–e), the Lü system (f–j), and the Yang system (k–o).
Figure 24. Experimental results considering PC Algorithm (74) applied to Family (78), showing the temporal series ( x 1 ( t ) , x 2 ( t ) ), ( x 1 ( t ) , x 3 ( t ) ) and the phase plane projections x 1 – x 2 , x 1 – x 3 , and x 2 – x 3 of Lorenz system (a–e), the Chen system (f–j), the Burke–Shaw system (k–o), and the Liu system (p–t).
Figure 25. Experimental results considering PC Algorithm (74) applied to Family (78), showing the temporal series ( x 1 ( t ) , x 2 ( t ) ), ( x 1 ( t ) , x 3 ( t ) ) and the phase plane projections x 1 – x 2 , x 1 – x 3 , and x 2 – x 3 of Shimizu–Morioka system (a–e), the Lü system (f–j), and the Yang system (k–o).

6.3. PRNG Application

Pseudo-Random Number Generators (PRNGs) are essential components in modern cryptographic systems, where they are used to generate keys, nonces, and masks whose unpredictability directly impacts overall security. Unlike true random number generators (TRNGs), which exploit physical phenomena and are inherently non-reproducible, PRNGs are deterministic algorithms that produce reproducible sequences fully defined by an initial secret seed. This determinism makes them attractive for digital hardware, offering high throughput and easy integration, but also places strict requirements on statistical quality, period length and resistance to cryptanalytic attacks [89,90,91].
Chaotic dynamical systems have emerged as promising building blocks for PRNG design, owing to properties such as ergodicity, topological mixing and extreme sensitivity to initial conditions and parameters. These characteristics can be mapped to desirable cryptographic features like diffusion, confusion and high key sensitivity, and many chaos-based PRNGs have been shown to pass stringent statistical batteries such as NIST SP 800-22, TestU01 and ENT, as well as key-space and correlation analyses [90,92,93,94].
To further enhance randomness and enlarge the key space, several works combine multiple chaotic maps, introduce turbulence or cross-over operations between maps, or add perturbation and scrambling stages before bit extraction [90,92,94,95].
However, when chaotic systems are implemented digitally, the finite precision of arithmetic leads to orbit quantization, short periods, and the possible loss or degradation of chaos, a phenomenon that is particularly relevant for fixed-point realizations preferred in FPGA designs due to their simplicity, low resource usage, and high clock frequencies [91,96]. A variety of countermeasures have been proposed to mitigate this dynamic degradation, including the dynamic perturbation of the state, weak coupling of several maps, conservative systems with controlled repetition rates, and careful selection of fixed-point formats guided by finite-precision period analysis [90,97,98].
Within this context, chaotic PRNGs implemented with sufficient resolution on FPGA can generate long-period sequences that closely approximate their continuous-time behavior, achieving a favorable trade-off between hardware efficiency and statistical quality, and making them promising candidates for high-speed stream ciphers and lightweight security applications [99,100,101,102].
To generate pseudorandom sequences from the digitally implemented fixed-point chaotic system, a simple post-processing method is applied in this work. This approach uses a bitwise XOR operation on the least significant bits (LSBs), which typically exhibit faster variations than the most significant bits (MSBs). In the evaluated configuration, the eight LSBs of the x 1 and x 3 state variables are combined to obtain one 8-bit pseudorandom number per accepted state update:
r n = LSB 8 ( X 1 , n ) ⊕ LSB 8 ( X 3 , n ) ,
where X 1 , n and X 3 , n denote the 32-bit fixed-point representations of x 1 and x 3 at update n, respectively. For the predictor–corrector topology, extraction is performed from the corrected state. The proposed post-processing scheme is illustrated in Figure 26.
Figure 26. Method for obtaining 8-bit pseudorandom numbers from 32-bit fixed-point chaotic variables.
The PRNG evaluation considers the Lorenz system for both topologies, with fractional order α = 0.97 , parameters ( a , b , c ) = ( 12 , 1.5 , 38 ) , and common initial conditions ( x 1 ( 0 ) , x 2 ( 0 ) , x 3 ( 0 ) ) = ( 0.1 , 0.5 , 0.1 ) , quantized to Q1.11.20. The rectangular topology uses h = 0.004  s and M = 500 , whereas the predictor–corrector topology uses h = 0.01  s and M = 200 , corresponding to a common nominal short-memory duration of 2 s.
Since one 8-bit word is extracted per accepted state update, the steady-state bit rate supported by each chaotic core is
R bit = 8 f clk C update ,
where f clk is the clock frequency and C update is the number of clock cycles between accepted state updates. At 50 MHz, with the configured short-memory windows filled, the rectangular and predictor–corrector cores require 261 and 175 clock cycles per update, respectively. Table 5 summarizes the corresponding update intervals and bit rates. The predictor–corrector configuration supports an approximately 49.1 % higher rate because its larger integration step allows fewer memory samples for the same nominal memory duration, reducing the update interval despite the additional correction stage.
Table 5. Core-derived generation throughput for 8-bit output words at 50 MHz with filled short-memory windows.
Finally, the statistical quality of the proposed pseudorandom number generators is evaluated using the NIST statistical test suite. After discarding an initial transient corresponding to 30 s of model time, a total of 1 billion bits, equivalent to 125 million 8-bit numbers, is collected directly from the FPGA implementation of each topology. Each dataset is divided into 1000 consecutive sequences of 1 million bits, using the default test parameters of NIST STS 2.1.2 [103].
This suite comprises 15 statistical test families that compare the evaluated sequences against an ideal random binary source, yielding 188 subtest results. Individual sequences pass a subtest when their p-value is greater than or equal to 0.01 . At the second level, the distribution of p-values is assessed for uniformity using a minimum p-value of 10 − 4 , while the passing proportion is evaluated using the integer count thresholds implemented in STS 2.1.2, derived from the three-sigma interval. The Random Excursions and Random Excursions Variant proportions use only the eligible sequences: 594 for rectangular and 631 for predictor–corrector.
Table 6 summarizes the NIST results obtained for both topologies. For test families producing multiple outputs, the minimum uniformity p-value and the minimum passing proportion are reported separately. Both methods satisfy all acceptance checks reported by STS 2.1.2.
Table 6. Results of NIST statistical tests for rectangular and predictor–corrector topologies using 1 billion bits per method. The reported p-values assess the uniformity of individual sequence p-values. The p-value and proportion minima are computed independently across each family’s subtests.
To complement the NIST evaluation, the same binary streams are tested using the Rabbit, Alphabit and BlockAlphabit binary-file batteries of TestU01 1.2.3 [104]. BlockAlphabit is applied with block sizes 1, 2, 4, 8, 16 and 32. A reported statistic is considered suspicious when its p-value falls outside [ 0.001 , 0.999 ] . Table 7 summarizes the numbers of statistics within this interval; these counts refer to reported statistics, rather than sequence passing proportions.
Table 7. Results of the TestU01 binary-stream batteries for rectangular and predictor–corrector topologies using 1 billion bits per method.
All three tested TestU01 batteries are successfully passed by both methods, with no suspicious p-values. The reported results support the statistical quality of the proposed generators for the evaluated configurations and stream lengths; statistical testing alone does not establish cryptographic security [103].

7. Conclusions

This work combines the dynamical characterization and FPGA implementation of seven fractional-order Lorenz-family systems using Caputo-based rectangular (REC) and predictor–corrector (PC) schemes with the short-memory principle. LLE maps and bifurcation diagrams obtained by varying both the fractional order α and memory duration T m e m characterize the dynamical regimes within the investigated parameter ranges and guide the selection of finite-memory operating conditions. The effect of truncation was assessed through the consistency of these maps across T m e m , not against a full-memory reference solution.
The precision assessment supports Q1.11.20 as a practical representation for the evaluated configurations. Across the fourteen system–method combinations, fixed-point simulations produced a maximum short-time NRMSE of approximately 0.065% relative to the corresponding double-precision reference. These comparisons precede history truncation and therefore quantify finite-precision effects over the evaluated intervals. The coefficient-error assessment and supplementary smooth-surrogate LLE estimates provide additional information for selecting the arithmetic format.
We implemented separate REC and PC architectures on a Cyclone V FPGA, each supporting selection among the seven models and memory lengths from 1 to 1000 samples. After a reset, model and memory settings can be changed without modifying the HDL code or resynthesizing the design. Within each architecture, the maximum supported memory capacity determines resource allocation, while the selected memory length determines the processing workload and update latency. The hardware comparison quantifies resource utilization, timing, estimated throughput, and estimated power under the reported configurations. REC requires fewer hardware resources, whereas PC achieves a higher estimated state-generation rate because its larger selected timestep requires fewer history samples for the same nominal memory duration. Experimental phase portraits obtained through DAC-based oscilloscope measurements complement the numerical characterization.
The implementations also support a PRNG application that extracts pseudorandom bits from the state variables of the selected Lorenz-family model. We performed statistical evaluation in the Lorenz configuration for both REC and PC. The resulting streams met the acceptance criteria in NIST SP 800-22 and the Rabbit, Alphabit, and BlockAlphabit batteries of TestU01. These findings support the statistical quality of the evaluated streams under the specified conditions. Potential applications in secure communications and IoT require further cryptanalytic assessment.
The Riemann–Liouville formulation remains theoretical, since we must close a gap in the numerical analysis before we can implement and validate it on an FPGA. The proposal for the iterative method, as well as the characterization of the Lorenz family via the Riemann–Liouville derivative, remains an open problem for future study.

Author Contributions

J.A.G.-G.: Data curation, Formal analysis, Investigation, Methodology, Software, Visualization, Writing—original draft, Writing—review and editing; O.M.-F.: Conceptualization, Formal analysis, Funding acquisition, Investigation, Methodology, Project administration, Resources, Supervision, Validation, Writing—original draft, Writing—review and editing; J.M.T.-A.: Data curation, Investigation, Software, Visualization, Writing—original draft; O.G.-F.: Data curation, Formal analysis, Investigation, Software, Visualization, Writing—original draft; E.T.-C.: Project administration, Resources, Supervision, Validation, Writing—review and editing; J.d.J.R.-M.: Project administration, Resources, Supervision, Validation, Writing—review and editing. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Data Availability Statement

The raw data supporting the conclusions of this article will be made available by the authors on request.

Conflicts of Interest

The authors declare no conflicts of interest.

Appendix A. Pseudocode Listings

Algorithm A1 Incremental explicit left-rectangle product-integration algorithm with the short-memory principle
Require: Initial condition x 0 , initial time t 0 , step size h, fractional order α , requested memory duration T mem , number of iterations N, and system function f ( t , x )
 1: M ← max 1 , round T mem h ▹ Memory length in samples
 2: L ← M h ▹ Realized memory duration
 3: C α ← h α Γ ( α + 1 )
 4: // Precompute the incremental history coefficients
 5: for  j ← 1 , … , M − 1 do
 6:     c j ← ( j + 1 ) α − 2 j α + ( j − 1 ) α
 7: end for
 8: x 0 ← x ( t 0 )
 9: F 0 ← f ( t 0 , x 0 )
10: for  n ← 0 , … , N − 1   do
11:     m ← min ( n , M − 1 ) ▹ Number of retained history terms
12:     S ← F n ▹ Current contribution
13:    // Incorporate the retained fractional memory
14:    for  j ← 1 , … , m  do
15:        S ← S + c j F n − j
16:    end for
17:     x n + 1 ← x n + C α S ▹ State update
18:     t n + 1 ← t 0 + ( n + 1 ) h
19:     F n + 1 ← f ( t n + 1 , x n + 1 )
20: end for
21: return  { x 0 , x 1 , … , x N }
Algorithm A2 Incremental predictor–corrector product-integration algorithm with the short-memory principle
Require: Initial condition x 0 , initial time t 0 , step size h, fractional order α , requested memory duration T mem , number of iterations N, and system function f ( t , x )
 1: M ← max 1 , round T mem h ▹ Memory length in samples
 2: L ← M h ▹ Realized memory duration
 3: C P ← h α Γ ( α + 1 )
 4: C C ← h α Γ ( α + 2 )
 5: a 0 ← 2 α + 1 − 3
 6: // Precompute predictor coefficients
 7: for  j ← 1 , … , M + 1   do
 8:     p j ← ( j + 1 ) α − 2 j α + ( j − 1 ) α
 9: end for
10: // Precompute corrector coefficients
11: for  j ← 1 , … , M   do
12:     q j ← ( j + 2 ) α + 1 − ( j − 1 ) α + 1 − 3 ( j + 1 ) α + 1 − j α + 1
13: end for
14: for  j ← 2 , … , N − 1   do
15:     b j ← ( α − j ) ( j + 1 ) α + ( 2 j − α − 1 ) j α − ( j − 1 ) α + 1 ▹ b j = γ j ( α )
16: end for
17: x 0 ← x ( t 0 )
18: F 0 ← f ( t 0 , x 0 )
19: for  n ← 0 , … , N − 1   do
20:     m ← min ( n , M + 1 ) ▹ Predictor depth; corrector depth is m − 1 for n ≥ 2
21:    // Predictor step
22:     S P ← F n
23:    for  j ← 1 , … , m  do
24:        S P ← S P + p j F n − j
25:    end for
26:     x n + 1 P ← x n + C P S P
27:     t n + 1 ← t 0 + ( n + 1 ) h
28:    if  n < 2  then
29:        x n + 1 ← x n + 1 P ▹ Use the rectangular rule for the first two steps
30:    else
31:        F n + 1 P ← f ( t n + 1 , x n + 1 P )
32:       // Corrector step
33:        S C ← F n + 1 P + a 0 F n
34:       for  j ← 1 , … , m − 1  do
35:           S C ← S C + q j F n − j
36:       end for
37:        S C ← S C + b n F 0 ▹ Initial history term
38:        x n + 1 ← x n + C C S C
39:    end if
40:     F n + 1 ← f ( t n + 1 , x n + 1 ) ▹ Store accepted RHS only
41: end for
42: return  { x 0 , x 1 , … , x N }

Appendix B. Behavior of the Function γ n ( α )

The values that Function (68) takes as iterations are performed in the numerical method decrease until they reach zero, i.e.,
lim n → ∞ γ n ( α ) = lim n → ∞ ( n − 1 ) [ n α − ( n − 1 ) α ] + lim n → ∞ ( n − α ) [ n α − ( n + 1 ) α ] = lim n → ∞ n 2 n α − ( n − 1 ) α − ( n + 1 ) α − lim n → ∞ n α − ( n − 1 ) α − lim n → ∞ α n α − ( n + 1 ) α = 0 .
The most interesting part is that the function always takes minimal values (close to zero) starting from iteration n = 2 , as shown in Figure A1a, and continues to decline asymptotically, fulfilling that lim n → ∞ γ n ( α ) = 0 . Note that the most significant value always occurs at iteration n = 2 , i.e., γ 2 ( α ) > γ n ( α ) for all n ≥ 3 . In addition, the maximum possible value always occurs at α = 0.649824 , as shown in Figure A1b.
Figure A1. Behavior of Function (68) considering the interval 0 ≤ α ≤ 1 : (a) Function γ n ( α ) in the interval 2 ≤ n ≤ 22 , (b) Function γ 2 ( α ) to show the minimum value.

Appendix C. Modified Explicit PI-RL Algorithm

The main part of this article focuses on the analysis and digital implementation—on an FPGA—of the Lorenz family using the Caputo operator. Regarding the Riemann–Liouville case, we have made some initial progress, but it still requires validation. From Algorithm (58), for n = 0 , we obtain
x 1 = x 0 + h α Γ ( α + 1 ) f ( t 0 , x 0 ) ,
and the sample n given as x n = n α − 1 x 0 + h α ∑ k = 0 n − 1 f ( t k , x k ) Λ n − k − 1 ( α ) . Considering n ≥ 1 , it follows that
x 0 = n 1 − α x n − h α ∑ k = 0 n − 1 f ( t k , x k ) Λ n − k − 1 ( α ) .
Substituting (A2) into (58) and simplifying, note that
x n + 1 = n + 1 n α − 1 x n + h α ∑ k = 0 n − 1 f ( t k , x k ) Λ n − k ( α ) − n + 1 n α − 1 Λ n − k − 1 ( α ) + h α f ( t n , x n ) Λ 0 ( α ) .
By reducing the coefficients, we find that we can define the next coefficient as
Ψ ^ j ( β ) = ( j + 1 ) β − j β − n + 1 n β − 1 j β − ( j − 1 ) β ,
so that
x n + 1 = n + 1 n α − 1 x n + h α Γ ( α + 1 ) [ f ( t n , x n ) + ∑ k = 0 n − 1 f ( t k , x k ) Ψ ^ n − k ( α ) ] .
Finally, according to the short-memory principle, one has
x 0 = b 1 Γ ( α ) h α − 1 x 1 = x 0 + h α Γ ( α + 1 ) f ( t 0 , x 0 ) x n + 1 = n + 1 n α − 1 x n + h α Γ ( α + 1 ) f ( t n , x n ) + ∑ j = 1 ν f ( t n − j , x n − j ) Ψ ^ j ( α ) ,
with
ν = n , 1 ≤ n ≤ L L + 1 , n ≥ L + 1
Remark A1.
To implement (A4) numerically, consider three interesting situations:
(i) 
Consider the value of (57) as a finite constant, i.e., b 1 < ∞ . Since α < 1 , then α − 1 < 0 . As the simulation grid is refined and h → 0 , the value x 0 = b 1 Γ ( α ) h α − 1 → ∞ , representing the singularity at the initialization time [53]. For example, consider the FDE D R L 0 α x ( t ) = λ x ( t ) , 0 < α ≤ 1 with initial condition D R L 0 α − 1 x ( 0 + ) = b 1 < ∞ . According to (56), the corresponding integral equation has the form
x ( t ) = b 1 Γ ( α ) t α − 1 + 1 Γ ( α ) ∫ 0 t ( t − τ ) α − 1 λ x ( τ ) d τ ,
so that
x m ( t ) = b 1 Γ ( α ) t α − 1 + λ Γ ( α ) ∫ 0 t ( t − τ ) α − 1 x m − 1 ( τ ) d τ .
Taking the initial approximation as x 0 ( t ) = b 1 Γ ( α ) t α − 1 , then
x 1 ( t ) = b 1 Γ ( α ) t α − 1 + λ b 1 Γ ( α ) Γ ( α ) ∫ 0 t ( t − τ ) α − 1 τ α − 1 d τ = b 1 Γ ( α ) t α − 1 + λ b 1 Γ ( α ) Γ ( α ) t 2 α − 1 Γ ( α ) Γ ( α ) Γ ( 2 α ) = b 1 Γ ( α ) t α − 1 + λ b 1 Γ ( 2 α ) t 2 α − 1 ,
x 2 ( t ) = b 1 Γ ( α ) t α − 1 + λ Γ ( α ) b 1 Γ ( α ) ∫ 0 t ( t − τ ) α − 1 τ α − 1 d τ + λ Γ ( α ) λ b 1 Γ ( 2 α ) ∫ 0 t ( t − τ ) α − 1 τ 2 α − 1 d τ = b 1 Γ ( α ) t α − 1 + λ b 1 Γ ( 2 α ) t 2 α − 1 + λ 2 b 1 Γ ( α ) Γ ( 2 α ) t 3 α − 1 Γ ( α ) Γ ( 2 α ) Γ ( 3 α ) = b 1 t α − 1 ∑ k = 0 2 λ t α k Γ ( α k + α ) ,
and so on, so that x m ( t ) = b 1 t α − 1 ∑ k = 0 m λ t α k Γ ( α k + α ) . Finally, asymptotically, we have that x ( t ) = lim m → ∞ x m ( t ) = b 1 t α − 1 E α , α ( λ t α ) . Note how the solution exhibits a singularity at t = 0 , i.e., x ( 0 ) = lim t → 0 + x ( t ) → ∞ . Finally,
I R L 0 + 1 − α x ( t ) = b 1 Γ ( 1 − α ) ∫ 0 t ( t − τ ) − α τ α − 1 E α , α ( λ τ α ) d τ = b 1 Γ ( 1 − α ) ∑ k = 0 ∞ λ k Γ ( α k + α ) ∫ 0 t ( t − τ ) − α τ α k + α − 1 d τ = b 1 E α ( λ t α ) ,
which implies
I R L 0 + 1 − α x ( t ) | t = 0 = lim t → 0 + b 1 E α ( λ t α ) = b 1 < ∞ .
(ii) 
If x 0 = lim t → 0 + x ( t ) < ∞ is a finite constant, then
b 1 = lim t → 0 + I R L 0 + 1 − α x ( t ) = lim t → 0 + 1 Γ ( 1 − α ) ∫ 0 t ( t − τ ) − α x ( τ ) d τ .
If x ( t ) behaves like a finite constant x 0 near t = 0 , we get
b 1 = lim t → 0 + x 0 Γ ( 1 − α ) ∫ 0 t ( t − τ ) − α d τ = x 0 Γ ( 1 − α ) lim t → 0 + 1 1 − α u 1 − α | 0 t = x 0 Γ ( 2 − α ) lim t → 0 + t 1 − α = 0 .
(iii) 
The trivial situation occurs if α = 1 , so that b 1 = x 0 .
Analysis of chaotic systems: From the previous analysis, note that, for b 1 to be non-zero, the system must necessarily exhibit a singularity at initialization. If we consider chaotic systems initialized with very large x 0 values (result of the singularity and a small value h), x 1 will further amplify the singularity, causing a numerical overflow in the first iteration, unless h is chosen very carefully to avoid numerical instability. Considering the second case, we must program b 1 = 0 ; however, this forces the initial state to be the origin x 0 = 0 for any system lacking this singularity. In most chaotic systems, the origin is an equilibrium point, so the system will be trapped at the origin for all iterations, so the trajectory stays there and never reaches the attractor [77,105,106].

References

  1. Gorenflo, R.; Mainardi, F. Fractional Calculus: Integral and Differential Equations of Fractional Order. arXiv 2008, arXiv:0805.3823. [Google Scholar]
  2. David, S.; Linares, J.L.; Pallone, E. Fractional order calculus: Historical apologia, basic concepts and some applications. Rev. Bras. Ensino Fis. 2011, 33, 4302. [Google Scholar] [CrossRef] [Scilit]
  3. Ortigueira, M.; Machado, J. What is a fractional derivative? J. Comput. Phys. 2015, 293, 4–13. [Google Scholar] [CrossRef] [Scilit]
  4. Al-Mdallal, Q.; Abdeljawad, T.; Hajji, M. Theoretical and Numerical Results for Fractional Difference and Differential Equations. Discret. Dyn. Nat. Soc. 2017, 2017, 2543452. [Google Scholar] [CrossRef] [Scilit]
  5. Gutiérrez, R.; Rosário, J.M.; Machado, J. Fractional Order Calculus: Basic Concepts and Engineering Applications. Math. Probl. Eng. 2010, 2010, 375858. [Google Scholar] [CrossRef] [Scilit]
  6. Suzuki, J.; Gulian, M.A.; Zayernouri, M.; D’Elia, M. Fractional Modeling in Action: A Survey of Nonlocal Models for Subsurface Transport, Turbulent Flows, and Anomalous Materials. J. Peridynamics Nonlocal Model. 2021, 5, 392–459. [Google Scholar] [CrossRef] [Scilit]
  7. Wu, G.-C.; Deng, Z.-G.; Baleanu, D.; Zeng, D.-Q. New variable-order fractional chaotic systems for fast image encryption. Chaos 2019, 29, 083103. [Google Scholar] [CrossRef] [Scilit] [PubMed]
  8. Muñoz-Pacheco, J.; Zambrano-Serrano, E.; Volos, C.; Jafari, S.; Kengne, J.; Rajagopal, K. A New Fractional-Order Chaotic System with Different Families of Hidden and Self-Excited Attractors. Entropy 2018, 20, 564. [Google Scholar] [CrossRef] [Scilit] [PubMed]
  9. Danca, M.F. Hidden chaotic attractors in fractional-order systems. Nonlinear Dyn. 2018, 89, 577–586. [Google Scholar] [CrossRef] [Scilit]
  10. Rahman, Z.A.S.A.; Jasim, B.H. Hidden Dynamics Investigation, Fast Adaptive Synchronization, and Chaos-Based Secure Communication Scheme of a New 3D Fractional-Order Chaotic System. Inventions 2022, 7, 108. [Google Scholar] [CrossRef] [Scilit]
  11. Roohi, M.; Zhang, C.; Taheri, M.; Basse-O’Connor, A. Synchronization of Fractional-Order Delayed Neural Networks Using Dynamic-Free Adaptive Sliding Mode Control. Fractal Fract. 2023, 7, 682. [Google Scholar] [CrossRef] [Scilit]
  12. Aguirre, J.; Viana, R.; Sanjuán, M. Fractal structures in nonlinear dynamics. Rev. Mod. Phys. 2009, 81, 333–386. [Google Scholar] [CrossRef] [Scilit]
  13. Lin, H.; Deng, X.; Yu, F.; Sun, Y. Diversified Butterfly Attractors of Memristive HNN With Two Memristive Systems and Application in IoMT for Privacy Protection. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 2025, 44, 304–316. [Google Scholar] [CrossRef] [Scilit]
  14. Cattani, M.; Caldas, I.; Souza, S.D.; Iarosz, K. Deterministic Chaos Theory: Basic Concepts. Rev. Bras. Ensino Fis. 2016, 39, e1309. [Google Scholar] [CrossRef] [Scilit]
  15. Lorenz, E.N. Deterministic nonperiodic flow. J. Atmos. Sci. 1963, 20, 130–141. [Google Scholar] [CrossRef] [Scilit]
  16. Gu, Y.; Li, G.; Xu, X.; Song, X.; Wu, S. Multistable dynamics and attractors self-reproducing in a new hyperchaotic complex Lü system. Chaos 2023, 33, 093112. [Google Scholar] [CrossRef] [Scilit] [PubMed]
  17. Wang, M.; Deng, Y.; Liao, X.; Li, Z.; Ma, M.; Zeng, Y. Dynamics and circuit implementation of a four-wing memristive chaotic system with attractor rotation. Int. J. Non-Linear Mech. 2019, 111, 149–159. [Google Scholar] [CrossRef] [Scilit]
  18. Kopp, M.; Samuilik, I. A New 6D Two-wing Hyperchaotic System: Dynamical Analysis, Circuit Design, and Synchronization. Chaos Theory Appl. 2024, 6, 273–283. [Google Scholar] [CrossRef] [Scilit]
  19. Yuan, Y.; Yu, F.; Tan, B.; Huang, Y.; Yao, W.; Cai, S.; Lin, H. A class of n-D Hamiltonian conservative chaotic systems with three-terminal memristor: Modeling, dynamical analysis, and FPGA implementation. Chaos 2025, 35, 013121. [Google Scholar] [CrossRef] [Scilit] [PubMed]
  20. Grassi, G. Chaos in the Real World: Recent Applications to Communications, Computing, Distributed Sensing, Robotic Motion, Bio-Impedance Modelling and Encryption Systems. Symmetry 2021, 13, 2151. [Google Scholar] [CrossRef] [Scilit]
  21. Yu, F.; Li, L.; Tang, Q.; Cai, S.; Song, Y.; Xu, Q. A Survey on True Random Number Generators Based on Chaos. Discret. Dyn. Nat. Soc. 2019, 2019, 2545123. [Google Scholar] [CrossRef] [Scilit]
  22. Aliabadi, F.; Majidi, M.; Khorashadizadeh, S. Chaos synchronization using adaptive quantum neural networks and its application in secure communication and cryptography. Neural Comput. Appl. 2022, 34, 6521–6533. [Google Scholar] [CrossRef] [Scilit]
  23. Devi, R.P.; Khan, M.I. Comparative Analysis of Fractional Derivative Operators: Stability, Asymptotic Behavior, and Computational Challenges. Int. J. Res. Sci. Technol. 2024, 14, 13–23. [Google Scholar] [CrossRef] [Scilit]
  24. Yu, X.; Xu, H.; Mao, Z.; Sun, H.; Zhang, Y.; Zhang, D.; Chen, Y. A data-driven framework for discovering fractional differential equations in complex systems. Nonlinear Dyn. 2024, 113, 24557–24577. [Google Scholar] [CrossRef] [Scilit]
  25. Wei, Y.; Chen, Y.; Cheng, S.; Wang, Y. A note on short memory principle of fractional calculus. Fract. Calc. Appl. Anal. 2017, 20, 1382–1404. [Google Scholar] [CrossRef] [Scilit]
  26. Deng, W. Short memory principle and a predictor-corrector approach for fractional differential equations. J. Comput. Appl. Math. 2007, 206, 174–188. [Google Scholar] [CrossRef] [Scilit]
  27. Abdelaty, A.; Roshdy, M.; Said, L.; Radwan, A.G. Numerical Simulations and FPGA Implementations of Fractional-Order Systems Based on Product Integration Rules. IEEE Access 2020, 8, 102093–102105. [Google Scholar] [CrossRef] [Scilit]
  28. He, S.; Sun, K.; Wang, H. Complexity Analysis and DSP Implementation of the Fractional-Order Lorenz Hyperchaotic System. Entropy 2015, 17, 8299–8311. [Google Scholar] [CrossRef] [Scilit]
  29. Piper, J.R.; Sprott, J. Simple Autonomous Chaotic Circuits. IEEE Trans. Circuits Syst. II Express Briefs 2010, 57, 730–734. [Google Scholar] [CrossRef] [Scilit]
  30. Clemente-López, D.; Muñoz-Pacheco, J.; Rangel-Magdaleno, J. A Review of the Digital Implementation of Continuous-Time Fractional-Order Chaotic Systems Using FPGAs and Embedded Hardware. Arch. Comput. Methods Eng. 2022, 30, 951–983. [Google Scholar] [CrossRef] [Scilit]
  31. Pano-Azucena, A.; Ovilla-Martínez, B.; Tlelo-Cuautle, E.; Muñoz-Pacheco, J.; Fraga, L.G.D.L. FPGA-based implementation of different families of fractional-order chaotic oscillators applying Grünwald–Letnikov method. Commun. Nonlinear Sci. Numer. Simul. 2019, 72, 516–527. [Google Scholar] [CrossRef] [Scilit]
  32. Tolba, M.; Said, L.; Madian, A.; Radwan, A.G. FPGA Implementation of the Fractional Order Integrator/Differentiator: Two Approaches and Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 2019, 66, 1484–1495. [Google Scholar] [CrossRef]
  33. Tolba, M.; Abdelaty, A.; Soliman, N.; Said, L.; Madian, A.; Azar, A.; Radwan, A.G. FPGA implementation of two fractional order chaotic systems. AEU-Int. J. Electron. Commun. 2017, 78, 162–172. [Google Scholar] [CrossRef] [Scilit]
  34. Mohamed, S.M.; Sayed, W.; Said, L.; Radwan, A.G. Reconfigurable FPGA Realization of Fractional-Order Chaotic Systems. IEEE Access 2021, 9, 89376–89389. [Google Scholar] [CrossRef] [Scilit]
  35. Tolba, M.; Saleh, H.; Mohammad, B.; Al-Qutayri, M.; Elwakil, A.; Radwan, A.G. Enhanced FPGA realization of the fractional-order derivative and application to a variable-order chaotic system. Nonlinear Dyn. 2020, 99, 3143–3154. [Google Scholar] [CrossRef] [Scilit]
  36. Yu, F.; Zhang, W.; Xiao, X.; Yao, W.; Cai, S.; Zhang, J.; Wang, C.; Li, Y. Dynamic Analysis and Field-Programmable Gate Array Implementation of a 5D Fractional-Order Memristive Hyperchaotic System with Multiple Coexisting Attractors. Fractal Fract. 2024, 8, 271. [Google Scholar] [CrossRef] [Scilit]
  37. Yu, F.; Xu, S.; Xiao, X.; Yao, W.; Huang, Y.; Cai, S.; Li, Y. Dynamic analysis and FPGA implementation of a 5D multi-wing fractional-order memristive chaotic system with hidden attractors. Integration 2024, 96, 102129. [Google Scholar] [CrossRef] [Scilit]
  38. Yu, F.; Zhang, S.; Su, D.; Wu, Y.; Gracia, Y.M.; Yin, H. Dynamic Analysis and Implementation of FPGA for a New 4D Fractional-Order Memristive Hopfield Neural Network. Fractal Fract. 2025, 9, 115. [Google Scholar] [CrossRef] [Scilit]
  39. Clemente-López, D.; Muñoz-Pacheco, J.; Zambrano-Serrano, E.; Beltrán, O.G.F.F.; Rangel-Magdaleno, J. A Piecewise Linear Approach for Implementing Fractional-Order Multi-Scroll Chaotic Systems on ARMs and FPGAs. Fractal Fract. 2024, 8, 389. [Google Scholar] [CrossRef] [Scilit]
  40. Sayed, W.; Roshdy, M.; Said, L.; Herencsar, N.; Radwan, A.G. CORDIC-Based FPGA Realization of a Spatially Rotating Translational Fractional-Order Multi-Scroll Grid Chaotic System. Fractal Fract. 2022, 6, 432. [Google Scholar] [CrossRef] [Scilit]
  41. Mohamed, S.M.; Sayed, W.; Madian, A.; Radwan, A.G.; Said, L. An Encryption Application and FPGA Realization of a Fractional Memristive Chaotic System. Electronics 2023, 12, 1219. [Google Scholar] [CrossRef] [Scilit]
  42. Zourmba, K.; Effa, J.; Fischer, C.; Rodríguez-Muñoz, J.D.; Moreno-Lopez, M.F.; Tlelo-Cuautle, E.; de Dieu Nkapkop, J. Fractional order 1D memristive time-delay chaotic system with application to image encryption and FPGA implementation. Math. Comput. Simul. 2024, 227, 58–84. [Google Scholar] [CrossRef] [Scilit]
  43. He, S.; Yu, F.; Guo, R.; Zheng, M.; Tang, T.; Jin, J.; Wang, C. Dynamic analysis and FPGA implementation of a fractional-order memristive Hopfield neural network with hidden chaotic dual-wing attractors. Fractal Fract. 2025, 9, 561. [Google Scholar] [CrossRef] [Scilit]
  44. Samko, S.G.; Kilbas, A.A.; Marichev, O.I. Fractional Integrals and Derivatives; Gordon and Breach Science Publishers: Yverdon-les-Bains, Switzerland, 1993; Volume 1. [Google Scholar]
  45. Artin, E. The Gamma Function; Courier Dover Publications: Garden City, NY, USA, 2015. [Google Scholar]
  46. Bell, W.W. Special Functions for Scientists and Engineers; Courier Corporation: San Francisco, CA, USA, 2004. [Google Scholar]
  47. Lebedev, N.N.; Silverman, R.A.; Livhtenberg, D. Special Functions and Their Applications; Prentice-Hall: Hoboken, NJ, USA, 1965. [Google Scholar]
  48. Diethelm, K. The Analysis of Fractional Differential Equations: An Application-Oriented Exposition Using Differential Operators of Caputo Type; Springer: Berlin/Heidelberg, Germany, 2010. [Google Scholar]
  49. Cheney, E.W.; Kincaid, D.R. Numerical Mathematics and Computing, 7th ed.; Cengage Learning: Boston, MA, USA, 2013. [Google Scholar]
  50. Thomas, G.B.; Weir, M.D.; Hass, J. Thomas’ Calculus: Early Transcendentals, 12th ed.; Pearson: London, UK, 2014. [Google Scholar]
  51. He, T.X. Methods for the Summation of Series; Chapman and Hall/CRC: Boca Raton, FL, USA, 2022. [Google Scholar]
  52. Burden, R.L.; Faires, J.D. Numerical Analysis, 9th ed.; Brooks/Cole, Cengage Learning: Boston, MA, USA, 2010. [Google Scholar]
  53. Podlubny, I. Fractional Differential Equations: An Introduction to Fractional Derivatives, Fractional Differential Equations, to Methods of Their Solution and Some of Their Applications; Elsevier: Amsterdam, The Netherlands, 1998; Volume 198. [Google Scholar]
  54. Miller, K.S.; Ross, B. An Introduction to the Fractional Calculus and Fractional Differential Equations; Wiley-Interscience: Hoboken, NJ, USA, 1993. [Google Scholar]
  55. Dimov, I.; Georgieva, R.; Todorov, V. Balancing of systematic and stochastic errors in Monte Carlo algorithms for integral equations. In Proceedings of the International Conference on Numerical Methods and Applications; Springer: Cham, Switzerland, 2014; pp. 44–51. [Google Scholar]
  56. Gong, C.; Bao, W.; Liu, J. A piecewise memory principle for fractional derivatives. Fract. Calc. Appl. Anal. 2017, 20, 1010–1022. [Google Scholar] [CrossRef] [Scilit]
  57. Lovitt, W.V. Linear Integral Equations; Dover: Garden City, NY, USA, 1924. [Google Scholar]
  58. Tricomi, F.G. Integral Equations; Dover: Garden City, NY, USA, 1985. [Google Scholar]
  59. Rahman, M. Integral Equations and Their Applications; WIT Press: Southampton, UK, 2007. [Google Scholar]
  60. Garrappa, R. Trapezoidal methods for fractional differential equations: Theoretical and computational aspects. Math. Comput. Simul. 2015, 110, 96–112. [Google Scholar] [CrossRef] [Scilit]
  61. Garrappa, R. Numerical solution of fractional differential equations: A survey and a software tutorial. Mathematics 2018, 6, 16. [Google Scholar] [CrossRef] [Scilit]
  62. Li, C.; Zeng, F. Numerical Methods for Fractional Calculus; CRC Press: Boca Raton, FL, USA, 2015. [Google Scholar]
  63. Tacha, O.I.; Munoz-Pacheco, J.M.; Zambrano-Serrano, E.; Stouboulos, I.N.; Pham, V.T. Determining the chaotic behavior in a fractional-order finance system with negative parameters. Nonlinear Dyn. 2018, 94, 1303–1317. [Google Scholar] [CrossRef] [Scilit]
  64. Owolabi, K.M.; Atangana, A. Numerical Methods for Fractional Differentiation; Springer: Singapore, 2019; Volume 54. [Google Scholar]
  65. Garrappa, R.; Popolizio, M. On accurate product integration rules for linear fractional differential equations. J. Comput. Appl. Math. 2011, 235, 1085–1097. [Google Scholar] [CrossRef] [Scilit]
  66. Hildebrand, F.B. Introduction to Numerical Analysis; Courier Corporation: San Francisco, CA, USA, 1987. [Google Scholar]
  67. Diethelm, K.; Ford, N.J.; Freed, A.D. Detailed error analysis for a fractional Adams method. Numer. Algorithms 2004, 36, 31–52. [Google Scholar] [CrossRef] [Scilit]
  68. Tlelo-Cuautle, E.; Pano-Azucena, A.D.; Guillén-Fernández, O.; Silva-Juárez, A. Analog/Digital Implementation of Fractional Order Chaotic Circuits and Applications; Springer: Cham, Switzerland, 2020. [Google Scholar]
  69. He, S.; Wang, H.; Sun, K. Solutions and memory effect of fractional-order chaotic system: A review. Chin. Phys. B 2021, 31, 060501. [Google Scholar] [CrossRef] [Scilit]
  70. Matusiak, M. Optimization for Software Implementation of Fractional Calculus Numerical Methods in an Embedded System. Entropy 2020, 22, 566. [Google Scholar] [CrossRef] [Scilit] [PubMed]
  71. Zhou, T.; Tang, Y.; Chen, G. Chen’s attractor exists. Int. J. Bifurc. Chaos 2004, 14, 3167–3177. [Google Scholar] [CrossRef] [Scilit]
  72. Shaw, R. Strange attractors, chaotic behavior, and information flow. Z. Naturforschung A 1981, 36, 80–112. [Google Scholar] [CrossRef] [Scilit]
  73. Liu, C.; Liu, T.; Liu, L.; Liu, K. A new chaotic attractor. Chaos Solitons Fractals 2004, 22, 1031–1038. [Google Scholar] [CrossRef] [Scilit]
  74. Shimizu, T.; Morioka, N. On the bifurcation of a symmetric limit cycle to an asymmetric one in a simple model. Phys. Lett. A 1980, 76, 201–204. [Google Scholar] [CrossRef] [Scilit]
  75. Lü, J.; Chen, G. A new chaotic attractor coined. Int. J. Bifurc. Chaos 2002, 12, 659–661. [Google Scholar] [CrossRef] [Scilit]
  76. Yang, Q.; Chen, G. A chaotic system with one saddle and two stable node-foci. Int. J. Bifurc. Chaos 2008, 18, 1393–1414. [Google Scholar] [CrossRef] [Scilit]
  77. Petráš, I. The fractional-order Lorenz-type systems: A review. Fract. Calc. Appl. Anal. 2022, 25, 362–377. [Google Scholar] [CrossRef] [Scilit] [PubMed]
  78. Li, H.; Shen, Y.; Han, Y.; Dong, J.; Li, J. Determining Lyapunov exponents of fractional-order systems: A general method based on memory principle. Chaos Solitons Fractals 2023, 168, 113167. [Google Scholar] [CrossRef] [Scilit]
  79. Danca, M.F.; Kuznetsov, N. Matlab code for Lyapunov exponents of fractional-order systems. Int. J. Bifurc. Chaos 2018, 28, 1850067. [Google Scholar] [CrossRef] [Scilit]
  80. Winandy, I.; Dion, A.; Manni, F.; Garoche, P.L.; Khalifa, D.B.; Martel, M. Automated Fixed-Point Precision Optimization for FPGA Synthesis. IEEE Open J. Circuits Syst. 2025, 6, 192–204. [Google Scholar] [CrossRef] [Scilit]
  81. Amin-Nejad, S.; Basharkhah, K.; Gashteroodkhani, T. Floating Point versus Fixed point Tradeoffs in FPGA Implementations of QR Decomposition Algorithm. Eur. J. Electr. Eng. Comput. Sci. 2019, 3, 1–5. [Google Scholar] [CrossRef] [Scilit]
  82. Sung, W.; Kum, K.I. Simulation-based word-length optimization method for fixed-point digital signal processing systems. IEEE Trans. Signal Process. 1995, 43, 3087–3090. [Google Scholar] [CrossRef] [Scilit]
  83. Constantinides, G. Word-length optimization for differentiable nonlinear systems. ACM Trans. Des. Autom. Electron. Syst. 2006, 11, 26–43. [Google Scholar] [CrossRef] [Scilit]
  84. Wang, Q.; Yu, S.; Li, C.; Lu, J.; Fang, X.; Guyeux, C.; Bahi, J. Theoretical Design and FPGA-Based Implementation of Higher-Dimensional Digital Chaotic Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 2015, 63, 401–412. [Google Scholar] [CrossRef] [Scilit]
  85. Méndez-Ramírez, R.; Arellano-Delgado, A.; Murillo-Escobar, M.; Cruz-Hernández, C. Degradation Analysis of Chaotic Systems and their Digital Implementation in Embedded Systems. Complexity 2019, 2019, 9863982. [Google Scholar] [CrossRef] [Scilit]
  86. Sayed, W.; Roshdy, M.; Said, L.; Radwan, A.G. Chaotic Dynamics and FPGA Implementation of a Fractional-Order Chaotic System With Time Delay. IEEE Open J. Circuits Syst. 2020, 1, 255–262. [Google Scholar] [CrossRef] [Scilit]
  87. Lin, L.; Wang, Q.; Cai, G. FPGA Realization of Two Different Fractional-Order Time-Delay Chaotic System With Predefined Synchronization Time. IEEE Access 2022, 10, 133663–133672. [Google Scholar] [CrossRef] [Scilit]
  88. Perez, J.C.N.; Prieto, R.U.A.; Afolabi, O.; Pinal, F.J.P.; Valdez, M.A.E. FPGA realization of fractional-order chaotic oscillators using ABM and EFORK methods. Sci. Rep. 2026, 16, 19716. [Google Scholar] [CrossRef] [Scilit] [PubMed]
  89. Dridi, F.; Assad, S.E.; Youssef, W.H.; Machhout, M.; Samhat, A. Design, FPGA-based Implementation and Performance of a Pseudo Random Number Generator of Chaotic Sequences. Adv. Electr. Comput. Eng. 2021, 21, 41–48. [Google Scholar] [CrossRef] [Scilit]
  90. Cang, S.; Kang, Z.; Wang, Z. Pseudo-random number generator based on a generalized conservative Sprott-A system. Nonlinear Dyn. 2021, 104, 827–844. [Google Scholar] [CrossRef] [Scilit]
  91. Gomar, S.; Ahmadi, M. A Digital Pseudo Random Number Generator Based on a Chaotic Dynamic System. In 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS); IEEE: Piscataway, NJ, USA, 2019; pp. 610–613. [Google Scholar]
  92. Krishnamoorthi, S.; Jayapaul, P.; Dhanaraj, R.K.; Rajasekar, V.; Balusamy, B.; Islam, S.H. Design of pseudo-random number generator from turbulence padded chaotic map. Nonlinear Dyn. 2021, 104, 1627–1643. [Google Scholar] [CrossRef] [Scilit]
  93. Irfan, M.; Khan, M.A. Cryptographically secure pseudo-random number generation using a Robust Chaotic Tent Map: A novel approach. Cogent Eng. 2025, 12, 2558751. [Google Scholar] [CrossRef] [Scilit]
  94. Dridi, F.; Assad, S.E.; Youssef, W.E.H.; Machhout, M. Design, Hardware Implementation on FPGA and Performance Analysis of Three Chaos-Based Stream Ciphers. Fractal Fract. 2023, 7, 197. [Google Scholar] [CrossRef] [Scilit]
  95. Krishnamoorthi, S.; Jayapaul, P.; Rajasekar, V.; Dhanaraj, R.K.; Iwendi, C. A futuristic approach to generate random bit sequence using dynamic perturbed chaotic system. Turk. J. Electr. Eng. Comput. Sci. 2021, 30, 35–49. [Google Scholar] [CrossRef] [Scilit]
  96. Abderrahim, N.W.; Benmansour, F.Z.; Seddiki, O. FPGA Implementation of a Chaotic Pseudo-random Numbers Generator. SN Comput. Sci. 2023, 4, 410. [Google Scholar] [CrossRef] [Scilit]
  97. Silva, S.J.S.; Cardoso, M.B.R.; Nardo, L.; Nepomuceno, E.; Hübner, M.; Arias-Garcia, J. A New Chaos-Based PRNG Hardware Architecture Using the HUB Fixed-Point Format. IEEE Trans. Instrum. Meas. 2023, 72, 2001208. [Google Scholar] [CrossRef] [Scilit]
  98. Wang, C.; Zheng, J.; Qian, Y. Structure-Varying Complex Network Chaotic Model and Its Hardware Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. 2025, 72, 4673–4685. [Google Scholar] [CrossRef] [Scilit]
  99. Gonzalez, J.A.G.; Rangel-Magdaleno, J.; Muñoz-Pacheco, J. FPGA Implementation of a Multi-PRNG Based on a Multiscroll Chaotic Hopfield Neural Network. IEEE Trans. Ind. Inform. 2025, 21, 3097–3106. [Google Scholar] [CrossRef] [Scilit]
  100. Garcia-Bosque, M.; Pérez-Resa, A.; Sánchez-Azqueta, C.; Aldea, C.; Celma, S. Chaos-Based Bitwise Dynamical Pseudorandom Number Generator On FPGA. IEEE Trans. Instrum. Meas. 2019, 68, 291–293. [Google Scholar] [CrossRef] [Scilit]
  101. Gupta, M.; Chauhan, R. Hardware Efficient Pseudo-Random Number Generator Using Chen Chaotic System on FPGA. J. Circuits Syst. Comput. 2021, 31, 2250043. [Google Scholar] [CrossRef] [Scilit]
  102. Hadjadj, M.A.; Kaibou, R.; Sadoudi, S. Design and Hardware Implementation of a PRNG-CS for Embedded Security Applications. In 2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI); IEEE: Piscataway, NJ, USA, 2025; Volume 1, pp. 1–4. [Google Scholar]
  103. Rukhin, A.; Soto, J.; Nechvatal, J.; Smid, M.; Barker, E. A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications; Technical Report SP 800-22 Revision 1a; National Institute of Standards and Technology: Gaithersburg, MD, USA, 2010.
  104. L’Ecuyer, P.; Simard, R. TestU01: A C Library for Empirical Testing of Random Number Generators. ACM Trans. Math. Softw. 2007, 33, 22. [Google Scholar] [CrossRef] [Scilit]
  105. Sene, N.; Ndiaye, A. On Class of Fractional-Order Chaotic or Hyperchaotic Systems in the Context of the Caputo Fractional-Order Derivative. J. Math. 2020, 2020, 8815377. [Google Scholar] [CrossRef] [Scilit]
  106. Heymans, N.; Podlubny, I. Physical interpretation of initial conditions for fractional differential equations with Riemann-Liouville fractional derivatives. Rheol. Acta 2006, 45, 765–771. [Google Scholar] [CrossRef] [Scilit]
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