High Step-Up Buck–Boost Converter with Coupled Inductors ^†

Abstract

This paper presents an in-depth analysis of a non-isolated buck–boost DC–DC converter which uses coupled inductors. The converter is designed to achieve a high static conversion ratio while using a moderate number of semiconductor devices. The proposed topology, originally introduced in a former paper of the authors, under ideal operating conditions, is now evaluated taking into account non-ideal components, modeling the conduction losses of the semiconductor devices and the equivalent series resistance of the output capacitor. In order to get a regulated output voltage, closed-loop behavior is also investigated. By using the state-space modeling approach, the calculation of the converter static conversion ratio and control-to-output transfer functions is performed. Because the topology is of fourth order, a procedure for controller design is provided. A type III error amplifier is chosen, and the pole-zero placement technique is used for its design, demonstrating that the classical control strategy still works even with this fourth-order converter. Thus, a good phase margin of 62.3 degrees is achieved. The theoretical results are validated both on open-loop and closed-loop operation, in the presence of conduction losses. Furthermore, a laboratory prototype is implemented, and it validates the theoretical and simulation results. The study demonstrates that the proposed coupled inductors buck–boost converter is a good choice for step-up applications that need a large difference between input and output voltages.

1. Introduction

The rapid growth of renewable energy systems, electric vehicles (EVs), portable electronics, and DC microgrids has increased the demand for flexible and efficient power conversion interfaces. DC–DC converters are very important for setting the voltage levels, ensuring power quality, and managing energy in a wide range of circumstances and operating conditions.

Buck–boost converters [1] are a widely used class of DC–DC converters because they are capable of increasing or decreasing the input voltage depending on what the application requires. Examples include photovoltaic systems (PV) that modify under changing irradiation, battery-powered systems that charge and discharge, fuel-cell energy conversion, and electric vehicle powertrains. In these cases, the converter needs to keep the output voltage stable even when the input voltage and load conditions change a lot. It also needs the converter to be small, efficient, and not put too much stress on the components.

The conventional buck–boost topology has an output voltage that is opposite to the input voltage [2]. Many topologies [3] based on the classical buck–boost architecture have been suggested in the literature. These include switched-capacitor cells [4], switched-inductor [5,6,7,8,9], coupled inductors [10], semi-quadratic or quadratic type [11,12,13], hybrid structures [14], interleaved, transformer-based cells [15], or soft-switching buck–boost topologies.

For renewable-energy and DC microgrid applications, a single-switch, non-isolated buck–boost DC–DC converter derived from the Ćuk topology, capable of achieving a wide voltage conversion ratio with continuous input and output currents and negative output polarity, is shown in [16]. Having three inductors, four capacitors, two diodes, and one transistor, the proposed converter attains a quadratic voltage gain at moderate duty cycles while significantly reducing current stress on the active switch and improving overall efficiency. Other structures with inverted output polarity are presented in [17]. There, three fourth-order buck–boost converter topologies with continuous input and output currents providing minimum-phase behavior through reverse inductor coupling are shown.

For medium-voltage renewable-energy applications such as offshore wind farms, a modular, non-isolated hybrid interleaved DC–DC converter based on an input-parallel output-series (IPOS) structure that integrates an inverting and a non-inverting buck–boost converter to achieve high voltage gain with reduced component count is described in [18]. Interleaved PWM operation enables a significant reduction in input current ripple and output voltage ripple, while the IPOS configuration halves the voltage and current stress on power devices and passive components.

A comprehensive review of non-isolated DC–DC converter topologies frequently used in renewable energy systems, with a specific focus on photovoltaic applications, can be read from [19]. Another review regarding the state-of-the-art of unidirectional, non-isolated single-phase power factor correction (PFC) converters, presented in [20], classifies the converters into fundamental and modified topologies and evaluates them in terms of power factor, total harmonic distortion, efficiency, power rating, and voltage range for both low-voltage and high-voltage EV battery applications. Both reviews provide practical performance comparisons and design-oriented insights, offering clear guidelines for selecting suitable PFC converter topologies for short- and long-distance EV charging systems. In [21] a comprehensive review and comparative analysis of DC–DC buck–boost and boost converter topologies for integrating fuel cells (FCs) into electric vehicles and DC microgrid applications is presented. The study highlights that single-switch buck–boost converters and boost converters employing impedance networks, particularly switched-inductor configurations, offer a favorable trade-off between high voltage gain, efficiency, and suitability for FC systems, providing practical guidelines for topology selection in EV and microgrid applications.

A family of extended boosting range non-isolated buck–boost converter (NIBBC) topologies that provide continuous input current, a common grounded structure, and enhanced quadratic voltage conversion ratio, can be found in [22].

Another family of non-isolated inverting buck–boost DC–DC converters with extended step-down and step-up voltage conversion ratios, including the inverting buck²–boost converter (IB2BC) and the inverting buck–boost² converter (IBB2C), is shown in [23]. Without using transformers or coupled inductors, the proposed fourth-order converters achieve high voltage gain at moderate duty cycles, common-ground structures, low component voltage and current stress, and avoidance of capacitor voltage discontinuities.

A novel isolated buck–boost DC–DC converter capable of operating in buck, buck–boost, and boost modes while providing a wide input voltage regulation range and galvanic isolation is presented in [24]. The topology employs a current-fed structure with a three-winding high-frequency transformer and six active switches, enabling zero-voltage switching (ZVS) for all main devices across all operating modes. It demonstrates that the converter is able to provide a constant output voltage over a wide input range and is suitable for photovoltaic microconverter applications [24].

A single-switch, non-isolated buck–boost DC–DC converter featuring a quadratic voltage gain and a wide voltage conversion range is shown in [25]. The proposed topology operates in both step-up and step-down modes, shares a common ground between input and output, and requires only one active switch, resulting in simple control and gate-drive implementation. This converter can be used in renewable energy applications where solar or wind variation uncertainties are typically present. The proposed topology from [26] is a non-isolated, unidirectional buck–boost DC–DC converter employing an active switched-inductor (ASI) configuration to achieve high voltage gain with a reduced number of components. This converter ensures continuous input current, noninverting output voltage, and reduced voltage and current stress on switches and passive components. A modified buck–boost converter with a boost stage included, yielding a quadratic voltage gain in boost mode and strong step-down capability in buck mode with a low number of components, is proposed in [27]. This non-isolated buck–boost DC–DC converter achieves a wide voltage conversion range, while significantly reducing the voltage stresses on semiconductor devices and maintaining continuous input current.

In [28], the analysis and implementation of a two-stage isolated twin buck–boost DC–DC converter for electric vehicle (EV) battery charging applications is described. The architecture combines a CLLC resonant isolation stage with a twin buck–boost converter, enabling wide output voltage regulation suitable for both normal and fast charging modes while reducing voltage stress on power devices. A comparative evaluation of proportional–integral (PI) and fuzzy logic controllers (FLC) demonstrates that the FLC achieves superior dynamic performance in terms of reduced rise time, settling time, and steady-state error.

A paper review on error-reduction techniques for closed-loop buck–boost converters by comparatively analyzing classical PID, fuzzy logic control (FLC), hybrid fuzzy–PID, and model predictive control (MPC) strategies is presented in [29].

One of the main goals of all these works is to get a higher voltage gain, less voltage ripple, better efficiency, or more power density. The primary benefit of buck–boost converters that use coupled inductors is that they can get a much higher voltage conversion ratio, provided that the right duty cycle and turns ratio are chosen. Changing the turns ratio can greatly improve the converter’s ability to step up or step down while keeping the voltage stress on the semiconductor devices at a moderate level. These features make these types of converters especially suitable for applications that require high conversion ratios [30], like renewable energy systems [31,32,33], electric vehicles [34], and battery management systems [35,36,37]. Another benefit is that the usage of coupled inductors allows for improved energy transfer and causes less stress on the power switches than in the classical buck–boost converter.

In the paper [38], a wide step-up and step-down Ćuk-type converter is presented, with inverted output polarity. This converter employs coupled inductors, a reduced number of passive components, and a higher voltage gain at the same duty cycle compared to the classical Ćuk. A coupled-inductor buck–boost DC–DC converter (CIBuBoC) that achieves an ultra-wide step-up/step-down voltage conversion ratio with continuous input current, common ground, and positive output polarity is shown in [39]. By employing two simultaneously operated switches and a coupled inductor with an adjustable turns ratio, the converter provides semi-quadratic voltage gain, reduced device voltage stress, and a tunable step-up/step-down boundary. Comprehensive steady-state analysis, loss modeling, and state-space averaged small-signal modeling are presented, and the experimental results demonstrate high efficiency, low input current ripple, and superior performance compared with existing high-gain buck–boost converters for photovoltaic applications. A coupled inductor soft-switching non-isolated DC/DC converter family with double synchronous rectification can be found in [40]. By relocating the auxiliary coupled inductor branch and replacing the auxiliary diode with a synchronously controlled MOSFET, zero-voltage switching is achieved for all active switches without increasing control complexity [40]. In [41], a non-isolated, coupled-inductor-based bidirectional buck–boost DC–DC converter with high voltage gain and soft-switching capability for DC microgrid applications is described. The proposed converter’s main switches work in ZVS mode, while its auxiliary switches work in ZCS mode.

The buck–boost converter proposed in the present paper falls in the same category of coupled-inductor topologies. It was first introduced in [42], and that work focused primarily on the ideal operating conditions, providing the theoretical dc analysis, along with simulation results. That paper also includes some aspects regarding the non-ideal converter, with conduction losses considered, as well as a comparative representation of the ideal and non-ideal theoretical and simulated static conversion ratio. This makes the converter work more effectively in general, especially in step-up conditions.

The purpose of the present paper is a continuation of [42], which stopped at the simulation level, by further investigating the proposed converter and addressing a number of complementary aspects. First, a comparison of the circuit static conversion ratio with those of other step-up/step-down topologies highlights its most important features. Second, a more in-depth examination of the non-ideal converter is performed utilizing a state-space modeling approach. This allows a small-signal analysis to be performed, thus finding the control-to-output transfer function of the proposed topology and the controller to be designed. Finally, the converter is practically implemented, and the results are presented.

The comparative analysis of the converter, together with state-space matrices and how the control-to-output transfer function was obtained, is presented in Section 2. Also, the design of the type III error amplifier can be found in the same section. Section 3 presents the simulation results of the proposed converter with conduction losses considered, both in open-loop and closed-loop situations. In the same section, the practical implementation of the converter, followed by a comparison between theoretical and experimental results, is also available. The research results are discussed in Section 4, and the paper ends with the conclusions drawn in Section 5.

2. Materials and Methods

The structure of the proposed converter [42], as seen in Figure 1, contains two perfectly coupled inductors, which are traditionally modeled for analysis by an ideal transformer (IT) together with its corresponding magnetizing inductor, equal to L₁, as presented in Figure 2. The turns ratio n = $\sqrt{{\displaystyle \frac{L_2}{L_1}}}$ is presumed to be less than unity. It is also easily observed that the presence of only one transistor in the schematic allows the converter control to be performed in a simple manner, by varying only the duty cycle D value, while maintaining a constant switching frequency fs, and switching period Ts, respectively. The continuous conduction mode (CCM) operation is assumed to be valid and, therefore, the converter exhibits two topological states, as seen in Figure 3 and Figure 4. It is remarked that the conduction state of the semiconductor elements depends on the topological state.

Figure 1. The buck–boost topology proposed in [42].

Figure 2. The equivalent model of the converter [42].

Figure 3. Equivalent schematic of the proposed converter [42]—first topological state.

Figure 4. Equivalent schematic of the proposed converter [42]—second topological state.

The ideal transformer is typically characterized by two equations, as seen below:

$$\left\{\begin{array}{c}{\displaystyle \frac{v_1}{1}}={\displaystyle \frac{v_2}{n}}\\ 1·i_1+n·i_2=0\end{array}\right.$$

(1)

Performing traditional dc analysis by invoking volt-second balance and charge balance equations, the expressions of the capacitor dc voltages, inductor dc currents, and static conversion ratio M result as follows:

$$V_{C1}=\left(1+{\displaystyle \frac{D}{n}}\right)·V_g$$

(2)

$$V_{Co}=\left({\displaystyle \frac{D}{1-D}}+{\displaystyle \frac{1}{n}}·{\displaystyle \frac{D^2}{1-D}}-1\right)·V_g$$

(3)

$$M={\displaystyle \frac{D}{1-D}}+{\displaystyle \frac{1}{n}}·{\displaystyle \frac{D^2}{1-D}}-1$$

(4)

$$I_{LM}={\displaystyle \frac{D·(1+n)}{1-D}}·\left({\displaystyle \frac{D}{1-D}}+{\displaystyle \frac{1}{n}}·{\displaystyle \frac{D^2}{1-D}}-1\right)·{\displaystyle \frac{V_g}{R}}$$

(5)

$$I_{L3}=\left({\displaystyle \frac{D}{1-D}}+{\displaystyle \frac{1}{n}}·{\displaystyle \frac{D^2}{1-D}}-1\right)·{\displaystyle \frac{V_g}{R}}$$

(6)

As mentioned in [42], there are certain duty cycle limits, which depend only on the value of the turns ratio n, that define the behavior of the proposed converter. For proper operation, the duty cycle must not go below $D_{lim1}=\sqrt{n^2+n}-n$. As Equation (4) reveals, a lower turns ratio leads to a higher static conversion ratio than that of a standard buck–boost converter. Moreover, it can be demonstrated that, for a specified n, the duty cycle values exceeding $D_{lim2}={\displaystyle \frac{2n}{\sqrt{n^2+4n}+n}}$ produces a static conversion ratio that is greater than that of the buck–boost topology. Because $D_{lim2}$ decreases as n gets smaller, lower turns ratios lead to a more pronounced boosting capability. If the duty cycle is higher than $D_{lim3}=\sqrt{n^2+2n}-n$, it can be demonstrated that the static conversion ratio becomes higher than that of the classical boost converter. On the other hand, the proposed topology also has a step-down operating mode for duty cycles lower than $D_{lim4}={\displaystyle \frac{\sqrt{{9n}^2+8n}-3n}{2}}$. This means that the step-down operating region narrows as the turns ratio n gets lower. The limiting duty cycles satisfy the inequality D_lim1 < D_lim4 < D_lim2 < D_lim3.

The static conversion ratio comparison performed for several values of the turns ratio n together with the corresponding characteristics of the classical boost [2], classical buck–boost [2], quadratic buck–boost [11], MSIBB [9], CIBuBoC [39], IB2BC [23] and IBB2C [23] converters is depicted in Figure 5, Figure 6 and Figure 7. To enhance visibility of the operating regions, Figure 6 presents the characteristics with limited duty cycles between 0.25 and 0.5, and Figure 7 illustrates the duty cycle range between 0.5 and 0.99.

Figure 5. Static conversion ratio comparison—graphical representation up to M = 50.

Figure 6. Static conversion ratio comparison—graphical representation up to M = 5 and with restricted duty cycle range (D between 0.25 and 0.5).

Figure 7. Static conversion ratio comparison—graphical representation up to M = 50 and with restricted duty cycle range (D between 0.5 and 0.99).

Depending on the value of n, the buck region is different. For example, from Figure 6, it can be observed that for n = 0.1, the proposed converter operates in a step-down regime from approx. D = 0.25 to D = 0.34. This behavior classifies this topology as having the shortest buck region compared to the other converters. As the duty cycle increases (Figure 7), the proposed converter exhibits a smooth transition in conversion ratio, maintaining a predictable, strictly monotonic increasing dependence on both D and n. In this region, the proposed topology demonstrates a more pronounced step-up when the turns ratio n = 0.1 relative to the other converters, and comparable to CIBuBoC [39] when n = 0.8.

Table 1 provides a comparison between the proposed buck–boost converter and the classical boost [2], classical buck–boost [2], quadratic buck–boost [11], MSIBB [9], CIBuBoC [39], IB2BC [23], and IBB2C [23] converters.

Table 1. Comparison between different converter topologies.

Parameter	Classical Boost [2]	Classical Buck–Boost [2]	Quadratic Buck–Boost [11]	MSIBB [9]	CIBuBoC [39]	IB2BC [23]	IBB2C [23]	Proposed
Total no. of components	4	4	12	9	12	8	8	9
No. of transistors	1	1	1	3	2	2	2	1
No. of diodes	1	1	5	2	3	2	2	3
Coupled inductors	no	no	no	no	yes	no	no	yes
Order	2	2	6	4	6	4	4	4
Conversion ratio	${\displaystyle \frac{1}{1-D}}$	${\displaystyle \frac{D}{1-D}}$	${\left({\displaystyle \frac{D}{1-D}}\right)}^2$	${\displaystyle \frac{2·D}{1-D}}$	${\displaystyle \frac{(1+n)·D}{{(1-D)}^2}}$	${\displaystyle \frac{D^2}{1-D}}$	${\displaystyle \frac{D}{{(1-D)}^2}}$	${\displaystyle \frac{D^2+2·n·D-n}{n·(1-D)}}$
Inverted output	no	yes	yes	no	no	yes	yes	yes

Examining Table 1, it is clear that the advantage of the proposed topology is the need for only one active switch, similar to the classical [2] and quadratic [11] converters. This feature simplifies the control strategy and gate driver circuit when compared to topologies that employ multiple transistors. The proposed topology is a higher-order system than the classical boost [2] and buck–boost [2] converters, the same fourth order with MSIBB [9], IB2BC [23], and IBB2C [23], but lower than the quadratic [11] and CIBuBoC [39]. The proposed solution differs from the classical [2] and quadratic [11] converters in the sense that it exhibits a better conversion ratio and, typically, to buck–boost counterparts, inverted output voltage compared to the input is provided. The comparison indicates that the proposed converter maintains a good balance between circuit complexity and voltage conversion ratio.

In each converter design, the evaluation of current and voltage stresses on the transistor and diodes has a major impact on the selection of the semiconductor devices. Due to their great importance, the stresses are expressed by using (2), (3), (5), and (6):

$$I_{D1}=D·{\displaystyle \frac{I_{LM}}{n}}$$

(7)

$$V_{D1}={\displaystyle \frac{V_{Co}+V_{C1}}{n+1}}$$

(8)

$$I_{D2}=\left(1-D\right)·{\displaystyle \frac{I_{LM}}{n+1}}$$

(9)

$$V_{D2}={\displaystyle \frac{1}{n}}·V_g$$

(10)

$$I_{D3}=\left(1-D\right)·\left(I_{L3}+{\displaystyle \frac{I_{LM}}{n+1}}\right)$$

(11)

$$V_{D3}=V_g+V_{Co}+V_{C1}$$

(12)

$$I_Q=D·\left(I_{L3}+{\displaystyle \frac{I_{LM}}{n}}\right)$$

(13)

$$V_Q=V_g+V_{Co}+V_{C1}$$

(14)

In practical implementations, it usually happens that in the region where step-up converters have a high voltage gain, they exhibit a totally different behavior compared to the ideal case due to the unavoidable presence of conduction and switching losses. Therefore, since the proposed buck–boost converter has a relatively wide duty cycle range where its step-up character is prominent, the analysis of the circuit in the presence of losses is of utmost importance. The considered losses, as depicted in Figure 8, are those introduced by the on-resistance (R_on) of the transistor, the forward voltage drops of the diodes (V_D1, V_D2, V_D3), and also the one from the output capacitor (R_Co). The analysis of the lossy converter is based on the state-space approach, where the input vector is chosen to be $u={[v_g v_{D1} v_{D2} v_{D3}]}^t$, while the state vector and the output vector are $x={[i_{LM} i_{L3} v_{C1} v_{Co}]}^t$ and $y=\left[v_O\right]$ respectively. Continuous conduction mode (CCM) operation is assumed, that is, the converter cycles through two distinct topological states.

Figure 8. The proposed buck–boost converter, with losses.

Based on Figure 9, the state matrices corresponding to the first topological state are:

Figure 9. The first topological state of the proposed buck–boost converter, with conduction losses.

$$\left\{\begin{array}{c}{A}_1=\left[\begin{array}{cccc}-{\displaystyle \frac{R_{on}}{n^2·L_M}}& -{\displaystyle \frac{R_{on}}{n·L_M}}& 0& 0\\ -{\displaystyle \frac{R_{on}}{n·L_3}}& -{\displaystyle \frac{R_{on}}{L_3}}& {\displaystyle \frac{1}{L_3}}& 0\\ 0& -{\displaystyle \frac{1}{C_1}}& 0& 0\\ 0& 0& 0& -{\displaystyle \frac{1}{C_o·\left(R+R_{Co}\right)}}\end{array}\right]; E_1=\left[\begin{array}{cccc}0& 0& 0& {\displaystyle \frac{R}{R+R_{Co}}}\end{array}\right]\\ B_1=\left[\begin{array}{cccc}{\displaystyle \frac{1}{n·L_M}}& -{\displaystyle \frac{1}{n·L_M}}& 0& 0\\ 0& 0& 0& 0\\ 0& 0& 0& 0\\ 0& 0& 0& 0\end{array}\right]; F_1=\left[\begin{array}{c}0\\ 0\\ 0\\ 0\end{array}\right]\end{array}\right.$$

(15)

According to Figure 10, the resulting state matrices corresponding to the second topological state, where $R_p=R\left|\right|R_{Co}$, are:

Figure 10. The second topological state of the proposed buck–boost converter, with conduction losses.

$$\left\{\begin{array}{c}{A}_2=\left[\begin{array}{cccc}-{\displaystyle \frac{R_p}{{(n+1)}^2·L_M}}& -{\displaystyle \frac{R_p}{(n+1)·L_M}}& -{\displaystyle \frac{1}{(n+1)·L_M}}& -{\displaystyle \frac{R}{(R+R_{Co})(n+1)L_M}}\\ -{\displaystyle \frac{R_p}{(n+1)·L_3}}& -{\displaystyle \frac{R_p}{L_3}}& 0& -{\displaystyle \frac{R}{(R+R_{Co})·L_3}}\\ {\displaystyle \frac{1}{(n+1)·C_1}}& 0& 0& 0\\ {\displaystyle \frac{R}{(R+R_{Co})(n+1)C_o}}& {\displaystyle \frac{R}{C_o·\left(R+R_{Co}\right)}}& 0& -{\displaystyle \frac{1}{C_o·\left(R+R_{Co}\right)}}\end{array}\right]\\ B_2=\left[\begin{array}{cccc}0& 0& -{\displaystyle \frac{1}{(n+1)·L_M}}& -{\displaystyle \frac{1}{(n+1)·L_M}}\\ -{\displaystyle \frac{1}{L_3}}& 0& 0& -{\displaystyle \frac{1}{L_3}}\\ 0& 0& 0& 0\\ 0& 0& 0& 0\end{array}\right]\\ E_2=\left[\begin{array}{cccc}{\displaystyle \frac{1}{(n+1)·R_p}}& R_p& 0& {\displaystyle \frac{R}{R+R_{Co}}}\end{array}\right]; F_2=\left[\begin{array}{c}0\\ 0\\ 0\\ 0\end{array}\right]\end{array}\right.$$

(16)

Applying the averaging operator in order to get a dc steady-state operation, the dc value of the output vector, in this case Vo, is obtained by applying the well-known formula [2]:

$$Y=V_o=\left(F_D-E_D·{A_D}^{-1}·B_D\right)·U$$

(17)

where the matrices A_D, B_D, E_D, and F_D are:

$$\left\{\begin{array}{c}{A}_D=D·A_1+(1-D)·A_2\\ B_D=D·B_1+(1-D)·B_2\\ E_D=D·E_1+(1-D)·E_2\\ F_D=D·F_1+(1-D)·F_2\end{array}\right.$$

(18)

Equations (17) and (18) are typical for dc analysis of two state topologies, being the same for any converter. By using (17), the expression of the lossy static conversion ratio, which is the ratio between the output and input voltages (V_o/V_g), is calculated as follows:

$$M={\displaystyle \frac{V_o}{V_g}}={\displaystyle \frac{Y}{U[1]}}, where U[1]=V_g$$

(19)

Knowing the averaged state matrices, written in (18), the control-to-output transfer function of the proposed topology, denoted by G_C, is obtained after linearizing the state-space equations around a dc constant steady-state operating point. It results in:

$$G_C\left(s\right)={\displaystyle \frac{{\widehat{v}}_o}{\widehat{d}}}=E_D·{\left(s·I-A_D\right)}^{-1}·{\alpha }_D+{\beta }_D$$

(20)

where I is the fourth-order unity matrix and:

$$\left\{\begin{array}{c}{\alpha }_D=\left(A_1-A_2\right)·X+(B_1-B_2)·U\\ {\beta }_D=\left(E_1-E_2\right)·X+(F_1-F_2)·U\\ and\\ X={A_D}^{-1}·B_D·U\end{array}\right.$$

(21)

The results in (20) and (21) are well-known and general, their formalism being the same for any DC–DC CCM-operated converter. The difference is made only by the state matrices.

The converter design is performed while considering the design parameters summarized in Table 2. Using the design equations provided in [42], the resulting component values are presented in Table 3.

Table 2. Design parameters.

Parameter	Value
Input voltage Vg	12 V
Output dc voltage Vo	48 V
Output power Po	16 W
Switching frequency fS	100 kHz
Maximum peak-to-peak output voltage ripple $∆V_o$	4 Vpp

Table 3. Component values.

Component	Value
Inductor L1 (=LM)	1.281 mH
Inductor L2	267.23 μH
Inductor L3	2.371 mH
Internal capacitor C1	474 nF
Output capacitor CO	2.2 μF
Load resistor R	144 Ω
Transformer ratio n	0.4567

The 100 kHz switching frequency is chosen high enough to get a compact and small converter, but low enough such that the switching losses can be neglected compared to the conduction ones, as the analysis was performed taking into account only the conduction losses.

The transformer ratio is chosen such that the converter operates at a reasonable duty cycle. In this case, the duty cycle was chosen to be 0.6986.

The losses are given by the semiconductor devices, which are selected based on their respective current and voltage stresses. Therefore, the chosen transistor is FDP083N15A, while all of the diodes are MURF1660CT. Looking at the datasheets, the transistor on-resistance is R_on = 8.3 mΩ and the diodes forward voltage drops are V_D1 = V_D2 = V_D3 = 1.5 V. The equivalent series resistor (ESR) of the output capacitor is considered to be 50 mΩ. The inductors were manufactured in the laboratory.

Using the component values and the input-output parameters that were imposed for the design, the numerical expression of the control-to-output transfer function is determined to be:

$$G_C\left(s\right)={\displaystyle \frac{-8.688e144s^4-7.88e151s^3+1.672e156s^2-4.901e160s+7.326e164}{1.575e146s^4+5.028e149s^3+8.467e154s^2+2.536e158s+2.136e162}}$$

(22)

The poles, ${\omega }_{pc\mathrm{1,2},\mathrm{3,4}},$ and zeros, ${\omega }_{zc\mathrm{1,2},\mathrm{3,4}},$ of the control to output transfer function are:

$$\left\{\begin{array}{c}{\omega }_{pc\mathrm{1,2}}=\left(-0.0021\pm 2.2600i\right)·{10}^4 \mathrm{r}\mathrm{a}\mathrm{d}/\mathrm{s}\\ {\omega }_{pc\mathrm{3,4}}=\left(-0.1575\pm 0.4906i\right)·{10}^4 \mathrm{r}\mathrm{a}\mathrm{d}/\mathrm{s}\\ {\omega }_{zc\mathrm{1,2}}=\left(0.0022\pm 0.0233i\right)·{10}^6 \mathrm{r}\mathrm{a}\mathrm{d}/\mathrm{s}\\ {\omega }_{zc3}=-9.0909·{10}^6 \mathrm{r}\mathrm{a}\mathrm{d}/\mathrm{s}\\ {\omega }_{zc4}=0.0169·{10}^6 \mathrm{r}\mathrm{a}\mathrm{d}/\mathrm{s}\end{array}\right.$$

(23)

It can be easily seen that the control transfer function is of fourth order with two pairs of left-half plane (LHP) complex conjugate poles, one LHP zero, and three right-half plane (RHP) zeros.

To validate the analytical Expression (22) of the open-loop control-to-output transfer function obtained in MATLAB 2025a [43], the proposed converter is also simulated using the PLECS simulation tool v5.0.1 [44], which provides an AC sweep analysis functionality and generates the Bode plots of the required transfer function. The converter schematic created in PLECS is depicted in Figure 11. The Bode plots obtained from the PLECS simulation and those resulting from MATLAB are compared in Figure 12 and Figure 13, where it can be observed that both the magnitude and phase characteristics are overlaid, thus validating the theoretical considerations.

Figure 11. PLECS simulation schematic of the proposed converter.

Figure 12. Comparison between magnitude characteristics—result from transfer function (blue) and AC sweeping (dashed green).

Figure 13. Comparison between phase characteristics—result from transfer function (blue) and AC sweeping (dashed green).

In the design of the controller, the type III error amplifier is still an adequate choice despite the higher converter order. From [45], considering an ideal type III amplifier, the typical formula of its transfer function is written as follows:

$$H_{AE3}\left(s\right)={\displaystyle \frac{1}{\frac{s}{{\omega }_{UGF}}}}·{\displaystyle \frac{\left(1+\frac{s}{{\omega }_{z1}}\right)·\left(1+\frac{s}{{\omega }_{z2}}\right)}{\left(1+\frac{s}{{\omega }_{p1}}\right)·\left(1+\frac{s}{{\omega }_{p2}}\right)}}$$

(24)

The design parameters, corresponding to the error amplifier, result after invoking the use of an analytical technique based on the system poles and zeros, usually known as the pole-zero placement method. Similar to the buck–boost and boost converters, the presence of the RHP zeros restricts the cut-off frequency. As is known, the type III amplifier exhibits two LHP poles and two LHP zeros. The zeros are chosen to cancel the first two pairs of conjugate poles, ${\omega }_{pc\mathrm{1,2}}$, while one pole is equal to ${\omega }_{z4}$, and the other is placed at half of the switching frequency. The cutoff frequency of 300 Hz is chosen according to the rules provided in [45,46]. A phase margin equal to 60 degrees is adopted, and the calculation of the component values that are part of the error amplifier is performed in MATLAB [43]. The results obtained are, the notations being those of [45]:

$$\left\{\begin{array}{c}{\omega }_{UGF}=5.4968 \mathrm{r}\mathrm{a}\mathrm{d}/\mathrm{s}\\ {\omega }_{p1}=3.1416e+5 \mathrm{r}\mathrm{a}\mathrm{d}/\mathrm{s}\\ {\omega }_{p2}=3.1416e+5 \mathrm{r}\mathrm{a}\mathrm{d}/\mathrm{s}\\ {{\omega }_{z1}=\omega }_{z2}=2.2600e+4 \mathrm{r}\mathrm{a}\mathrm{d}/\mathrm{s}\end{array}\right.$$

(25)

Figure 14 illustrates the magnitude characteristic of the error amplifier for the selected parameter values, whereas Figure 15 shows its phase characteristic. The magnitude characteristic of the open-loop transfer function is shown in Figure 16, while the corresponding phase characteristic is presented in Figure 17.

Figure 14. Error amplifier—magnitude characteristic obtained in MATLAB.

Figure 15. Error amplifier—phase characteristic obtained in MATLAB.

Figure 16. Open-loop transfer function—magnitude characteristic obtained in MATLAB.

Figure 17. Open-loop transfer function—phase characteristic obtained in MATLAB.

As seen from the graphical representation above, the actual crossover frequency is 347.6279 Hz, and the resulting phase margin is 62.3304 degrees.

3. Results

The simulations of the proposed converter, as well as the experimental part, are performed while considering the design parameters mentioned above.

3.1. Simulation Results

3.1.1. Open-Loop Simulation

The lossy converter was simulated using the CASPOC 2017 package [47], and the simulation results are shown in Figure 18, Figure 19, Figure 20, Figure 21, Figure 22, Figure 23, Figure 24, Figure 25 and Figure 26. The same parameters as those adopted in the previous section are used. As a convention, the currents are represented in red, while the waveforms of the voltages are depicted in blue.

Figure 18. Converter with losses (open loop)—voltage and current corresponding to L₁.

Figure 19. Converter with losses (open loop)—voltage and current corresponding to L₂.

Figure 20. Converter with losses (open loop)—voltage and current corresponding to L₃.

Figure 21. Converter with losses (open loop)—voltage and current corresponding to C₁.

Figure 22. Converter with losses (open loop)—voltage and current corresponding to transistor Q.

Figure 23. Converter with losses (open loop)—voltage and current corresponding to diode D₁.

Figure 24. Converter with losses (open loop)—voltage and current corresponding to diode D₂.

Figure 25. Converter with losses (open loop)—voltage and current corresponding to diode D₃.

Figure 26. Converter with losses (open loop)—output voltage.

All simulations were performed with a duty cycle of 0.69891, slightly higher than the duty cycle of 0.66967 in the ideal case, as expected. It can be remarked that qualitatively, the main waveforms remain unchanged.

3.1.2. Closed-Loop Simulation

The waveforms corresponding to the proposed topology remain the same as in the case of the open-loop converter. Additionally, in the case of closed-loop simulation, the dynamic response to a step change in the input voltage is shown in Figure 27, while the load resistance is shown in Figure 28.

Figure 27. Dynamic response to step variation in the input voltage, showing the output (red) and the input (blue) voltage.

Figure 28. Dynamic response to step variation in the load resistance showing the output voltage (blue) and the output current (red).

In the simulation, for both figures, the print interval is 100 simulation time steps. In Figure 27, the input voltage changes from 12 V to 14 V–12 V–10 V–12 V. It can be observed that, following the transient intervals, the output voltage is successfully regulated to the nominal value of 12 V with moderate overshoot, as specified in the design requirements. The step changes in the load resistance, from Figure 28, show how the converter reacts when the load resistance is modified from the set value of R = 144 Ω. The load is changed from 144 Ω to 120 Ω–144 Ω–170 Ω–144 Ω–120 Ω and back to 144 Ω. The output voltage exhibits good regulation.

3.2. Experimental Results

As mentioned beforehand, the component values and design parameters specified at the beginning of Section 2 are being used not only in the simulation, but also in the experimental part. The waveforms acquired from the oscilloscope are presented in Figure 29, Figure 30, Figure 31 and Figure 32, where the transistor gate voltage is considered as a reference signal.

Figure 29. Experimental waveforms: vG—transistor gate voltage against supply ground (reference signal, acquired with attenuation of 10, represented with dark blue), vDS—transistor drain to source voltage (red).

Figure 30. Experimental waveforms: vG—transistor gate voltage against supply ground (reference signal, represented with dark blue), vL2—voltage corresponding to inductor L₂ (red).

Figure 31. Experimental waveforms: vG—transistor gate voltage against supply ground (reference signal, acquired with attenuation of 10, represented with dark blue), vL3—voltage corresponding to inductor L₃ (red), iL3—current through inductor L₃ (light blue).

Figure 32. Experimental waveforms: vG—transistor gate voltage against supply ground (reference signal, acquired with attenuation of 10, represented with dark blue), Vout—output voltage (acquired with attenuation of 10, green).

Based on the practical measurements, a comparison between the ideal static conversion ratio of the proposed converter and the one obtained from the experimental part has been performed. Figure 33 reveals that the experimental characteristic in the buck region almost overlapped the ideal one, while in the boost region, as expected, the experimental conversion ratio is below the ideal characteristic. Experimental efficiency against the output power is depicted in Figure 34. Reasonable values around 90% are obtained, with a typical drop at high-duty cycles mainly due to the transistor on-resistance.

Figure 33. Static conversion ratio—ideal (pink) and from the experiment (blue).

Figure 34. Experimental efficiency for the proposed converter.

4. Discussion

The performance of the proposed buck–boost converter, with coupled inductors, was evaluated through simulation and experiment, considering both open-loop and closed-loop operation. The proposed converter achieves a high step-up conversion ratio while maintaining stable dynamic behavior. Taking into account the conduction losses, the analysis shows that the converter still provides a high step-up static conversion ratio, and the state-space model is a realistic representation of the practical operation.

Even if the converter is a fourth-order system, the classical control design techniques can be used, without compromising stability. A type III error amplifier was designed using the classical pole-zero placement method, and the simulation results demonstrated that the proposed control strategy is a good choice, with the system being stable and predictable even when changes in the input voltage or load resistance appear.

5. Conclusions

This paper presented an extensive investigation of a fourth-order DC–DC converter, employing coupled inductors, focusing on its analysis when conduction losses and ESR for the output capacitor are taken into account. Starting from steady state and small-signal analysis, the control-to-output transfer function was derived using a matrix-based state-space approach that considers the mentioned losses. The results from MATLAB and PLECS validate the theoretical study. Using the classical pole-zero placement method, a type III error amplifier was successfully designed, and the closed-loop response shows that the system is stable, with a good phase margin and good response to changes in the input voltage and output load. The applications where this converter can be used include energy harvesting systems, power conditioning for sensor nodes, IoT, and, in general, all the applications requiring conversions with a large step-up.