Review Reports

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The proposed architecture adds a Fault Data Transmission Controller, a Previous Result Register, a 128-to-7 priority encoder, a 7-to-128 decoder, selected-bit clear logic, and an index shift register (Figures 2, 5, 6). For a testability paper, the added silicon area, power, and any impact on the critical path or DA-port timing are essential to judge practicality, especially since this logic sits on the base die alongside the comparator. Please report at least a gate-count/area estimate (e.g., from a logic synthesis run) and note whether the added combinational logic (priority encoder, OR trees) affects the achievable clock frequency.

The model targets a single HBM2 channel (Table 1), but real HBM devices operate with 8–16 channels, potentially tested in parallel through shared or per-channel DA resources. A brief discussion (or additional simulation) of how the proposed controller and duplicate/index logic would scale, in area and in contention for the DA path, when multiple channels are tested concurrently would improve the paper's applicability claims.

Author Response

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Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

To substantiate the technical soundness and practical viability of the manuscript, the authors must provide a rigorous hardware-level evaluation and further justify their experimental assumptions.

Specifically, relying solely on a C-based cycle-accurate simulation is insufficient for a hardware architecture proposal; the authors should present RTL synthesis results (e.g., ASIC or FPGA implementation) detailing the gate count, silicon area overhead on the HBM Base Die, power consumption, and impact on maximum operating frequency (fmax ).

Furthermore, the authors need to justify the evaluated fault rates (5% to 25%), which are excessively high compared to realistic post-manufacturing memory test scenarios where defect rates are significantly lower.

Lastly, to demonstrate true novelty, the proposed scheme should be benchmarked against existing state-of-the-art fail-data compression and collection techniques rather than exclusively comparing it to raw, uncompressed transmission.

Author Response

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Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

Reducing Test Response Volume and Test Time in Direct-Access-Based High-Bandwidth Memory Testing

2026/09/24

Reviewer Comments

This paper proposes three fault-data transfer optimization methods. These three methods complement one another by tackling fault-free responses, repeated fault responses, and sparse fault responses. By improving the utilization efficiency of the bandwidth-constrained DA path, the proposed approach effectively lowers both test time and cost for high-bandwidth memory testing. However, several areas require further clarification and refinement before the manuscript can be considered for publication. Addressing the following points will significantly enhance the overall quality and impact of the paper.

Some suggestions that can improve the quality of the paper:

(1)What are the advantages and disadvantages of the proposed method (three fault-data transfer optimization methods)? How does this technique effectively reduce the time and cost of HBM testing compared to others? Please include a comparative analysis.

(2)Overall, we see a lot of tables. If possible, some of the results can be presented as graphs. 

(3)How can the authors prove the effectiveness of the proposed method?  A comparative summary table showing performance differences would help. Furthermore, the authors should provide some comparison graphs of the results.

(4)References must be formatted according to the journal's standard. Moreover, it is advisable to include more literature sources on the areas of research.

(5) In the final section, "5. Conclusions," to improve ease of use, I propose a minor adjustment to the text layout so that it briefly summarizes the entire study. Finally, directions for further research should be included in the conclusion.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 3 Report

Comments and Suggestions for Authors

The authors have addressed all the comments raised previously, and the article may be accepted for publication.