Review Reports

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The manuscript presents a useful experimental demonstration of a CMOS-integrated 32×8 1T1R memristive crossbar, with encouraging multilevel retention, endurance, and hardware-based pattern classification results. The paper has a useful experimental contribution, particularly because the 256-cell array is actually fabricated and a small hardware classification experiment is demonstrated. However, from my side, several points should be clarified to better support the claims about in-memory computing and practical neuromorphic applications, as follows:  
1. The manuscript presents a 32×8 1T1R array with 256 cells, but similar memristive crossbar arrays have already been reported. Explain more explicitly what the main technical novelty is compared with previous CMOS-integrated 1T1R arrays in the introduction section.

2. It would be useful to explain why a 32×8 architecture was selected and what advantages it provides in terms of area, routing, scalability, and peripheral circuitry. 

3.  The manuscript states that the crossbar occupies 25 mm² on the chip, but the active memristor area is only 10×10 μm². Please provide the area breakdown of the memristor, NMOS selector, interconnects, and peripheral circuitry and calculate the effective cell density. 

4. Reporting failure statistics would make the endurance claim stronger. 

5. Improve your literature review by adding new studies in line with your paper, such as DOI: 10.1002/aisy.202500806 and DOI: 10.1002/smm2.70032.

6.  Only a 4×2 section of the array is used to classify the two binary patterns 1010 and 0101. Discuss more clearly what prevents the full 32×8 array from being used in a larger hardware demonstration. 

7. The manuscript uses a 70 μA demarcation line to distinguish the two classes. Explain how this threshold was selected.

8. The paper uses 16 resistive states, corresponding to 4-bit representation, but the exact mapping from neural-network weights to conductance values should be described more clearly. Also explain how negative weights are represented, since a single memristive conductance is intrinsically non-negative.

9. The MNIST experiment is primarily a simulation rather than a full-chip demonstration. The manuscript should make this distinction clearer. 

10.  The authors use an ImageNet-pretrained ResNet-18 and train only the final 512×10 layer. Explain why this configuration was selected and discuss how representative it is of a complete memristive accelerator.

Author Response

Thank you very much for taking the time to review this manuscript. Please find the detailed responses in the attached PDF file; the corresponding changes in the revised manuscript and the revised supplementary materials are highlighted in red.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

This manuscript presents a 32×8 1T1R memristive crossbar array, based on which a simple hardware neural network is constructed for the binary classification of signal patterns. Furthermore, the experimental data are extend to a large neural network for classifying images from the Canadian Institute for Advanced Research 10-classes (CIFAR-10) dataset. This study is interesting and can be considered for publication in Electronics following appropriate revisions. 

• Regarding the developed 32×8 memristive crossbar array, the authors are required to investigate the device-to-device variations.
• As illustrated in Fig. 4, the device exhibits highly nonliear synaptic potentiation and depression behaviors that severely deteriorate computing accuracy. The authors are advised to include a detailed discussion on feasible strategies to improve the linearity of synaptic weight modulation .
• In the Introduction, to help readers comprehensively understand the research background, the authors are suggested to provide a brief discussion on typical resistive switching mechanisms including filamentary switching (e.g., 10.1002/adma.200900375) and purely electronic switching (e.g., 10.1002/adfm.202005582).

Author Response

Thank you very much for taking the time to review this manuscript. Please find the detailed responses in the attached PDF file; the corresponding changes in the revised manuscript and the revised supplementary materials are highlighted in red.

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

This manuscript presents a comprehensive study on a 32×8 1T1R memristive crossbar array for in-memory computing applications. The topic is highly relevant to the development of energy-efficient neuromorphic hardware, and the integration of memristive devices with CMOS technology provides meaningful practical value. The authors have systematically investigated the device fabrication, structural characterization, electrical properties, multilevel storage capability, endurance, and neural network demonstration. The experimental results are interesting and demonstrate the potential of the proposed architecture for hardware artificial intelligence applications. However, some aspects of the manuscript require further improvement in terms of presentation, discussion depth, and logical consistency to enhance the overall quality and impact of the work. Therefore, the manuscript can be considered for publication after major revision.

 

1. The authors demonstrated a 32×8 1T1R crossbar array using ZrO₂(Y)-based memristive devices. Could the authors further discuss the scalability of this architecture toward larger arrays and the possible challenges during high-density integration?
2. The device shows excellent endurance and multilevel resistance states. Could the authors provide more discussion about the uniformity of device performance across the whole array and the possible influence of device-to-device variation?
3. The neural network demonstration mainly focuses on classification tasks using MNIST and CIFAR-10 datasets. Could the authors discuss the potential advantages of the proposed hardware compared with conventional digital computing platforms?
4. The crossbar array adopts a 1T1R structure to suppress sneak current effects. Could the authors further explain the additional area and energy costs introduced by transistor selectors in practical large-scale applications?
5. The memristive devices exhibit promising retention and switching characteristics. Could the authors discuss the long-term reliability of the devices under different environmental conditions, such as temperature variation and repeated programming operations?
6. The authors are encouraged to cite recent advances in stimulus-responsive memristive devices for neuromorphic sensing and in-sensor computing, such as the humidity-gated memristive dynamics enabling near-sensor spiking computation (DOI: 10.1002/adma.202518105), to better highlight the emerging trend of sensing–memory–computing integration.

Author Response

Thank you very much for taking the time to review this manuscript. Please find the detailed responses in the attached PDF file; the corresponding changes in the revised manuscript and the revised supplementary materials are highlighted in red.

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

Comments and Suggestions for Authors

The revised manuscript has been greatly enhanced by addressing my concerns. Consequently, I recommend acceptance.

Reviewer 3 Report

Comments and Suggestions for Authors

The authors have satisfactorily addressed all of my previous questions and concerns. I am satisfied with the revisions made to the manuscript. Therefore, I agree to recommend this manuscript for acceptance in its current version.