Impact of Physical and Material Parameters on the Threshold Voltage and the Channel Resistance of Nanowire Field-Effect Transistors for Advanced Nanoscale Devices

Abstract

This work studies the impact of different physical and material parameters on the channel resistance, $R_{ch}$, and threshold voltage, $V_{th}$, of nanowire field-effect transistors (NWFETs). In particular, by means of detailed numerical simulations, we investigate the role of the channel length, nanowire diameter, gate oxide thickness, channel-doping concentration, energy bandgap, oxide thickness, and gate oxide permittivity in a wide range of temperatures (200–500 K). Our findings show that optimal values for both $R_{ch}$ and $V_{th}$ are achieved by reducing the nanowire channel length, as well as by increasing the nanowire diameter and doping concentration. Furthermore, NWFETs benefit from using wide-bandgap materials and thinner oxide layers with a higher permittivity. Notably, in short-channel NWFETs operating under ballistic transport, channel resistance remains nearly constant with temperature, governed by quantum conductance and injection statistics rather than temperature-sensitive scattering. These results underscore the complex interplay between material selection, doping levels, and device geometry in shaping the threshold voltage and the channel resistance of NWFETs. Also, they are useful for enhancing the device stability and advancing the design of NWFETs for the next-generation of nanoscale transistors.

1. Introduction

Representing a significant development in semiconductor device structure, nanowire field-effect transistors (NWFETs) suggest one-dimensional nanowires as the channel material, replacing the planar systems defined in conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). These devices are widely recognized as potential candidates for future electronics, offering improved electrostatic control, scalability, and compatibility with high-density integration.

The threshold voltage, $V_{th}$, in NWFETs plays a crucial role in determining the device performance, power consumption, and overall reliability. It refers to the minimum gate voltage required to establish a conductive channel between the source and the drain terminals. Once the gate voltage surpasses $V_{th}$, the transistor switches from the off state (non-conductive) to the on state (conductive), allowing the current to flow. A lower $V_{th}$ can improve the switching speed, thus enabling faster operation in digital circuits. Several factors influence the threshold voltage in NWFETs, including the nanowire diameter, doping concentration, intrinsic carrier concentration, effective mass, temperature, energy bandgap, gate oxide permittivity, and oxide thickness. These parameters collectively determine the effective device behavior and stability, making the study of $V_{th}$ crucial for optimizing the device’s performance.

Starting from previous results reported in the literature, we can state that increasing the nanowire diameter of silicon-based NWFETs causes a shift in the threshold voltage, with an improvement in the gate coupling [1]. Similarly, in silver-doped zinc-oxide NWFETs, the threshold voltage shifts to lower negative values as the nanowire diameter increases, although other electrical properties remain unchanged [2]. In cadmium selenide NWFETs, growth in the grain diameter through treatment affects the threshold voltage, suggesting that larger diameters improve electrical performance by minimizing defects and enhancing the electrical properties of the crystal [3,4]. For junctionless NWFETs, precise doping techniques allow for a tunable $V_{th}$, making them ideal for specific applications. For example, in organic FETs, surface doping results in a positive shift of the threshold voltage [5], while chemical doping in carbon nanotube FETs improves flexibility and the overall device performance [6]. Similarly, in silicon-doped hafnium-oxide ferroelectric FETs, accelerated doping modifies polarization, leading to an effective threshold voltage shift [7]. Moreover, a gate-all-around (GAA) design enhances the device performance by reducing the impact of random dopant fluctuations [8]. Finally, in Si_xGe_1−x NWFETs, the tight-binding band structure reveals that the effective mass and the metal gate granularity significantly affect the device threshold voltage [9,10].

In a semiconductor device, the intrinsic carrier concentration, $n_i$, increases with a rising temperature and, depending on the material bandgap, $E_g$, more electrons can transition from the valence band to the conduction band. Devices based on materials with a lower $n_i$, such as GaN and SiC, compared to silicon, exhibit a higher and more stable $V_{th}$ due to a reduced number of thermally generated carriers. Also, they require more energy for electron transitions. Advances in nanostructuring have shown potential for controlling$n_i$ and enhancing a device’s stability [11]. For example, the use of NWFETs in bio-sensing applications enables the detection of DNA traces for precise intrinsic carrier concentration values [12,13].

As the temperature increases, $V_{th}$ decreases because of a rising $n_i$ and bandgap narrowing. For instance, in ZnO NWFETs, a temperature increase from 323 K to 363 K causes a significant $V_{th}$ shift of −6.5 V, attributed to thermally activated electrons released from traps with an activation energy of 1.432 eV [5,14]. Studies reveal that material-specific effects, including phonon and surface scattering, reduce mobility and contribute to the $V_{th}$ shifts [15,16]. In addition, in single-walled carbon nanotube FETs, the bandgap reduction enhances the carrier injection and reduces the short-channel effects, influencing $V_{th}$ indirectly [17,18]. Also, in β-Ga₂O₃ nanobelts, with a wide bandgap of ~4.85 eV, high-energy proton irradiation causes a positive $V_{th}$ shift, underscoring the bandgap’s role in determining the impact of external factors on the $V_{th}$ [19,20]. Not only that, but the material choice also plays a key role. For instance, ozone treatment in ZnO NWFETs induces significant $V_{th}$ shifts, demonstrating the influence of the oxide properties [21].

The overall impact of the oxide capacitance on $V_{th}$ varies across architectures and conditions, necessitating accurate exploration in diverse material systems. In fact, increasing the oxide thickness shifts the $V_{th}$ by reducing the gate capacitance, requiring higher voltages to achieve the same electric field [22]. Conversely, thinner oxides improve the drive current, reduce leakage, and enhance switching speed and transconductance due to a better electrostatic control and mitigated short-channel effects [23,24]. Several studies reveal that oxide material properties influence $V_{th}$ significantly [25,26,27]. For example, indium oxide (In₂O₃) functionalized with Ag nanoparticles tunes $V_{th}$ from −6.9 V to +7 V [25]. In zinc-oxide devices, gate-bias stress induces $V_{th}$ instability due to charge trapping at the ZnO–dielectric interface, highlighting the effect of permittivity on charge dynamics [21].

NWFETs exhibit a performance that is heavily influenced by factors such as the material composition and geometric parameters. These elements play a key role in shaping the channel resistance, which directly impacts the overall device performance. Silicon nanowires (SiNWs) have been the focus of extensive research due to their compatibility with established CMOS technology. Studies showed that SiNWs can help to reduce drain-induced barrier lowering (DIBL) and subthreshold swing (SS) compared to conventional MOSFETs, positioning them as an ideal choice for high-density integrated circuits [28]. Additionally, incorporating SiNWs in GAA configurations enhances the device performance by improving the gate control and minimizing the short-channel effects (SCEs) [29]. Germanium–tin (GeSn) nanowires have attracted interest for their high mobility and low effective mass, offering advantages for long-channel transistors. However, if transistor dimensions shrink below 10 nm, source-to-drain tunneling (SDT) emerges as a major limitation [30]. Silicon–germanium (SiGe) nanowires are also being investigated for their potential in tunnel field-effect transistors (TFETs). By utilizing low-bandgap SiGe in the source region, along with high-k dielectrics at the source–channel interface, the device performance significantly improves, making it a promising option for low-power applications. Simulations with different diameters and channel lengths reveal that smaller diameters enhance the band-to-band tunneling in weak conduction regimes, while larger diameters are more effective in strong conduction regimes [31].

The channel length and diameter of NWFETs significantly affect device performance. To effectively reduce the SCEs and DIBL effects in the structure, shorter channel lengths and smaller diameters are preferred. Additionally, minimizing the diameter of SiNWs enhances the suppression of SCEs and improves electrostatic control. Also, physical parameters such as doping concentration and vacancy defects in SiNWs play crucial roles in shaping their band structure and transport characteristics [32].

In our research, we explored the complex interplay of various factors that influence the threshold voltage and the channel resistance of NWFETs. Unlike previous studies that typically focused on one or two parameters, our study takes a broader approach. We discovered that shortening the nanowire channel lengths and increasing the doping concentrations significantly increase (in modulo) the threshold voltage by improving the gate control and boosting the carrier density. Also, we found that larger nanowire diameters further contribute to higher threshold voltages, as well as that employing higher oxide capacitances enables better gate modulations. At the same time, short-channel devices exhibit a lower resistance with an almost stable profile. Moreover, devices with higher doping concentrations exhibit lower resistance and reduced sensitivity to temperature. Finally, wide-bandgap materials lead to superior results and improve a device’s stability with temperature, thus making it well suited for high-power and high-temperature applications.

By investigating the combined impact of different technology parameters on two fundamental device figures of merit (i.e., $V_{th}$ and $R_{ch}$), this study provides valuable insights for advancing the design of more reliable NWFETs.

2. Device Modeling

Figure 1 presents the geometric configuration of a cylindrical NWFET, which is similar to an MOSFET design. However, in the NWFET’s structure, a semiconductor nanowire replaces the conductive channel typically found in an MOSFET.

Figure 1. The cylindrical gate-all-around nanowire field-effect transistor (NWFET) considered in this work.

In this unique device, an oxide layer is introduced as a dielectric separating the channel from the gate electrode. The nanowire is contacted at both ends by metal electrodes, designated as the source and drain regions. By applying a drain-to-source voltage, $V_{ds}$, and simultaneously varying the gate-to-source voltage, $V_{gs}$, an electric field is established to modulate the channel conductance. The resulting drain current, $I_{ds}$, was measured as a function of both $V_{ds}$ and $V_{gs}$ to provide insight into the device’s electrical behavior. The equivalent circuit of the device can be schematized as in Figure 2.

Figure 2. NWFET equivalent circuit with series resistances.

The threshold voltage of an NWFET represents the minimum gate voltage required to induce a conductive inversion layer along the nanowire channel. This critical parameter is influenced by several device-specific and material-dependent factors, including the fixed positive charge on the gate electrode, dielectric permittivity of the nanowire material, flat-band voltage, gate oxide thickness, and channel-doping concentration. A recent analytical expression for the threshold voltage of an NWFET is in the form shown in the following [33]:

$$V_{th}={\varphi }_M-{\varphi }_{nw}+{\displaystyle \frac{k_{B}T}{q}}ln\left({\displaystyle \frac{{8k}_{B}T{\epsilon }_{nw}}{q^2{n}_i}}\right)-{\displaystyle \frac{2K_{B}T}{q}}ln\left[R_{nw}{\left({\displaystyle \frac{1+t_{ox}}{R_{nw}}}\right)}^{{\displaystyle \frac{2{\epsilon }_{nw}}{{\epsilon }_{ox}}}}\right]$$

(1)

where the intrinsic carrier concentration is modeled as follows:

$$n_i=5.2\times {10}^{15}{T}^{\raisebox{1ex}{$3$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}exp\left({\displaystyle \frac{-E_g}{2k_{B}T}}\right).$$

(2)

By considering the cylindrical geometry of the gate oxide, the oxide capacitance per unit length ($C_{ox}$) for a core–shell NWFET structure can be expressed as follows [34]:

$$C_{ox}={\displaystyle \frac{2\pi {\epsilon }_{ox}}{ln\left(\frac{R_{nw}+t_{ox}}{R_{nw}}\right)}}$$

(3)

where ${\epsilon }_{ox}={\epsilon }_0{\epsilon }_r$ is the permittivity of the oxide, $R_{nw}$ is the radius of the nanowire channel, $t_{ox}$ is the oxide thickness, ${\epsilon }_0$ is the vacuum permittivity, and ${\epsilon }_r$ is the relative permittivity of the oxide.

For a nanowire semiconductor, the nanowire potential (calculated in volts) is given by the following:

$${\varphi }_{nw}={\displaystyle \frac{k_{B}T}{q}}ln\left({\displaystyle \frac{N_{ch}}{n_i}}\right)$$

(4)

where $k$ is the Boltzmann constant (1.38 × 10⁻²³ J/K), $T$ is the absolute temperature$, q$ is the elementary charge (1.602 × 10⁻¹⁹ C), $N_{ch}$ is the channel-doping concentration, and $n_i$ is the intrinsic carrier concentration.

3. Contact Resistance in NWFETs

The metal–semiconductor contact is one of the main elements of a semiconductor device. Two types of metal–semiconductor contacts are known, namely, Schottky and ohmic contacts [34]. When a Schottky barrier (SB) is formed at an interface, the charge injection can be realized in the following two ways: thermionic emission and/or field emission (tunneling). On the other hand, ohmic contacts have linear and symmetrical I-V characteristics and a negligible contact resistance [35].

To make high-performance devices, a good ohmic contact between the electrode and the semiconductor layer is required to inject the maximum current density across the contact. To create ohmic contacts, we can increase the semiconductor doping level or decrease the barrier height. Ohmic contacts also require electrodes with high and low work functions to inject holes and electrons, respectively, where the work function is the minimum energy required to remove an electron from the electrode’s Fermi level to the vacuum level [36]. Therefore, reducing the SB height when realizing ohmic contacts is essential to minimize the contact resistance and maximize the carrier injection efficiency, thus accurately improving the channel mobility, low-voltage driving, and high-frequency operation characteristics of devices. In conventional bulk NWFETs, the total resistance, $R_{Total}$, includes the following two components: series resistance, $R_{sd}$, and channel resistance, $R_{ch}$. The series resistance, $R_{sd}$, is an important factor for NWFETs. As the channel length scales down, the channel resistance becomes smaller and, therefore, it becomes more important to keep ${\mathrm{R}}_{\mathrm{s}\mathrm{d}}$ much smaller than $R_{ch}$. In this context, the device’s total resistance, $R_{Total}$, can be calculated as the sum of $R_{sd}$ and $R_{ch}$.

$$R_{Total}={\displaystyle \frac{V_{ds}}{I_{ds}}}=R_{ch}+R_{sd}$$

(5)

Finally, the carrier mobility ($\mu$) is related to $R_{ch}$, as shown by the following equation [37]:

$$R_{ch}={\displaystyle \frac{L}{\mu { C}_{ox}W\left(V_{gs}-V_{th}\right)}}$$

(6)

where $L$ is the channel length, $C_{ox}$ is the oxide capacitance per unit area, $V_{gs}$ is the gate voltage, $W$ is the channel width, and $V_{th}$ is the device threshold voltage.

4. Results and Discussion

In this section, we present a collection of simulation results focused on the influence of different technology parameters—channel length, doping concentration, semiconductor bandgap, nanowire radius, oxide thickness, and gate dielectric permittivity—in determining the NWFET threshold voltage and channel resistance. A summary of the device parameters used during the simulations is reported in Table 1 and Table 2.

Table 1. Geometrical parameters used in the NWFET simulations.

NWFET Parameters	Reference Values
Channel length (nm)	5, 10, 15, 20, 50
Nanowire radius (nm)	2, 4, 6
Oxide thickness (nm)	1, 2, 3

Table 2. Technological parameters used in the NWFET simulations.

NWFET Parameters	Reference Values
Doping concentration (cm−3)	1 × 1018–1 × 1020
Energy bandgap for Si, Ge, GaAs, GaN, diamond (eV)	1.12, 0.66, 1.43, 3.44, 5.47
Relative permittivity for Si, Ge, GaAs	11.7, 16, 12.9
Intrinsic carrier concentrations for Ge, Si, GaAs (cm−3)	2.4 × 1013, 1.5 × 1010, 1.8 × 106
Dielectric constant for HfO2, Al2O3, SiO2	25ɛ0, 9ɛ0, 3.9ɛ0

4.1. Threshold Voltage Analysis

Considering a Si-based NWFET with a channel length of 20 nm, the temperature dependence of the threshold voltage is shown in Figure 3 for three different acceptor-doping concentrations. During the simulations, a metal work function of 5 eV was assumed. As we can see, for temperatures rising from 200 K to 400 K, $V_{th}$ goes down, showing a temperature dependence due to the increase in the intrinsic carrier concentration. Higher doping levels determine a more negative $V_{th}$ because of the enhanced built-in potential and the larger depletion region. This illustrates that dopant impurities and temperature both have a pronounced effect on the threshold voltage, as well as on the leakage currents and stability of the device.

Figure 3. Threshold voltage versus temperature for three different acceptor-doping concentrations in a Si-based NWFET.

The impact of a shorter channel length on the $V_{th}$ is shown in Figure 4. These curves were obtained for a silicon NWFET with a doping concentration of 1 × 10²⁰ cm⁻³. The most negative $V_{th}$ was observed for the shorter channel length (L = 5 nm), whereas the longer channel (L = 15 nm) had a relatively lower (in modulo) $V_{th}$, which increases the subthreshold leakage and can be explained by stronger short-channel effects for small-scale devices that weaken the gate control over the channel.

Figure 4. Threshold voltage versus temperature for three different channel length values.

Notably, Figure 5 shows that, for a rising temperature, $V_{th}$ was reduced independently of the oxide thickness due to the increased internal carrier concentration, which reduces the gate voltage required for switching on the device. A thin oxide ($t_{ox}$ = 1 nm) results in a more negative $V_{th}$ due to a higher gate capacitance and better electrostatic control of the channel. In contrast, a thick oxide can lead to weaker control by the gate. The obtained results emphasize the importance of increasing the electrostatic control by reducing the short-channel effects and reducing the oxide thickness to improve the NWFET’s performance.

Figure 5. Threshold voltage versus temperature for three different oxide thicknesses.

Figure 6 shows the $V_{th}$’s dependency on $T$ for wide-bandgap materials, for example, gallium nitride (Eg = 3.44 eV) and diamond (Eg = 5.47 eV). As we can see, with a temperature variation from 200 K to 500 K, $V_{th}$ decreased slightly. These behaviors can be attributed to thermal dependencies, such as the increasing intrinsic carrier concentration and the bandgap-narrowing effect, which indicate that semiconductors with larger bandgaps produce significantly fewer intrinsic carriers and, therefore, display a superior threshold voltage with an increased stability. Also, this result indicates that wide-bandgap semiconductors are less susceptible to leakage caused by temperature and are, thus, suitable for high-power and high-temperature applications.

Figure 6. NWFET threshold voltage versus temperature for gallium nitride and diamond.

On the other hand, Figure 7 shows the variation in $V_{th}$ with temperature for conventional semiconductors such as Ge (Eg = 0.66 eV) and GaAs (Eg = 1.43 eV). When compared with Si (Eg = 1.12 eV and $n_i$ = 1.5 × 10¹⁰ cm⁻³), the Ge’s behavior is linked to the lower bandgap and the higher intrinsic carrier concentration, which reduce the built-in potential, thus resulting in a less negative $V_{th}$. In fact, at T = 300 K, Ge has a higher $n_i$ (2.4 × 10¹³ cm⁻³) than Si, which makes it intrinsically more conductive, leading to undesired leakage currents. Also, by considering the relative permittivity of materials (i.e., 11.7 for Si and 16 for Ge), we must also consider that the higher relative permittivity affects the gate capacitance of the nanowire as well. Similarly, the GaAs’s behavior is mainly determined by a relative permittivity of 12.9, although it presents an extremely low $n_i$= 1.8 × 10⁶ cm⁻³, which assures poor thermal generation of carriers.

Figure 7. Threshold voltage versus temperature for germanium and gallium arsenide.

Figure 8 shows the variation in $V_{th}$ for different values of the oxide permittivity, ${\epsilon }_{ox}$, which were 3.9${\epsilon }_0$, 9${\epsilon }_0$, and 25${\epsilon }_0$ relative to SiO₂, Al₂O₃, and HfO₂, respectively.

Figure 8. Threshold voltage versus temperature for three different values of oxide permittivity.

As we can see, $V_{th}$ appears to be only slightly dependent on this parameter, although when the temperature increases, $V_{th}$ decreased for all cases as a consequence of the $n_i$ increase and bandgap narrowing, which reduce the required gate voltage to turn on the device. However, a higher oxide permittivity tends to enhance the gate capacitance, leading to a slightly more negative value of $V_{th}$.

Finally, Figure 9 shows the variation in $V_{th}$ with temperature for different values of the nanowire diameter. In particular, we considered $R_{nw}$ = 2 nm, 4 nm, and 6 nm. It is evident that small nanowires affect the gate control over the channel, determining a less negative $V_{th}$, which can be attributed to changed quantum-confinement phenomena.

Figure 9. Threshold voltage versus temperature for three different nanowire diameter values.

4.2. Channel Resistance Analysis

The channel resistance behaviors, as a function of temperature for different semiconductor doping levels, are shown in Figure 10. A carrier mobility reference value of µ_o = 100 cm²/Vs was assumed. As the temperature increased, $R_{ch}$ increased. This result is expected due to increased phonon scattering at higher temperatures, which reduces the carrier mobility. Also, the resistance was highest for the lowest doping level, and it decreased as the doping increased. Notably, we can state that higher doping concentrations not only reduce resistance, by increasing the carrier concentration, but also compensate for the mobility degradation due to the temperature. This appears to be a key finding for building effective NWFETs, particularly for applications involving high temperatures.

Figure 10. Channel resistance versus temperature for different doping concentrations.

We know that phonon scattering increases in the channel with temperature. However, in semiconductor nanowires, especially at nanoscale dimensions, other effects like the enhanced carrier concentration due to thermal activation across the bandgap can counteract this. When these opposing effects manifest, carrier mobility reduction and carrier density increase cancel each other out, and the net change in the $R_{ch}$ value can be minimal. In this context, it is evident that optimizing the carrier mobility in the device structure is critical for reducing resistance and improving the NWFET current’s capabilities. In fact, as shown in Figure 11 for different carrier mobility reference values (N_A = 5 × 10¹⁹ cm⁻³), while $R_{ch}$ increased with temperature due to enhanced phonon scattering, carrier mobilities that were too low led to a relevant increase in the device’s resistance ($R_{ch}\propto 1/{\mu }_0$).

Figure 11. Channel resistance versus temperature for different values of the carrier mobility.

Similarly, Figure 12 shows the $R_{ch}$’s dependence on T for different channel lengths (i.e., 10 nm, 20 nm, and 50 nm). Once again, the obtained results can be explained by the fact that charge carriers scatter more, increasing resistive losses. Also, shorter channel lengths perform better at higher temperatures. In fact, for L = 50 nm we can observe the steepest rise in $R_{ch}$, indicating that longer channel lengths intensify temperature sensitivity. On the other hand, when the channel length is very short, electron transport becomes fully ballistic, meaning that electrons travel through the channel with minimal scattering. Under such conditions, phonon scattering, which normally increases with temperature and leads to higher resistance in bulk or long-channel devices, plays a reduced role. In other words, since the channel length is short and the electrostatic control is strong, the mobility becomes less temperature dependent, leading to an almost stable $R_{ch}$ profile.

Figure 12. Channel resistance versus temperature for different channel lengths.

The effects of different nanowire diameters on the $R_{ch}$ curves are shown in Figure 13, where the channel resistance appears always slightly dependent on temperature. However, it is evident that a smaller nanowire radius exhibits a significantly higher resistance compared to the larger ones. This result is attributed to a stronger quantum confinement and an increased surface roughness scattering in narrower wires, which further impedes carrier transport.

Figure 13. Channel resistance versus temperature for three different nanowire diameters.

In the temperature analysis presented above, it is important to note that the NWFET’s channel resistance remained nearly constant with the gate-bias level, as shown in Figure 14.

Figure 14. Channel resistance versus temperature for different values of V_gs.

This behavior reflects the dominance of the electrostatic control for managing gate modulation and short-channel effects efficiently. In fact, the extremely small variation across all curves emphasizes that the device operates in a regime where temperature has only minimal influence on resistance. In other words, the changes in lattice temperature have minimal influence on carrier dynamics, thus leading to an almost temperature-independent $R_{ch}$ over a given bias range, which is an ideal characteristic for stable nanoscale electronics.

The dependence of the NWFET’s channel resistance on the gate-bias voltage, V_gs, for different design parameters, namely, the nanowire radius, channel length, and oxide thickness, is shown in detail in Figure 15, Figure 16 and Figure 17. From Figure 15, we can see that $R_{ch}$ decreased steeply as V_gs increased, indicating an enhanced electrostatic gating that induces a stronger inversion layer, thereby increasing the carrier density and lowering the resistance. In particular, from Figure 15, smaller nanowires exhibit a higher channel resistance due to a stronger quantum confinement, which limits the number of conducting subbands and suppresses the carrier mobility. In contrast, a wider nanowire (6 nm) benefits from reduced quantum effects and support higher carrier transport. This has a direct impact on the NWFET performance. In fact, devices with a larger radius offer lower resistance and a higher drive current, enhancing speed and transconductance, while a smaller radius, although better at controlling short-channel effects, suffer from a limited current drive and an increased delay due to the higher channel resistance.

Figure 15. Channel resistance as a function of V_gs for different values of the nanowire radius.

Figure 16. Channel resistance as a function of V_gs for different values of the channel length.

Figure 17. Channel resistance as a function of V_gs for different values of the oxide thickness.

Similarly, from Figure 16, as V_gs increased the $R_{ch}$ value decreased across all lengths due to an enhanced carrier accumulation in the channel, which reduces the resistive path. Notably, longer channel devices exhibit higher channel resistance due to the increased physical length through which carriers must travel, leading to greater scattering and resistive losses. Conversely, the shortest channel (5 nm) displays the lowest resistance, promoting better current conduction. From a performance standpoint, while shorter channels enable a higher drive current and faster switching due to a reduced $R_{ch}$, they also pose challenges such as worsened short-channel effects (SCEs) and possible leakage. Longer channels mitigate SCEs but at the cost of an increased resistance and degraded performance metrics like transconductance and switching speed. Thus, careful optimization of the channel length is essential for balancing electrostatic integrity and performance in NWFETs.

Finally, from Figure 17, the devices with thinner gate oxides consistently exhibited a lower $R_{ch}$ because a thinner oxide improves gate electrostatic control, enhancing the gate capacitance and enabling a more efficient inversion of the channel at lower voltages. In contrast, thicker oxides weaken the gate influence over the channel, requiring higher voltages to induce a comparable charge density, thus resulting in higher resistance values. A thinner t_ox is advantageous, as it reduces the $R_{ch}$, leading to higher drive currents, faster switching speeds, and improved transconductance. However, this comes with challenges such as an increased gate leakage and reliability concerns. Hence, optimizing oxide thickness is another key for balancing electrostatics, performance, and leakage in advanced NWFET designs.

4.3. Current–Voltage Characteristics

In this section, we present the NWFET’s output characteristics, namely, the drain-to-source current (I_ds) versus the drain-to-source voltage (V_ds), and the transfer characteristics, namely, the drain-to-source current (I_ds) versus the gate-to-source voltage (V_gs), calculated for different geometrical device parameters (channel length, oxide thickness, and nanowire radius), as shown in Figure 18, Figure 19, Figure 20, Figure 21, Figure 22 and Figure 23.

Figure 18. I_ds–V_ds curves for different values of the channel length. V_gs = 0.7 V.

Figure 19. I_ds–V_gs curves for different values of the channel length. V_ds = 0.5 V.

Figure 20. I_ds–V_ds curves for different values of the oxide thickness. V_gs = 0.6 V.

Figure 21. I_ds–V_gs curves for different values of the oxide thickness. V_ds = 0.5 V.

Figure 22. I_ds–V_ds curves for different values of the nanowire radius. V_gs = 0.7 V.

Figure 23. I_ds–V_gs curves for different values of the of the nanowire radius. V_ds = 0.5 V.

The curves in Figure 18 indicate that shorter channel lengths result in significantly higher I_ds values, especially in the saturation region due to a reduced channel resistance and an enhanced carrier injection efficiency. This behavior can be attributed to reduced scattering events and shorter transit times for carriers in shorter channels, which lead to an improved drive current. Moreover, the early onset of saturation in longer channels, combined with lower drain currents, highlights a stronger electrostatic control but at the cost of a reduced current capability. In contrast, the 5 nm channel shows higher current levels and a more gradual transition to saturation, which may also suggest the onset of short-channel effects such as DIBL. In addition, this plot emphasizes the performance versus control trade-off in ultra-scaled NWFETs and highlights once again the significance of a channel length optimization for balancing current drive and potential loss of gate control.

From Figure 19, we can clearly see that as the channel length decreased, the drain current significantly increased for a given gate voltage. This is a direct consequence of a reduced channel resistance and an improved carrier transport efficiency in shorter channels. At shorter lengths, carriers experience less scattering and shorter transit times, enabling a higher current flow. Moreover, the steeper subthreshold slope and rapid current increase in shorter channels suggest stronger gate control and higher transconductance. However, the increased I_ds for L = 5 nm may also indicate the influence of short-channel effects, such as threshold voltage roll-off and DIBL, which become prominent as the electrostatic control of the gate weaken with an aggressive device scaling.

Figure 20 clearly shows the impact of the oxide scaling on the device performance. For a given V_ds, transistors with thinner gate oxides yield higher drain currents, a result of the enhanced gate control over the channel and the stronger electrostatic coupling. As the oxide becomes thinner, the gate capacitance increased, leading to a higher inversion charge in the channel and, thus, a greater carrier injection from source to drain.

In Figure 20, each curve initially shows a linear increase in I_ds with V_ds, followed by the saturation regime as the channel near the drain enters pinch-off and velocity saturation effects dominate. The saturation current increases with a decrease in the oxide thickness, underlining the importance of aggressive oxide scaling in improving drive current and switching performance for high-performance NWFETs.

From Figure 21, we can see that decreasing the oxide thickness improved the gate control over the channel, leading to a higher drive current for a given V_gs. The thinnest oxide exhibited the highest I_ds due to the stronger gate capacitance, enhancing the inversion layer and boosting carrier density. As t_ox increased, the gate lost efficiency in controlling the channel potential, causing a reduction in the output current.

Finally, Figure 22 and Figure 23 show the effect of a different nanowire radius. In particular, as R_nw increased, the drain current significantly increased for all investigated V_ds (Figure 22). This behavior can be physically attributed to the enlarged cross-sectional area of the channel, which reduces the channel resistance and allows for more carriers to flow. A larger radius also accommodates a greater inversion charge due to the increased volume, enhancing the current drive. However, larger nanowire diameters can potentially degrade the electrostatic gate control, possibly due to a strong gate coupling or high-k dielectrics, as assumed in the simulations. All curves show typical transistor behavior with linear and saturation regions, and the saturation current increased with the radius.

At the same time, Figure 23 demonstrates how increasing the R_nw enhanced the device’s drive current capability. In fact, as the nanowire radius increased, the cross-sectional area available for carrier transport also increased, which reduced the quantum confinement and allowed for more charge carriers to flow through the channel for a given V_gs. This is reflected in the upward shift of the I_ds curve as R_nw increased from 2 nm to 6 nm. Furthermore, the steeper slope in the subthreshold and moderate inversion regions for larger R_nw suggests an improved gate control and stronger channel formation, leading to a higher transconductance. These effects are consistent with enhanced electrostatics and reduced channel resistance in thicker nanowires, making them more favorable for high-performance applications.

5. Conclusions

This work offers an in-depth exploration of the roles of different physical and material parameters in determining two fundamental figures of merit of an NWFET, namely, the device’s threshold voltage and channel resistance. Reducing the channel doping or the nanowire diameter tends to worsen short-channel effects and weaken the gate control. These changes drive the threshold voltage down and the channel resistance up. The resistance variation is further amplified under thermal stress. On the other hand, by reducing the channel length and the gate oxide thickness, the electrostatic control of the channel is improved. This enhancement leads to a more favorable shift in both the threshold voltage and channel resistance behaviors. Also, semiconductors with a wide bandgap display a threshold voltage with an increased stability.

A key finding is that, for short-channel devices operating under a ballistic or quasi-ballistic regime, the channel resistance remains remarkably stable with temperature (200–500 K). This temperature insensitivity arises considering the resistance governed by quantum conductance, electrostatics, and injection statistics, which are weakly temperature dependent. Moreover, if the carrier transport is dominated by quantum-confinement effects or degenerately doped conditions, especially at nanoscale dimensions, the scattering mechanisms do not significantly affect the overall channel resistance. In fact, the carrier injection is not thermally activated and then the resistive behavior is mainly geometric, not thermal, leading once again to a channel resistance nearly invariant with temperature. Such behavior is particularly advantageous for devices operating under variable thermal conditions. The near-constant channel resistance with temperature and the observed current-voltage characteristics for different geometrical device parameters showed a hallmark of advanced nanoscale transistors. Notably, NWFETs appear to be compelling candidates for high-temperature-tolerant nanoelectronic systems and, in general, for the next-generation of transistors, as the industry continues to push for more compact and thermally robust semiconductor technologies.