Review Reports - FPGA Implementation of High-Efficiency ECC Point Multiplication Circuit

Round 1

Reviewer 1 Report

My comments are as follows:

1. "anti-attack capability" -> "side channel attack resistance" would sound better
2. lines 17-18: "to improve the operation speed of ECC to improve the
reconstruction efficiency" -> improve used twice in the same phrase
3. line 22 -> time values have no relevance as long as clock frequency is not
mentioned
4. line 31: "are widely used" -> "adopted" sounds better as long as many countries
have problems with smartification
5. line 32 -> extra space is needed before mentioning references, the first issue
being "scenarios[1,2]"
6. lines 34-36: phrase is not clear
7. line 37: "so the fuzzy extractor is needed to correct the PUF response" ->
"could be used" sounds better because fuzzy extractors are a particular class of
error correction circuits, any other method useful for correction can be used as
well (it is important to give general hints and not reducing our discussion to a
single particular solution)
8. line 44: "simple, and it can be realized simply" -> simple is used twice
9: line 74: "makes a plan for the next step of research" -> it is not necessary to
mention a future plan (actually it is not recommended at all)
10: line 79: " the security authentication cannot be realized" -> authentication
can't be realized securly (or secure authentication can't be achieved)
11: line 86: use "cannot" instead of "can not"
12: lines 89-90: "Numerous studies have been proposed during the last decade/years
[...]" would sound better.
13: line 4: "and Yan Zhang and Rui Chen" -> it is not clear why we have "and" inserted twice
and so on... Authors are invited to review English style and synthax, there are still many errors left.

14. Eq. (1) seems to be a picture/screenshot, authors are invited to insert
equations instead of pictures, the same comment is applicable to algorithms.

15. Titles should stay on the same page as their content, the opposite can be noticed on line 366.

16. MOD_INV_SETP crosses the arrow denoted as T4 (Fig. 13). They should be distinct.

17. Figure 19 has generic description...!? ("Figure 19. This is a figure. Schemes follow the same formatting.")

18. In Table 5, "Circuits" could be replaced by "Solutions".

19. Judging the performances reviewed in Table as a function of frequency it is obvious that the solution proposed in this article is better. However, it is not clear how these values are obtained. For example, we have 19.33 which is close to 19.34 reported by [20]; it is not clear why they are so closed.

I am pretty sure that we have a rich literature focused on ECC HDW implementations so a longer final table would be expected.

The second major issue addresses Figs. 17 & 18. These are generic pictures. To increase the confidence level, authors are invited to update the manuscript with photos disclosing the real physical setup and also practical measurements (taken with an oscilloscope or other means). Without these, the results reported in Table 5 are theoretical values, therefore not enough for being published in a journal.

Author Response

Dear Reviewer:

Thank you for your comments concerning our manuscript entitled “FPGA Implementation of High-Efficiency ECC Point Multipli-cation Circuit” (ID: electronics-1203176). Those comments are all valuable and very helpful for revising and improving our paper, as well as the important guiding significance to our researches. We have studied comments carefully and have made correction which we hope meet with approval. Revised portion are marked in red in the paper. The main corrections in the paper and the responses to the reviewer’s comments are in the letter.

Thank you again for taking time out of your busy schedule to review our paper and provide valuable opinions and constructive suggestions to further improve this round of manuscripts. We have revised the manuscript appropriately (where markups are used to track all the changes as instructed by the editor). We hope that our responses and revisions are satisfactory.

Thanks!

Author Response File: Author Response.pdf

Reviewer 2 Report

Paper is well written and technically sound, with minor modifications of typos and grammatical mistakes. Contributions are also clearly mentions. I would recommend it for publication with minor revision of typos and grammatical mistakes.

Author Response

Dear Reviewer:

Thanks!

Author Response File: Author Response.pdf

Reviewer 3 Report

This article implements a binary field Elliptic Curve Cryptography (ECC) point multiplication (PM) circuit in a FPGA device. The procedure of producing the point multiplication result is divided in its parts, each one implementing a part of the overall algorithm. The authors claim some progress with respect to previously published implementations of the ECC PM procedure, especially by performing a multiplication with four key lengths, expandable to N different key lengths and implementing a pair of ECC algorithms in parallel.

The article is mostly well written, however there are some key corrections that need to be made. First, the overall length of the article needs to be compressed, especially section 3, where the background knowledge is expanded. Although background is needed, it should probably be delivered by a more careful selection of the literature in the References section. Only what is essential for the actual FPGA implementation needs to be presented in some length, along with those algorithms that are not presented elsewhere in the literature. Section 4 is essential but in my opinion should be re-written in a more compact form.

The reference list should be expanded and the relevant literature should be reported in more detail, both with respect to ECC cryptography and with respect to relevant FPGA implementations.

Some grammatical errors persist, as well as formatting errors. For example, in p. 3 the affiliations of authors of literature articles given in parentheses are not relevant and should be omitted. Again in p. 3 lines 131, 132 make no sense and probably are leftovers from formatting instructions. Figure 2 needs some lettering enhancement. The title of Table 4 (p. 15) needs correction. In Fig. 20, line 519, reference to “Figure 18” should become “Figure 19”. Lines 536 and 599 need review and correction. Line 608 a (log2) in parenthesis makes no meaning. Other similar oversights all over the text need careful review and correction.

Author Response

Dear Reviewer:

Thanks!

Author Response File: Author Response.pdf

Reviewer 4 Report

The main content of the paper is the decryption of a digital design for ECC point multiplication supporting different key lengths, what is fine.

What remains unclear is whether the design is optimized for a specific purpose (the introduction can be understood in this way that it is intended specifically for decrypting PUF helper data), or whether IoT is just a motivating example where device authentication would be needed.

Several aspects of the use case described for motivating the design are unclear:

The addressed used case is to decrypt PUF helper data: How would decryption help here, would rather authentication of helper data be needed? Which specific fuzzy key extraction do you have in mind that would required independent authentication/encryption of helper data? Where would the cryptographic key be stored that would be needed for this? Usually, PUF realize the key store, but here it seems a PUF-independent key store would be needed in addition. Why would a PUF be used at all if key material is already available? How would keys be established?
When would PUF helper data be decrypted/verified? If this happens only once during power-up, what design objectives for the ECC part would be relevant for this case (probably rather optimization for size, not for speed)? Why are different key lengths needed for this use case?
The introduction mentions side channel resistance. How has this aspect been addressed by the design of the multiplier? What overhead is introduced (space, speed)?
Introduction motivates PUF for device authentication "fingerprint can achieve lightweight authentication": What exactly is your intended use of a PUF? Realize a non-volatile key store, do device authentication directly using a PUF (then, what would be the purpose of the ECC point multiplication), or verifying PUF helper data read from an untrusted memory?
Section 2: "For equipment certification, ....": Unclear what is meant (really certification, and if yes according to which standard)?
Is the design optimized for FPGA or for ASIC? How does it compare to (typically commercial) implementations optimized for specific FPGA architectures or ASICs?
Section 5: Have further tests been performed to check the correctness of the implementation (for different data, and key sizes)? It is not necessary to include all the test data, but describe how you have verified the design. Having just one single test value for which the correct results is obtained is not convincing.
What has been implemented beyond the point multiplication as such (e.g., also a PUF, a key extractor, an authentication/encryption function)?

Please consider updating the description of the use case motivating the need for the specific design, and also evaluation.

Editorial comments:

Space should be added before references (e.g., "scenarios[1,2]" -> "scenarios [1,2]"
Some figures seem to be broader than text width.
"Setp" in figures should probably be "Step"
Title of Table 4 seems to come from a template ("This is a table. Tables should be placed in the main text near to the first time they are cited")
Abbreviations: Use consistently (either "IoT" or "IOT"); introduce meaning at first use (e.g., τNAF )
Introduction: "perform encryption operation of randomly selected four key lengths": meant is probably "arbitrarily"
Introduction: "Section 3 gives a brief on the mathematical" -> "Section 3 gives a brief overview on the mathematical"

Author Response

Dear Reviewer:

Thanks!

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

First of all, the authors did the best to answer at my comments, as detailed in their cover letter. In addition, the content is significantly improved from technical perspective, offering more details that clarify the context. However, there are new issues, as follows (and not limited to):

1. Pictures should be centered.

2. It is normal to have a space between a text line and the picture following below.

3. There are unclear phrases such as:

"[13], which is to be gained by the following Algorithm 9." (line 235) ;

"PM, which enables the influence of different field multipliers to be reflected" (line 531) ;

"standard project coordinates to" (line 532),

" the research group will delve into" (which research group?, line 539)

and so on.

4. Extra space should be inserted within text in the following cases: "Freq(MHz)", "TT(μs)", "Freq.(MHz)", " 2.5µs", "4.09µs", " 163bit", " Fig.2", etc.

5. There is a difference in citing similar references, such as "IET Comput. Digit. Tech. 2019, 13, 361–368" vs "23-24 Oct. 2018; IEEE: 2019" or " Circuits and Systems I: Regular Papers， 2017， 64（2）： 399-408" (why ';' and ':'). Also, why "Cited 24 June 2009"...?

Authors are advised to recheck the manuscript.

Author Response

Dear Reviewer:

Thank you for your comments concerning our manuscript entitled “FPGA Implementation of High-Efficiency ECC Point Multiplication Circuit” (ID: electronics-1203176). These comments have important guiding significance for the improvement of our work. Thank you again for your meticulous reminder. We have carefully studied the opinions and made corrections, hoping to get approval. The revised part is marked in red on the paper.

Author Response File: Author Response.pdf