Abstract
Aiming at the problems of intelligent ship inductive power transfer (IPT) systems under complex marine operating conditions, such as susceptibility to parameter perturbations and power device faults, which result in low modeling accuracy, slow dynamic response and poor post-fault stability, this paper investigates an integrated full-system fault diagnosis and hierarchical fault-tolerant control strategy. Based on the complex Fourier series and generalized state-space averaging (GSSA) method, a complete nonlinear time-domain model of the IPT system is established. The high-order switching-coupled system is accurately reduced to a first-order dominant model, and the inherent over-damping characteristics of the system as well as the influence rules of relevant parameters are clarified. A PI closed-loop regulation strategy is designed, and the trade-off mechanism of proportional integral parameters regarding steady-state accuracy, response speed and fault robustness is revealed. Comparative theoretical analysis and simulation results verify that the established model is highly consistent with the dynamic characteristics of the practical system, with the steady-state error controlled within 2%. Under the open-circuit fault of power switches, the system can still maintain stable output current without instability or sharp current drop, demonstrating excellent fault tolerance. The research findings provide a theoretical basis and technical support for high-precision modeling, parameter tuning and the safe and reliable operation of wireless charging systems for intelligent ships.
1. Introduction
Driven by the rapid advancement of artificial intelligence in recent years, numerous industries, including medical treatment, electric vehicles, unmanned aerial vehicles, smart grids and marine shipping, are advancing toward full-scale intelligent transformation [1,2,3]. Conventional ships are predominantly powered by diesel engines and gas turbines, which heavily rely on non-renewable fossil fuels. Amid tightening global maritime situations and growing shortages of oil and gas resources, all-electric ships have emerged as a promising mainstream trend for future shipping. Medium- and large-sized intelligent all-electric ships usually demand megawatt (MW)-level power supply. The conventional wired charging scheme requires bulky heavy cables and substantial manpower and material resources for docking and charging operations. Benefiting from its outstanding convenience, IPT has been widely adopted for the shore-to-ship charging of intelligent vessels [4,5,6]. As illustrated in Figure 1, after an intelligent ship berths at the port, the shore-mounted robotic arm can automatically align with the receiving coil installed onboard, enabling efficient high-power charging even under minor ship swaying motions.
Figure 1.
Wireless charging scenario of intelligent ship at shore side.
Nevertheless, wireless power transfer (WPT) systems consist of a large number of electronic components. As intelligent ships operate persistently in harsh marine environments featuring high humidity, high salinity and strong winds, electronic equipment on the receiving side is prone to premature failure [7,8,9]. Against this backdrop, scholars worldwide have carried out extensive research on relevant system faults.
In recent years, T-type three-level converters [10], constant-current IPT systems, and doubly salient electromagnetic machine (DSEM) drive systems [11] have been widely adopted in new energy grid integration, wireless charging and special-purpose drive applications. Nevertheless, power switches and rectifier diodes are susceptible to open-circuit faults under high-frequency operation, elevated temperatures and severe electrical stresses. Such faults readily trigger current distortion, neutral-point potential drift, abrupt output drop and even catastrophic system breakdown, which constitute the primary bottleneck restricting reliable system operation. Conventional fault-tolerant control and fault diagnosis approaches suffer from inherent drawbacks: traditional PWM/SVM-based fault-tolerant schemes neglect the fault-induced variations in system mathematical models and exhibit poor performance in multi-objective coordinated regulation; rectifier faults in IPT systems tend to incur transient overvoltage [12], while existing protection strategies either rely on redundant hardware or fail to accommodate the evolutionary processes of multi-switch faults; for the converter fault diagnosis of DSEM drive systems, prevalent methods are plagued by excessive diagnostic latency, mandatory auxiliary sensor deployment, and an incapability of simultaneous localizations for single- and dual-switch faults, further resulting in out-of-control currents and excessive current ripples during fault-tolerant operation.
Meanwhile, emerging technologies, including model predictive control built upon fault state-space equations, LC fault-tolerant topologies free from extra switching devices [13], and rapid diagnosis based on DC-bus current signatures, have opened up innovative avenues for fault modeling, on-line fault identification and adaptive fault-tolerant regulation. However, an integrated solution that simultaneously satisfies consistent fault mechanism characterization, high-speed diagnosis, seamless control transition and minimal hardware overhead is still absent. Accordingly, a lightweight and versatile fault-tolerant topology deployed on the secondary side is urgently required to enhance the overall reliability of the entire system.
Apart from generic fault-tolerant topologies, a complete closed-loop control scheme is also indispensable for practical engineering applications. This paper focuses on maintaining high-efficiency and stable system operation under secondary-side fault conditions. Domestic scholars have proposed numerous fault-tolerant control strategies and modeling methodologies in existing research [14,15,16]. Ref. [17] developed a floating-capacitor voltage-balancing-based fault-tolerant control scheme for hybrid T2C-HB converters. The method stabilizes line voltages and balances capacitor voltages post-fault without redundant hardware or additional sensors, yet it is only valid for single-switch fault scenarios. Ref. [18] put forward a signal-diagnosis-based fault-tolerant approach for interleaved Boost converters in fuel cell applications, featuring sensorless implementation, rapid fault diagnosis and strong anti-interference capability; nevertheless, the solution is exclusively applicable to multi-phase interleaved architectures. Ref. [19] applied model-free predictive control to three-level T-type converters, where a neural-network-based observer enables inherent fault tolerance, streamlines fault diagnosis and accommodates both single and dual power-switch faults. However, this approach increases computational burden and imposes minor adverse impacts on neutral-point potential regulation. For partially observable shipboard power systems, Ref. [20] proposed a distributed state estimation and fault-tolerant control strategy that accelerates fault localization by two orders of magnitude, whereas its core emphasis lies in system-level reconfiguration rather than device-level fault tolerance of power converters. Ref. [21] presented an SPWM reconstruction-based fault-tolerant strategy for cascaded multilevel propulsion converters. The technique improves the fundamental amplitude of post-fault output voltage and equalizes power losses with no extra hardware required, yet it suffers from complicated modulation logic and is limited to cascaded H-bridge topologies. Ref. [22] investigated a hybrid modulation and capacitor voltage balancing strategy for dual five-level ANPC inverters deployed in marine propulsion systems, which achieves independent and stable regulation of neutral-point and floating-capacitor voltages alongside superior output harmonic performance and abundant voltage levels, while overlooking fault-tolerant operation against power device failures. Targeting fluctuating wave load conditions, Ref. [23] established a propeller speed adaptive power management strategy to suppress propulsion power oscillation without auxiliary energy storage, effectively mitigating frequency and voltage distortion of shipboard grids; unfortunately, the method is optimized merely for power fluctuation suppression instead of converter fault handling. Ref. [24] designed an optimal control framework for high-power intelligent ship charging networks at harbors, supporting multi-form AC/DC power supplies with diverse voltages, frequencies and wiring configurations to enhance shore power utilization and universality. Still, this research centers on shore-side power supply topologies and fails to address reliability and fault tolerance of on board receiving terminals.
In summary, existing achievements fall short of developing a universal, lightweight secondary-side fault-tolerant solution suitable for harsh marine environments. Therefore, it is urgent to conduct integrated research on fault diagnosis and fault-tolerant control to strengthen the reliability and environmental adaptability of marine power electronic systems.
The subsequent content is arranged as follows: Section 2 details the transmission characteristics and fault-tolerant performance of the LC fault-tolerant constant-current IPT system. Section 3 constructs the generalized state-space equations of the full system to pave the way for the subsequent controller design. Section 4 analyzes the stability and dynamic performance of the practical closed-loop system. Section 5 covers simulation and experimental verification, focusing on the post-fault output stability of the system as well as the effects of controller parameters.
2. Performance Analysis of LC Fault-Tolerant IPT System
2.1. System Configuration and Fault-Tolerant Effectiveness
As depicted in Figure 2, an LC protection unit is introduced at the front stage of the rectifier in the traditional SS-type constant current (CC) output topology. In the case of a rectifier open-circuit fault, the secondary side establishes an alternative circuit path with the LC protection device, thereby preventing the occurrence of overvoltage at the rectifier input terminal. The complete system is composed of a DC constant-voltage input power supply, a medium-frequency inverter, primary and secondary compensation networks, a loosely coupled coil, a full-bridge uncontrolled rectifier, a filtering circuit, and the load. Additionally, the system simulation parameters are tabulated in Table 1 to facilitate the subsequent analysis.
Figure 2.
Fault-tolerant constant current IPT system.
Table 1.
System simulation parameters.
As shown in Figure 3 and Table 2, the system operation can be categorized into four modes according to the parameters of the LC protection module. Traditional corresponds to the conventional SS topology without any protection scheme. Mode I employs only an inductor for protection, which may introduce a hazardous voltage spike at the instant of the D1 open-circuit fault. Mode II uses the same total reactance as Mode I, where the added capacitor effectively absorbs fault-induced voltage spikes and allows a smaller inductance to be adopted. Mode III keeps the same inductance as Mode II but uses a smaller capacitor, which helps mitigate the intermittent interruption of the input current to the rectifier [13].
Figure 3.
Variation in rectifier input voltage under different modes before and after D1 open−circuit fault at t = 0.02 s.
Table 2.
Simulation parameters for different protection modes.
2.2. System Output Characteristics
2.2.1. Constant−Current and Constant−Voltage Output in Second−Order Two−Port Networks
Figure 4 depicts typical second-order two-port networks. Figure 4a shows the left L-type network fed by a constant voltage source, whereas Figure 4b illustrates the right L-type network driven by a constant current source. In these configurations, X1L, X2L, X1R, and X2R represent the total reactance of the corresponding branches. On the basis of Kirchhoff’s laws, the output current of the left L−type network and the output voltage of the right L-type network can be derived as follows:
Figure 4.
Second−order two-port network. (a) Left−L-type. (b) Right−L-type.
It can be observed from (1) that achieving constant current and voltage output independent of the equivalent impedance Zeq requires the resonance condition shown in (2).
Substitute (2) into (1) and simplify to obtain:
When the resonance condition defined in (2) holds, the left L−type second-order network achieves voltage−to−current conversion, and the right one realizes current−to−voltage conversion. The total input impedance of the dual networks is presented in (4).
2.2.2. AC Transfer Efficiency
The topology shown in Figure 2 is simplified via fundamental harmonic analysis and the T-type equivalent method of the coupler. The corresponding equivalent circuit is presented in Figure 5. Meanwhile, the system resonant frequency ω0 is defined and complies with the formulas in (5).
Figure 5.
T−type equivalent circuit of coupled coils.
When the primary side circuit in Figure 4 operates at the resonance condition of the left L-type second-order network, the secondary side voltage stays consistent with Up. Supplied by a constant voltage source, the output current Is is constant and features negligible harmonics. This paper only focuses on the fundamental component of Is. Additionally, to maximize system active power transfer and achieve inverter soft switching, the system total input impedance is designed to be weakly inductive in practical implementation.
To simplify the subsequent calculation process, the impedance is defined in (6). The internal resistances of inductors and the coupler are neglected during system gain calculation. Nevertheless, the parasitic resistances of all components should be taken into account for AC transmission efficiency analysis.
When the inverter operates at the resonant frequency, substitute (6) into (4) to derive the system’s total input impedance, presented in (7).
Based on Kirchhoff’s laws, the electrical quantities for all components of the system are expressed in (8). Under the resonance condition defined in (5), Is keeps a constant value. For I2 to remain unchanged, the following inequality must hold: .
Major active power losses of the system arise from the inverter and rectifier switching losses, coupling coil losses, and losses of inductors in the LC network. In the AC efficiency calculation, converter switching losses are disregarded, with only coupling coil losses and LC inductor losses considered. The expression for AC active power efficiency is presented in (9).
3. Development of the Linearized System Model
3.1. Introduction to Exponential Fourier Series
For an improved analysis of converter switching functions in IPT systems, we adopt the concept of the complex Fourier series. The formula for the classic trigonometric Fourier series is presented in (10).
Here, let . The relationship between trigonometric functions and complex numbers can be established via Euler’s formula, as follows:
Substituting (11) into (10), we obtain:
The complex Fourier form of an arbitrary signal is presented in (12). There exist three distinct cases depending on the value of n.
where denotes the coefficient of the n-th complex Fourier series, and and are a complex conjugate pair. Thus, (12) can be expressed uniformly as follows:
where and stand for the real part and imaginary part of . The first expression in (14) is the complex Fourier form of the signal, and the second is the trigonometric Fourier form. As stated in the Refs. [25,26,27], the complex Fourier series complies with three core operational properties: differentiation, convolution and linear relations.
3.2. Generalized State-Space Modeling of Open-Loop Systems
The previous chapter presented the optimal fault-tolerant topology for constant-current IPT systems. To establish the state-space equations and derive the transfer function between the input source and load output, all internal parasitic resistances of inductors in the system are neglected. The corresponding circuit is illustrated in Figure 6.
Figure 6.
LC-type fault-tolerant IPT system with neglected parasitic resistance.
The complete system comprises the outer DC part, inner AC part and switching function module of the converter. Coil decoupling implemented on the topology in Figure 6 yields the equivalent circuits for each component, which are illustrated in Figure 7.
Figure 7.
Coil decoupling circuit.
In the generalized state-space averaging (GSSA) model, small signals represent minor perturbations around the steady-state operating point and are components of the full large signals. In the IPT system, the DC input voltage and DC output vary slowly and contain approximately only the zero-order harmonic component, i.e., DC quantities. By contrast, the output voltage of the inverter and the input voltage and current of the rectifier are large signal variables, for which only the first-order harmonic component is adopted in GSSA modeling.
3.2.1. Time-Domain Equations of the System
After removing the dotted terminals of the coupled coils in the system, two independent controlled voltage sources are formed on the primary and secondary sides. Taking the capacitor voltages and inductor currents within the system as state variables and defining the directions of electrical quantities in Figure 5 as the reference directions, the corresponding time-domain differential equations of the system are presented in (16).
where stands for the first derivative with respect to time. Externally, ZL presents resistive-capacitive properties.
3.2.2. Small-Signal Approximations for State Variables
Based on the differential equations established from (16), the output voltage of the inverter and the input voltage of the rectifier are square-wave signals. When the system operates at the resonance point, the AC section contains few harmonics, so only the fundamental component is taken into account. The inverter can be controlled by adjusting the pulse duty cycle and frequency, while only duty cycle control is discussed in this chapter. As shown in Figure 8, the square-wave output voltage turns into a trapezoidal waveform after phase shifting the pulses of the rear bridge arm, with its duty cycle denoted as d.
Figure 8.
Inverter timing diagram.
The nonlinear switching function sp(t) for the inverter and switching function ss(t) for the rectifier are introduced, as expressed in (17).
Accordingly, the expressions for the inverter output voltage, rectifier input voltage and output current can be deduced by means of the switching functions:
Expand sp(t) and ss(t), the switching functions, into the first-order trigonometric Fourier series:
In accordance with the relation between trigonometric Fourier coefficients and complex Fourier coefficients presented in (13), the first-order coefficients of the complex Fourier series for the switching functions in (19) are deduced and listed in (20).
Given that uin serves as the system DC input and consists solely of the zero-order phasor, the procedure for the first-order complex Fourier expansion of up(t) in (18), based on the convolution formula and complex Fourier series, is as follows:
Extract the first-order harmonics of inductor currents and capacitor voltages in (16), and take the DC component for the filter capacitor voltage. The first-order harmonic approximation of each state variable is expressed as shown in (22).
If the entire inductor currents and capacitor voltages are selected as state variables, nonlinear issues cannot be easily solved. For this reason, we transform the complex Fourier form into real and imaginary parts to build the state space. The expansion of complex Fourier coefficients in (23) is given below:
In this case, the system now has fifteen generalized state variables, compared with the original set of eight: , , , , , , and .
3.2.3. Generalized State Space Construction
Define the general formula of the new generalized state variable in (23) as . By computing the first time derivative on both sides, the general expression of is presented as follows
The first-order complex Fourier series of uab(t) and zero order complex Fourier expansion of io are deduced, as shown in (26).
In this expression, represents the impedance angle corresponding to the rectifier equivalent impedance. After substituting (21) through (26) into (16) and matching the coefficients of sinusoidal and cosinusoidal components, the new set of generalized state-space equations is presented in (27).
Rearrange the seventh equation from (16). Suppose , and its associated admittance is . Accordingly, the coefficients of the first-order complex Fourier series for this equation are matched.
The above equation is simplified to derive the relationship governing the coefficients of i2 and uab.
By substituting (29) into (27) and performing order reduction, a 13th-order system is derived, which gives the final state-space equations.
Based on the above expression, the system’s generalized state-space matrix is further deduced and presented in (31).
Based on the experimental data in Table 1, the transfer function of the system output y = IL with respect to the input u1 = uin is derived using the built-in sys and tf functions in MATLAB 2023b, as shown below.
The corresponding pole zero results are presented below.
The open-loop transfer function of the investigated system is presented in (32). To further verify the validity of the calculated results, comparisons with system simulation are conducted. The unit step responses of the system are tested respectively, as illustrated in Figure 9.
Figure 9.
Correction diagram of open-loop transfer function. (a) Before revision. (b) After revision.
While all system parameters are kept identical, the parasitic resistances of inductors are neglected in the derivation of theoretical formulas. Comparisons of the system step responses reveal that the theoretical model and circuit simulation exhibit identical dynamic performance, including pole locations, transient response speed and damping ratios. The only discrepancy is a fixed 20% steady-state amplitude offset. This offset is attributed to inaccurate static gain induced by modeling simplification of the open-loop transfer function, rather than flawed dynamic system architecture or incorrect simulation configurations. Such modeling bias can be fully compensated through static gain calibration. As depicted in Figure 9b, the theoretical and simulated step responses achieve nearly perfect overlap after multiplying the transfer function by a static correction factor of 0.8.
4. Stability and Dynamic Characteristic Analysis of Closed-Loop System
4.1. Equivalent Open-Loop Transfer Function
The open-loop transfer function, Gyu1(s), from load current to DC input voltage, derived in the previous section, is a 13th-order system, which is impractical for direct engineering application. Therefore, order reduction is implemented by analyzing its dominant poles and zeros.
Rewriting Gyu1(s) in root form yields the simplified expression as follows:
where szi and spj denote the real zeros and real poles of Gyu1, respectively; ai and bi represent the real and imaginary parts of the complex conjugate roots. Here, m is the number of real zeros, and n is the number of real poles.
When a unit step signal is applied to the DC input of the system, the corresponding output IL(s) and its time-domain solution are derived as follows:
where denotes the first-order derivative of D(s) with respect to s, and represents the modulus operation.
Analysis of the time-domain solution of the output shows that poles farther from the imaginary axis decay to zero more rapidly and only affect the system at the early transient stage. As time elapses, only the zeros and poles close to the imaginary axis dominate the system dynamics. The zeros and poles of Gyu1 are listed in (34), and their distribution is illustrated in Figure 8.
As observed from the pole–zero plot in Figure 10, the pole closest to the imaginary axis is −357. The subdominant poles and dominant zeros are located far farther from the imaginary axis, with their distances over 80 times that of the dominant pole. The reduced-order open-loop transfer function can be approximated by a first-order system, as presented in (36).
Figure 10.
Pole−zero map of the open−loop transfer function.
4.2. Steady-State Error and Stability Analysis of Closed-Loop System
When rewriting Gyu1(s) into root form, it can be simplified as follows
where szi and spj denote the real roots of zeros and poles of Gyu1, respectively. ai and bi represent the real and imaginary parts of the complex conjugate roots. m is the number of real zeros, and n is the number of real poles.
To facilitate the analysis of steady-state error and the design of controller parameters, (38) in root form is converted into the unity constant term standard form.
Here, K1 denotes the open-loop gain of the system. Since the input signal and control signal are multiplied in the state-space Equation (31), and the control variable d is contained in the input matrix B1, it is difficult to derive the corresponding control block diagram. Therefore, we redefine the system input as . The new state-space equations of the system are presented below.
Thus, the transfer function from the new input u2 to the output y = IL is derived and presented in (40).
A nonlinear relationship exists between the two transfer functions. For further simplification, the term is approximated by its first-order small-signal model around d = 0. The resulting control block diagram is shown in Figure 11, where uin and the control signal d satisfy an algebraic product relationship.
Figure 11.
Closed−loop control block diagram.
A conventional PI controller is adopted in this chapter. To reduce the impact of noise on the system, the derivative term is excluded. The general frequency-domain expression of the PI controller is given below.
According to the system control block diagram in Figure 9, the steady-state error transfer function of the closed-loop system is derived and presented in (42).
Meanwhile, the steady-state error of the system e(∞) is expressed as:
Here, denotes a positive value approaching zero. It is evident that for a system without an integral term, a larger proportional gain Kp leads to a smaller steady-state error. Nevertheless, the integral gain should not be set excessively large. Since the duty cycle of the controller output is constrained within the range of 0 to 1, excessive error accumulation before the system reaches a steady state will easily cause saturation of the PID output, resulting in persistent steady-state deviation that cannot be eliminated.
Substituting (36) and (40) into the closed-loop control system illustrated in Figure 9, we obtain the closed-loop transfer function from the reference signal IL_ref(s) to the output IL(s) as follows:
According to the Routh stability criterion for linear systems, the overall system remains stable when the parameters d, Kp, uin and Ki are all positive in the characteristic equation.
5. Simulation and Experimental Verification
5.1. Simulation Verification
The system parameters adopted in the simulation are consistent with those listed in Table 1. The output of the controller is limited within the range of [0, 1]. To avoid excessive accumulation of the error integral term, the initial integral coefficient is set to less than 1. The overall simulation process is illustrated in Figure 10, which consists of three successive stages: open-loop response, controller activation, and fault-tolerant control.
As shown in Figure 12, from 0 to 0.03 s, the system operates in the open-loop mode with a DC input voltage of 100 V and a duty cycle of 1. Since no closed-loop current regulation is applied, the load output current rises in an overdamped manner. At 0.03 s, the closed-loop control loop is switched on. The initial integral coefficient is set to 1 and the proportional coefficient is set to 5. The load output current is accurately regulated to the reference value of 4 A within 0.8 ms. In addition, as the proportional gain Kp increases gradually from 5 to 25, the steady-state current error decreases monotonically.
Figure 12.
System output control performance with different proportional coefficients.
An open-circuit fault occurs in the power switch D1 at 0.06 s, which leads to abrupt changes in the converter topology and equivalent gain, and the system enters the fault-tolerant operation mode. After the fault occurrence, the current can be maintained around the target value of 4 A under all parameter conditions without system instability or severe current drop, indicating that the closed-loop control still maintains basic regulation capability under faulty conditions. Nevertheless, the steady-state current ripple and dynamic oscillation amplitude increase remarkably, resulting in obvious degradation of the system’s steady-state performance.
Considering the soft-start operation of the inverter switches in practical implementations, the system does not operate under a fully compensated resonant state. Additionally, the effects of the inductor internal resistance and the equivalent impedance of the rectifier circuit further degrade the constant-current output performance, as shown in Figure 13.
Figure 13.
Dynamic response curves of output current with diode open-circuit fault under different loads.
As the load increases, the system time constant increases accordingly. Consequently, the open-loop response current gradually decreases, and the response speed slows down. After the closed-loop control is activated, the dynamic response is significantly improved, enabling the output current to be stably regulated at 4 A. This performance remains unaffected even after the open-circuit fault of switch D1 occurs.
5.2. Experimental Verification
5.2.1. Platform Introduce
To validate the operating performance of the proposed fault-tolerant system, a kilowatt-scale experimental prototype for the IPT system was built, as illustrated in Figure 14. In the experimental setup, four DZ47S-C40 air circuit breakers (Zhejiang, China) rated at 40 A are deployed to independently trigger open-circuit and short-circuit faults in each diode. The entire system is fed by a DC power supply, capable of delivering an upper limit voltage of 750 V and a peak output current of 35 A. The inverter circuit adopts four C2M0025120D MOSFET (Wolfspeed, Durham, NC, USA) devices, while the control board integrates a TMS320F28335 DSP chip (Texas Instruments, Dallas, TX, USA) and a XC6SLX16 FPGA (Xilinx, San Jose, CA, USA) to generate drive pulses for the inverter.
Figure 14.
Experiment platform.
The rectifier circuit is fabricated on a 200 mm × 190 mm double-sided printed circuit board (PCB), fitted with 12 external terminals to regulate the working states of the four diodes. The rectifier diodes selected are MUR6060PT, featuring a rated reverse breakdown voltage of 600 V, a maximum average forward rectifying current of 60 A, a reverse saturation current of 10 μA at 600 V and 25 °C ambient temperature, as well as a maximum reverse recovery time of 50 ns.
Table 3 lists the key experimental parameters of the system. The LC compensation network possesses an inductance of 40.4 μH and an internal resistance of 0.08 Ω, alongside a capacitance of 94 nF [13]. With the above parameter configuration, the LC compensation network achieves compact size and a light weight owing to its low inductance values, while enabling the system to attain the maximum AC power transfer efficiency; its equivalent reactance reaches −260 Ω, indicating overall capacitive characteristics. After being paralleled with the load impedance ZL, this network allows the inverter to achieve ZVS operation. Figure 13 depicts a pair of identical square-shaped coupled coils. Their coupling coefficient is measured as 0.24, and the vertical separation along the Z-axis is set to 130 mm. In normal operation, the two coil assemblies are precisely aligned face-to-face with no positional offset in either the X or Y direction. Each coil is wound with 14 turns in total, and the single wire strand for every turn features a diameter of 2.45 mm, as shown in Figure 15 and Table 4.
Table 3.
Experimental parameters of the system.
Figure 15.
Structure of the coupling coils. (a) Actual item. (b) Space structure. (c) Inner structure.
Table 4.
Coupling coil parameters.
5.2.2. System Real-Time Control in Normal Operation
In this control experiment, the value acquired by the AD sampling chip is 338 times the actual current. The sampled data is read via the ad [3] port of the DSP and stored in the corresponding array. The control interrupt frequency is set to 10 kHz, corresponding to a sampling period of 0.1 ms.
The output of the controller consists of a proportional error term and an integral error term. Due to the cumulative characteristic of the integral term, the system fails to converge to a steady state. Consequently, the real-time duty cycle oscillates continuously within a small range. Both the controller output and integral output are limited to the range of [0, 1], and the proportional coefficient and integral coefficient are both set to 1.
Figure 16 presents the system performance before and after enabling the control loop. As shown in Figure 16a, under open-loop normal operation, the DC output current increases from 0.92 A to 2.29 A as the DC input voltage rises gradually. After the closed-loop control is activated, the system is regulated with a target current of 1.5 A. As illustrated in Figure 16b, when the DC input voltage increases from 20 V to 40 V, the DC output current is steadily maintained at 1.5 A, and the output current of the inverter remains nearly constant throughout the process.
Figure 16.
Inverter output waveforms at different DC input voltages. (a) Uncontrolled state; (b) controlled state.
In addition to the variable input voltage test, this experiment also conducts control stability tests under variable load conditions. As shown in Figure 17, the input voltage of the system is maintained at 50 V. When the load resistance increases from 20 Ω to 40 Ω, the DC output current remains stable at approximately 1.5 A throughout the test.
Figure 17.
Control waveforms under different loads (normal operation).
5.2.3. System Real-Time Control in Fault Operation
This fault-tolerant topology enables the system to keep operating when an open-circuit fault occurs on a single side of the rectifier. Nevertheless, such asymmetric operation will generate even-order harmonics and degrade the output power quality. As shown in Figure 18, when the DC input voltage of the system rises from 50 V to 100 V, the output current is regulated from 4.54 A (under the rated 100 V input condition) to 3.49 A. After the open-circuit fault of diode D1 occurs, Uab on the faulty side loses the voltage regulation effect of the filter capacitor, and only the healthy branch supplies power to the load. The output current of the system remains stable at 3.48 A. The results verify the feasibility of the proposed topology and control scheme.
Figure 18.
System control and fault−tolerant operation performance.
Figure 19 presents the dynamic response waveforms of the proposed fault-tolerant topology under an open-circuit fault of diode D1. The overall waveform plot captures the complete operating process of the system before and after the fault. The blue curve denotes the load current IL, the yellow curve represents the rectifier input voltage Uab, and the green curve corresponds to the rectifier input current i2. When the open-circuit fault of D1 occurs, the system undergoes a transient process lasting only 0.48 ms, after which it rapidly resumes stable operation.
Figure 19.
Rectifier input voltage and DC output changes during D1 open−circuit fault.
The left detail view shows the waveforms under normal operation before the fault: the load current IL is stably maintained at 3.49 A, the RMS value of Uab is 64.4 V, and the rectifier input current i2 is 3.19 A. The waveforms exhibit no significant distortion, indicating good power quality. The right detail view displays the steady-state waveforms after the fault: the bridge voltage waveform in the faulty channel is significantly distorted due to the loss of voltage regulation from the filter capacitor, with its RMS value rising to 81.1 V and the corresponding i2 dropping to 2.9 A. Despite this, the load current IL remains nearly unchanged at 3.48 A, without noticeable fluctuations.
The experimental results demonstrate that the proposed fault-tolerant topology and control strategy can maintain a stable load current after an extremely short transient period, even when an open-circuit fault occurs in a single branch of the rectifier. This effectively verifies the fault-tolerant capability and operational reliability of the proposed scheme.
6. Discussion
The proposed LC fault-tolerant topology and PI control strategy are well suited for the IPT wireless charging systems of intelligent ships. The GSSA-based model and its reduced first-order equivalent accurately reflect system dynamics, with a steady-state error below 2% after calibration, validating the modeling approach.
Under normal operation, the closed-loop control maintains a stable constant-current output against variations in DC input voltage and load resistance, featuring fast response and strong anti-interference capability. When a single rectifier diode suffers an open-circuit fault, the LC topology suppresses overvoltage, and the system recovers stability within 0.48 ms with nearly unchanged load current. However, asymmetric post-fault operation generates even-order harmonics and degrades power quality, which can be alleviated by additional harmonic suppression circuits or optimized modulation.
PI parameters have obvious coupling effects on steady-state precision, dynamic performance and fault tolerance. Improper parameter settings may cause large ripples or controller saturation. Parasitic parameters of practical devices also slightly weaken constant-current performance, which can be compensated via parameter tuning.
This work only addresses single open-circuit faults of rectifier diodes. Future studies will target short-circuit faults, multi-device composite faults, as well as coil misalignment caused by harsh sea conditions, to develop integrated fault diagnosis and more robust control schemes.
7. Conclusions
Aiming at low modeling accuracy, slow dynamics and poor reliability of marine IPT systems under complex conditions and power device faults, this paper presents a dynamic modeling method, an LC fault-tolerant topology and a PI control strategy. The main conclusions are as follows:
- (1)
- A system nonlinear model is built using complex Fourier series and GSSA. The high-order model is simplified into a first-order dominant model with error less than 2%, offering a reliable reference for the modeling and controller design of switching power electronic systems.
- (2)
- The auxiliary LC topology effectively restrains overvoltage during single-branch open-circuit faults. The system operates continuously with a short transient process, greatly improving fault tolerance and operational safety.
- (3)
- The designed PI control achieves stable constant-current output under variable input voltage and load. It also guarantees steady load current without obvious drop or system instability after faults.
- (4)
- Simulations and experiments verify the superior dynamic performance, steady-state characteristics and fault-tolerant ability of the proposed scheme. The results provide theoretical and technical support for high-reliability wireless charging of intelligent ships.
Author Contributions
Conceptualization, Y.L.; Methodology, Y.L.; Software, Y.L.; Validation, Y.L.; Formal analysis, Y.L.; Investigation, Y.L.; Resources, Y.L.; Data curation, Y.L.; Writing—original draft, Y.L.; Writing—review & editing, Y.L.; Supervision, J.S.; Project administration, P.S.; Funding acquisition, H.Z. and C.C. All authors have read and agreed to the published version of the manuscript.
Funding
This research was funded by National Natural Science Foundation of China under Grant U24A20144.
Data Availability Statement
The original contributions presented in this study are included in the article. Further inquiries can be directed to the corresponding authors.
Conflicts of Interest
The authors declare no conflicts of interest.
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