Conducted Electromagnetic Interference Mechanisms and Mitigation Techniques in SiC Electric Vehicle Traction Inverters: A Review

Abstract

Due to the higher power density of silicon carbide (SiC) inverters in electric vehicles (EVs), effectively managing conducted electromagnetic interference (EMI) has become a vital aspect of inverter design. The complex power topology of SiC inverters increases the complexity of different types, phenomena, and mechanisms of conducted EMI, making the selection of appropriate suppression methods more challenging. Many studies have examined the mechanisms of conducted EMI and their suppression techniques. However, the fast switching transients of SiC devices can affect an automotive traction inverter at multiple physical levels, ranging from the gate-drive circuit and isolation interface to the external power terminals. These phenomena are closely related through their common switching excitation and parasitic coupling networks, but they should not all be interpreted as equivalent conducted-emission phenomena. To provide a structured engineering perspective, this review organizes the relevant disturbances using a source–path–victim framework and examines three representative paths: gate-loop crosstalk, common-mode (CM) coupling across the isolated gate-drive interface, and system-level CM/DM-conducted emissions. The corresponding mitigation techniques and their applicability to EV traction inverters are subsequently reviewed.

1. Introduction

With the development of transportation electrification, SiC MOSFETs are increasingly used in electric vehicle traction systems [1]. Compared with conventional Si IGBTs, SiC devices offer lower switching losses and faster switching transitions, which support higher switching frequencies, higher efficiency, and greater inverter power density [2,3,4,5,6,7]. However, the shorter switching transitions also produce higher voltage and current slew rates. These fast transients excite parasitic capacitances and inductances distributed throughout the power stage, gate-drive circuit, isolation interface, and connected power network, thereby increasing the high-frequency excitation of the system and making electromagnetic interference more difficult to control [4,5]. From an EMC perspective, switching disturbances in power electronic systems can appear as both conducted and radiated interference, and recent reviews have summarized radiated EMI mechanisms and mitigation in power converters [8]. This review focuses instead on switching-induced disturbances and conducted EMI associated with SiC traction inverters. The relevant phenomena include internal coupling effects, such as gate-voltage crosstalk and common mode disturbance across the isolation barrier, as well as common mode (CM) and differential-mode (DM)-conducted emissions at the inverter power terminals.

Figure 1a defines the system boundary considered in this review, including the traction inverter, AC cables, motor, and DC network [9]. The SiC switching stage and its gate circuits are the primary design objects. The motor, cables, battery, and vehicle chassis are included only when their impedances, parasitic capacitances, shielding, or grounding connections influence the CM return path or system resonances. Detailed EMC design of the motor, cable, and complete vehicle is outside the scope of this review.

Figure 1. System boundary and hierarchical organization of switching-induced disturbances in a SiC traction inverter. (a) System boundary of EV traction inverter; (b) locations of three disturbance paths; (c) source–path–victim mapping of gate loop crosstalk (Path A), isolation-interface CM disturbance (Path B), and terminal CM/DM-conducted emissions (Path C).

Although studies have analyzed and improved EMI from the perspective of electric drive impedance modeling and finite element simulation [10,11,12], more focus is placed on the objects affected by EMI and the specific suppression methods in practical engineering. Additionally, the complex structure of the inverter creates many interference paths, which cause disruptions in objects like PWM signals, gate voltages, and three-phase currents. Various interference suppression methods are suited to each disrupted object. This variety of factors makes the existing research lacking in comprehensive analysis and summary of the interference mechanisms and suppression techniques. Moreover, due to space constraints in electric drive systems for EVs, many methods are not appropriate for EV inverters. Current research also lacks a clear summary and analysis of interference mechanisms and suppression methods specific to EV inverters.

From the conventional EMC perspective, conducted emissions at power terminals are generally decomposed into CM and DM components according to their propagation and return paths. The present review retains this conventional classification for system-level terminal emissions. However, fast SiC switching also produces internal electromagnetic coupling that affects the gate-drive and control circuits before the disturbance is observed at an external terminal. Therefore, instead of treating all of these phenomena as equivalent types of conducted EMI, this review adopts the established source, path, and victim framework as the organizing principle [13,14,15]. The disturbance source, coupling path, and sensitive subsystem are identified separately at different physical levels of the traction inverter. Table 1 provides a brief overview of the basic characteristics of the three interference paths.

Table 1. Classification of the three representative disturbance paths considered in this review.

Path	System Level	Disturbance Source	Coupling/Propagation Path	Victim	Main Observable	Relation to Conventional CM/DM
A	Device	High dv/dt	Cgd, common-source and gate loop parasitic inductances	Complementary MOSFET gate	Vgs crosstalk, false turn-on	Local coupling
B	Gate driver	Switching-node dv/dt	Cps, Ciso, isolation and grounding impedances	Low voltage reference, PWM/control circuit	CM current, ground fluctuation, PWM disturbance	Internal CM disturbance
C	Inverter	CM voltage and switching current generated by inverter	DC-link, busbar, cable, motor, heatsink/chassis parasitic network	DC/AC terminals and connected vehicle network	ICM, IDM, conducted emission spectrum	Conventional CM/DM-conducted emissions

Based on this framework, three representative disturbance paths are considered, as illustrated in Figure 1b,c. Path A corresponds to the gate-loop level. The high dv/dt and di/dt generated by commutation are coupled through the Miller capacitance and parasitic inductances into the complementary MOSFET gate loop, resulting in positive or negative gate-voltage crosstalk and, in severe cases, false turn-on or excessive negative gate stress. This phenomenon is treated in this review as an internal gate-loop coupling problem rather than a terminal-conducted emission. Path B corresponds to the gate-driver/isolation-interface level. Switching-node voltage transients couple through the parasitic capacitances of the isolated power supply and gate driver, producing CM current and fluctuations of the low voltage side reference potential. This path is therefore identified as an internal common mode disturbance across the isolation interface. Path C corresponds to the inverter/powertrain level, where switching generated CM voltage and DM current excite the distributed impedance network formed by the DC link, busbars, heatsink/chassis, cables, motor, and associated parasitic elements. The resulting disturbances appear as conventional CM/DM-conducted emissions at the inverter and connected-system terminals. In addition, CISPR 25 specifies representative test methods for conducted emissions from automotive electrical and electronic components, in which the artificial network (AN/LISN), harness arrangement, and ground reference plane jointly define the measurement boundary for terminal noise [16]. Consequently, the measured spectrum of the same inverter may vary with the impedance characteristics of the artificial network, harness length and routing, grounding configuration, probe location, and the settings of the detector and resolution bandwidth (RBW) [17]. Moreover, the measured differential-mode noise in motor drive systems may contain a non-intrinsic DM component produced by coupling through the common mode propagation path [18]. Previous studies have shown that incorporating the inverter, DC link, harness, motor, and their associated parasitic parameters into a system-level equivalent model can provide a more accurate description of the propagation paths and spectral characteristics of CM and DM conducted EMI in high-voltage electric drive systems [19].

This review paper aims to provide an overview of the current state of the art in EMI suppression of EV SiC inverters. The paper is organized as follows: Section 2 analyzes the three disturbance paths and the parasitic parameters that govern their responses. Section 3 compares mitigation methods for the gate loop, isolation interface, source modulation, and EMI propagation path. Section 4 discusses emerging design trends associated with 800 V platforms, higher integration, and adaptive EMI control. The resulting framework links each mitigation technique to its dominant disturbance source, propagation path, and engineering constraints.

2. High dv/dt Induced Disturbance and Conducted EMI Mechanisms in SiC Traction Inverters

2.1. Gate Crosstalk in Half-Bridge Circuits

In the inverter topology, Figure 2 shows the equivalent half bridge used to analyze gate-voltage crosstalk. When the lower device turns on while the upper device remains off, the switching node rises and the drain source voltage of the upper device changes rapidly. The resulting Miller current through C_gdH enters the upper gate loop. Part of this current charges C_gsH, while the remainder flows through the gate impedance, producing a positive disturbance in V_gsH. Hereafter, the subscripts H and L denote the upper and lower MOSFETs, respectively; i_dH and i_dL are their drain currents, and V_dsH and V_dsL are their drain source voltages.

Figure 2. Equivalent circuit of a SiC half bridge for crosstalk analysis.

When the lower device turns off, the direction of the Miller current reverses and a negative V_gsH disturbance is produced. The same mechanism applies to the lower MOSFET when the upper device commutates [20].

The above analysis qualitatively explains how crosstalk occurs in half-bridge circuits. To quantitatively evaluate how each parasitic parameter influences the crosstalk voltage, the switching process in the circuit shown in Figure 2 is modeled and analyzed, with the resulting waveforms presented in Figure 3a. The crosstalk effect can be observed in the frequency spectrum of V_gsH. If the crosstalk signal has a frequency f_crosstalk, as shown in Figure 3c, the noise in V_gsH increases by 10–25% near this frequency, as seen in Figure 3c. The switching transition provides a broadband excitation to the gate loop, whereas the dominant oscillation observed in V_gs is determined primarily by the equivalent gate-loop inductance and capacitance. Therefore, the MHz-range component observed in Figure 3c should be interpreted as a crosstalk ringing or spectral-peak frequency rather than the switching speed. For the circuit conditions reported in [21], the dominant crosstalk-related spectral components occur approximately in the 5–20 MHz range; this range is circuit-dependent and is not a universal characteristic of SiC MOSFET switching.

Figure 3. Theoretical switching waveforms when the crosstalk occurs. (a) Switching timing diagram. (b) The trend definition of V_{gs_on} and V_{gs_off} changes, V_{gs_on} = V_{p_spike} − V_Gate(off), V_{gs_off} = V_{n_spike} − V_Gate(off). (c) Spectrum of V_gsH.

To clarify the relationship between the switching waveforms and the analytical model, the crosstalk process in Figure 3a is divided into several characteristic stages. During t₁–t₂ interval, the dominant disturbance is associated with current commutation and the voltage induced by the common-source inductance. During t₂–t₃, the low side MOSFET enters the Miller plateau and the rapid variation in V_dsL produces a displacement current through C_gdH, which becomes the dominant excitation of the high-side gate loop. The subsequent t₃–t₄ interval describes the natural oscillation and damping of the victim-side gate loop after the switching excitation decreases. The corresponding reverse transition during t₆–t₈ interval follows the same physical mechanisms with opposite voltage and current polarities.

Specifically, during t₁~t₂ interval, the lower bridge begins to conduct, the drain-source current i_dH in the upper bridge decreases, and the drain-source current i_dL in the lower bridge increases. The decrease in the upper bridge i_dH (initial value i_dH0 = I_load) is equal to the increase in the lower bridge i_dL. The di_dH/dt generates a voltage drop across the upper bridge inductor L_SH, which satisfies Equation (1) for the upper bridge gate-drive loop, and V_gsH can be calculated using (1).

$$V_{GATE(off)}=L_{gH}{C}_{gsH}{\displaystyle \frac{d^2{V}_{gsH}}{d{t}^2}}+R_{gH(off)}{C}_{gsH}{\displaystyle \frac{d{V}_{gsH}}{dt}}+V_{gsH}+L_{sH}{\displaystyle \frac{d{i}_{dH}}{dt}}$$

(1)

where the V_GATE(off) is the gate turn-off voltage.

During t₂~t₃ interval, the lower bridge gate-source voltage V_gsL reaches the Miller plateau, causing a rapid drop in V_dsL and an increase in the upper V_dsH. Based on Kirchhoff’s voltage and current laws, the crosstalk expression (2) can be obtained. Because the V_dsH can be expressed in i_dH ($V_{dsH}={\int }_{t3}^t{i}_{dH}dt/C_{XL}$), (2) can be further expressed as (3) [22], in which C_XH represents the parasitic capacitance of the SiC MOSFET on the drain-source loop, expressed as (4). During this crosstalk stage, the C_dsH and C_gsH of the upper bridge charge, leading to a voltage drop across L_SH. As a result, V_gsH acts as a positive voltage crosstalk.

$$\begin{array}{l}{L}_{gH}{\mathrm{C}}_{gsH}{\displaystyle \frac{d^2{V}_{gsH}}{d{t}^2}}+R_{gH}{C}_{gsH}{\displaystyle \frac{d{V}_{gsH}}{dt}}+V_{gsH}\\ =L_{gH}{\mathrm{C}}_{gdH}{\displaystyle \frac{d^2{V}_{dsH}}{d{t}^2}}+R_{gH}{C}_{gdH}{\displaystyle \frac{d{V}_{dsH}}{dt}}-L_{sH}{\displaystyle \frac{d{i}_{dH}}{dt}}+V_{Gate(off)}\end{array}$$

(2)

$$\begin{array}{l}{L}_{gH}(C_{gsH}+C_{gdH}){\displaystyle \frac{d^2{V}_{gsH}}{d{t}^2}}+R_{gL(off)}(C_{gsH}+C_{gdH}){\displaystyle \frac{d{V}_{gsH}}{dt}}+V_{gsH}\\ =({\displaystyle \frac{L_{gH}{C}_{gdH}}{C_{XH}}}-L_{sH}){\displaystyle \frac{d{i}_{dH}}{dt}}+{\displaystyle \frac{R_{gL(off)}{C}_{gdH}}{C_{XH}}}{i}_{dH}+V_{Gate(off)}\end{array}$$

(3)

$$C_{XH}={\displaystyle \frac{C_{gsH}{C}_{gdH}+C_{gsH}{C}_{dsH}+C_{gdH}{C}_{dsH}}{C_{gsH}+C_{gdH}}}$$

(4)

where C_XH denotes the equivalent parasitic capacitance associated with the drain-source loop of the high-side SiC MOSFET. Let C_iss,H = C_gsH + C_gdH, the homogeneous part of (3) can then be written as:

$${\displaystyle \frac{d^2{V}_{gsH}}{d{t}^2}}+{\displaystyle \frac{R_{gH,off}}{L_{gH}}}{\displaystyle \frac{d{V}_{gsH}}{dt}}+{\displaystyle \frac{1}{L_{gH}{C}_{iss,H}}}{V}_{gsH}=0$$

(5)

Comparing this expression with the standard second-order form:

$${\displaystyle \frac{d^{2}x}{d{t}^2}}+2{\zeta }_H{\omega }_{n,H}{\displaystyle \frac{dx}{dt}}+{\omega }_{n,H}^{2}x=0$$

(6)

The natural angular frequency of the victim-side gate loop ω_H and its dimensionless damping ratio ζ_H can be derived as shown in (7).

$$\left\{\begin{array}{c}{\omega }_H={\displaystyle \frac{1}{\sqrt{L_{gH}(C_{gsH}+C_{gdH})}}}\\ {\zeta }_H={\displaystyle \frac{R_{gH(off)}}{2}}\sqrt{{\displaystyle \frac{C_{gsH}+C_{gdH}}{L_{gH}}}}\end{array}\right.$$

(7)

During t₃~t₄ interval, the V_gsH oscillates and decays.

During t₆~t₇ interval, V_gsL decreases to the Miller plateau while V_dsL rises and V_dsH drops. This causes C_dsH and C_gsH capacitors to discharge, with V_gsH changing in a resembling t₂~t₃. Therefore, the crosstalk response of V_gsH can also be described by (2). In the t₇~t₈ phase, V_gsH fluctuations satisfy (1).

Under inverter operating conditions, if the peak positive crosstalk voltage V_{gs_on} exceeds the gate threshold voltage of the MOSFET, it causes the upper bridge MOSFET to turn on incorrectly, thus affecting the inverter’s output current. If the peak negative crosstalk voltage V_{gs_off} exceeds the maximum withstand voltage of the negative gate voltage, the MOSFET may be damaged. Therefore, it is necessary to limit the spikes of the crosstalk voltage. Equation (2) represents a second-order nonhomogeneous differential equation with respect to V_gs, where the response amplitude primarily depends on the forcing terms R_gHC_gdHdV_ds/dt and L_sHdi_dH/dt on the right-hand side. The influence of the d²V_ds/dt² term proves negligible due to its substantially smaller coefficient compared to the other terms.

Combining (1) and (2), the factors influencing each parameter in the drive loop on crosstalk are summarized in Table 2. The waveforms of V_{gs_on} and V_{gs_off} are shown in Figure 3a.

Table 2. Impact of circuit parameters on crosstalk voltages.

Parameters	Positive Crosstalk Vgs_on	Negative Crosstalk Vgs_off	Explanation	Refs.
LsH	↑	↑	During the positive and negative crosstalk periods, didH/dt is always negative. Although the increase in LsH slightly reduces the rate of current change, the term -LsdidH/dt on the right side of Equation (2) still shows an increasing trend. Therefore, as LsH increases, both VgsH and Vgs_off increase accordingly.	[23]
LsL	↓	↓	Increasing the LsL limits VgsL variation, reducing MOSFET switching speed, and lowering VdsL and idL variation. It also slows the voltage-current rate change for the complementary MOSFET, suppressing CgdH Miller current and LsH voltage. Other methods, like increasing RgL and CgsL, also slow switching to reduce crosstalk, but can significantly alter the lower bridge MOSFET waveform.	[22,24]
Lg	—	—	The impedance of Lg is small compared to the gate resistance Rg, and the effect is negligible.	—
CgsH	↓	↓	According to (4), CgsH, together with CgdH, determines both the natural frequency and damping ratio of the victim-side gate loop. Increasing CgsH decreases ωn,H and increases ξH under otherwise fixed circuit parameters.	[20,25]
CgdH	↑	↑	The increase in CgdH leads to a rise in Miller current, which results in an increase in positive crosstalk spikes during turn-on and negative crosstalk spikes during turn-off.
RgH	First ↑ and then ↓	↓	Increasing $R_{gH}$ reduces both |dVds/dt| and |did/dt|. Because the Miller term RgHCgdHdVdsH/dt initially increases with RgH and subsequently decreases as the slew rate is reduced, the positive crosstalk voltage shows a nonmonotonic trend. During negative crosstalk, the combined Miller and source inductance contributions decrease over the investigated range, so the negative spike is reduced.	[20,22,23]

Note: ↑ and ↓ indicate an increase or decrease in the listed response when the corresponding parameter increases, with the remaining circuit parameters and operating conditions held constant. The arrows indicate qualitative sensitivity trends rather than fixed percentage changes.

2.2. Common-Mode Disturbance in Isolated Gate-Drive Circuits

In the SiC MOSFET driving circuit, because of the floating MOSFET source potential, the gate driving signal requires level shifting and isolation of the PWM control signal [26]. The shifted level is generated by an isolated auxiliary power supply, as shown in Figure 4. Here, GND1 and GND2 are the reference grounds for the low-voltage and high-voltage sides, respectively. Since they are not perfectly isolated, Z1 is typically added to represent the parasitic impedance between them. The primary-secondary parasitic capacitance of the isolated power supply, C_ps, results from the parasitic capacitance of the isolation device itself, typically in the pF range. The isolated gate driver parasitic capacitance is C_iso. If a voltage disturbance occurs on the high-voltage side, a CM current, I_CM, is generated on the low-voltage side. Due to the low voltage of the PWM signal, it might be missed if disturbed [27]. Therefore, C_iso and C_ps must be strictly limited to maintain the integrity of the PWM signal.

Figure 4. Conventional structure gate driver architecture considering parasitic components.

The drain-source voltage slew rate dV_ds/dt associated with SiC switching produces a rapid variation in the potential between the floating high-voltage-side domain and the low-voltage-control domain. This transient excites displacement currents through the parasitic capacitances crossing the isolation barrier. As illustrated in Figure 4, the main capacitive coupling paths considered here are the primary-to-secondary capacitances of the isolated auxiliary supply and the isolation-barrier capacitance of the gate driver. In the physical circuit, these capacitances are connected to different nodes on the isolated secondary side. Therefore, their contributions are first expressed separately. The total displacement current of isolated auxiliary supply and gate driver can be written as:

$$\left\{\begin{array}{l}{i}_{ps}={\displaystyle \sum _k{C}_{ps,k}\frac{d\left(v_{\mathit{sec},k}-v_{GND1}\right)}{dt}}\\ i_{iso}=C_{iso,CM}{\displaystyle \frac{d\left(v_{drv,\mathit{sec}}-v_{drv,pri}\right)}{dt}}\end{array}\right.$$

(8)

where C_ps,k denotes the distributed primary-to-secondary capacitance associated with the $k$-th secondary-side conductor, such as the V_CC, V_EE, and transformer-winding nodes. During a fast CM transient, the isolated DC-DC secondary and the output side of the gate driver form a floating high-voltage-side domain referenced to GND2. With sufficient local decoupling, the differential supply voltages V_CC-GND2 and V_EE-GND2 vary much more slowly than the CM transition of GND2. Therefore, it can be assumed that dv_sec,k/dt = dv_drv,sec/dt = dv_GND2/dt. Defining v_CM,iso = v_GND2 − v_GND1, the total CM displacement current injected into the low-voltage side can be approximated as (9). During the commutation transient, GND2 roughly follows the potential at the switch node; thus, v_CM,iso ≈ v_SW.

$$i_{CM}=i_{ps}+i_{iso}=\left(C_{ps,CM}+C_{iso,CM}\right){\displaystyle \frac{d{v}_{SW}}{dt}}$$

(9)

Figure 5a shows the fluctuations in the isolated power supply as the device switches. As illustrated in Figure 5b, the spectrum of the coupled CM current is broadband. In the experimental results reported in [28], pronounced spectral components occur approximately in the 5–30 MHz range. These components should be interpreted as dominant CM spectral peaks associated with the switching-edge excitation and the resonant characteristics of the coupling network.

Figure 5. (a) Isolated supply voltage fluctuation of the upper bridge when the lower bridge is switching. (b) Spectrum of $I_{CM}$ coupled to the low voltage side [28].

In the SiC inverter, the isolated gate driver circuit of the half-bridge topology is shown in Figure 6a. The C_HS and C_LS capacitors form a low-impedance path. The isolated auxiliary supply is simplified to an LC model [29,30], with an equivalent circuit shown in Figure 6b. If the dV_ds/dt generated by the high-side or low-side device switch is regarded as the excitation signal, the ratio of the CM currents on the low-voltage side (I_NoiseGND1) and high-voltage side (I_NoiseGND2) can be derived as shown in (10) [31,32]. The direction of the current is indicated by the red arrow in Figure 6b.

Figure 6. Conventional structure gate driver in half bridge: (a) Gate driver architecture considering parasitic components; (b) CM interference propagation paths in equivalent circuit.

$${\displaystyle \frac{I_{NoiseGND1}}{I_{NoiseGND2}}}={\displaystyle \frac{Z_s+2\pi f{L}_{wiring\_LS}}{2\pi f{L}_{wiring}}}$$

(10)

where Z_s represents the equivalent impedance of the isolation C_ps capacitance and C_iso, and the stray inductance between the isolation module and the device pins is L_{wiring_LS}. Additionally, L_wiring is the stray inductance of the low-voltage ground. The common-mode current coupled across the isolation interface is driven by the voltage slew rate of the floating high-side domain. A shorter switching transition time generally corresponds to a broader excitation spectrum. However, the resulting CM-current spectrum is also shaped by the parasitic capacitances and impedances of the isolation and low-voltage return networks. Therefore, the MHz-range spectral components observed in the gate-driver circuit should be determined from the combined switching edge spectrum and CM transfer impedance.

The analysis of (9) and (10) shows that the factors affecting the conducted EMI of the isolated gate driver are summarized in Table 3.

Table 3. Parameters affecting isolated gate driver.

Parameters	Influence	Physical Interpretation	Refs.
Cps	ICM  $\uparrow$	Primary–secondary capacitance of isolated auxiliary supply; larger Cps increases the displacement-current branch	[26,27,28,29,30,31,32,33]
Ciso	ICM  $\uparrow$	Isolation-barrier capacitance of gate driver; contributes in parallel with Cps in the lumped CM model	[31]
dvCM,iso/dt	ICM  $\uparrow$	Direct excitation term in (9)	—
Z1/ZM	Vnoise,LV for larger transfer impeance	Determines conversion from injected CM current to low-voltage ground/PWM disturbance	[27,29]

Note: ↑ indicate that the common-mode current is aggravated, as the corresponding parameter increases, with other conditions unchanged.

2.3. CM/DM-Conducted Emissions in Electric Drive Systems

In the electric drive system, parasitic capacitance in the heat sink, motor housing, and other components, along with parasitic inductance in the connecting wires, create an equivalent circuit shown in Figure 7a. The voltage and current transitions generated during MOSFET commutation constitute the principal high-frequency excitation sources. Based on the noise propagation path, it can be classified into CM interference (red path) and DM interference (blue path), as indicated in Figure 7a. Along the CM path, switching voltage excites displacement current through the parasitic capacitances between the inverter, motor, cable, and chassis. The drain-source voltage of the Q1 MOSFET during inverter operation is shown in Figure 7b [34], while the DC bus current is depicted in Figure 7c.

Figure 7. Conducted EMI modeling of three-phase power converters at high frequencies: (a) Equivalent circuit for CM and DM coupling paths. (b) Switching voltage V_ds of Q1. (c) I_DC and I_DM caused by switching of each phase on the DC side [34].

The inverter’s CM voltage V_CM is shown in Figure 7b. Variations in V_CM during MOSFET switching can cause interference in the electric drive system by creating a CM interference loop through the parasitic capacitance. The equivalent circuit for single-phase CM interference is illustrated in Figure 8a [35], where parasitic elements such as the distributed inductance of the AC cables, MOSFET drain-source capacitance, and inter-cable capacitance are combined into Zeq/3. Additionally, the CM model of the electric drive system can be simplified to the circuit in Figure 8b [36], with the symmetry of the structure allowing a quantitative description of V_CM and I_CM using (11).

$$\left\{\begin{array}{c}{I}_{CM}={\displaystyle \frac{1}{\frac{Z_{eq}}{3}}}{V}_{CM}\\ V_{CM}={\displaystyle \frac{V_{CM1}+V_{CM2}+V_{CM3}}{3}}\end{array}\right.$$

(11)

Figure 8. (a) CM circuit configuration for a part of the inverter in frequency domain [35]. (b) CM equivalent schema. (c) CM source based on standard PWM wave. (d) CM Noise Spectrum Schematic.

The MOSFET switching equivalent voltage source V_CM can be approximated by a periodic trapezoidal pulse with finite rise and fall times, as shown in Figure 8c. For frequency-domain analysis, V_CM is represented by a truncated complex Fourier series. To avoid the singularity at n = 0, the DC component is treated separately from the nonzero harmonic components:

$$\left\{\begin{array}{l}{V}_{CM}\left(t\right)=V_{CM,0}+2\mathit{Re}\left[{\displaystyle \sum _{n=1}^N{V}_{CM,n}{e}^{jn{\omega }_{s}t}}\right], {\omega }_s={\displaystyle \frac{2\pi }{T_s}}\\ V_{CM,0}={\displaystyle \frac{V_{dc}}{T_s}}\left(t_{off}-t_{on}-{\displaystyle \frac{t_r}{2}}+{\displaystyle \frac{t_f}{2}}\right)\end{array}\right.$$

(12)

and for n ≥ 1,

$$V_{CM,n}={\displaystyle \frac{V_{dc}{\displaystyle \sum _{i=0}^{N-1}\left(Sa\left(\frac{t_{f}n}{T_s}\right)\cdot e^{-\pi jn\frac{2t_{on,i,p}+t_f}{T_s}}-Sa\left(\frac{t_{r}n}{T_s}\right)\cdot e^{-\pi jn\frac{2t_{off,i,p}+t_r}{T_s}}\right)}}{-2\pi jn}}$$

(13)

where is the DC-link voltage, T_s is the switching period, t_on and t_off denote the starting instants of the rising and falling transitions, respectively, and t_r and t_f are the corresponding rise and fall times. $n$ denotes the harmonic order, N is the truncation order of the Fourier series, and Sa(x) = sin (x)/x [37]. The exponential terms describe the phase positions of the rising and falling edges, whereas the Sa(·) terms determine the attenuation of the high-order harmonics associated with the finite switching transition times. Figure 8d shows that the CM conducted EMI is distributed over a broad frequency range and generally attenuates with increasing frequency, while a resonance peak remains around 10 MHz due to the frequency-dependent CM propagation network.

DM interference is represented by a differential-mode current I_DM on the DC bus side of the electric drive system, as shown in Figure 7c. The equivalent circuit for DM interference in a single phase is illustrated in Figure 9a [35]. The load inductance displays high impedance at high frequencies and can be considered open-circuited; therefore, it is not shown in the diagram. Additionally, the design of the DC bus must account for the mutual inductance between the DC bus and the phase wiring harness. For the equivalent current source I_DM, it can be similarly described as a sequence of square waves, as shown in Figure 9b, with its expression satisfying (14) assuming t_r = t_f. As shown in Figure 9c, the DM conducted-emission spectrum extends over the full 150 kHz–30 MHz band. The measured curve rises in the MHz range and exhibits two pronounced resonance peaks, reflecting the frequency-dependent resonant characteristics of the motor-drive impedance network, before decreasing at higher frequencies. This indicates that the observed DM spectrum is determined jointly by the equivalent PWM current source and the system impedance network. Similar source-network analytical prediction concepts have also been reported for SiC motor-drive EMI analysis [38].

$$I_{DM}=2I_{amp}D\cdot Sa\left(n\pi D\right)\cdot Sa\left(n\pi t_f/T\right)$$

(14)

$$f_c=1/\left(\pi \cdot \mathit{min}\left(t_r,t_f\right)\right)$$

(15)

where D is the duty cycle, T is the inverter switching period, I_amp is the current amplitude, and n represents the harmonic order. Figure 10 summarizes the different roles of the switching-edge and PWM parameters in the spectrum of an idealized periodic pulse waveform [39]. As shown in Figure 10a, the noise attenuation characteristics at both low and high frequencies can be described by the corner frequency, where f_c is expressed as in (15) [33]. As shown in Figure 10b, reducing the t_r and t_r, or equivalently increasing the voltage/current slew rate, shifts the transition-related corner frequency toward higher frequencies. Consequently, appreciable switching-edge spectral content extends further into the MHz range. This effect is distinct from changing the switching frequency f_s. As illustrated in Figure 10c, f_s determines the spacing and locations of switching-related harmonics, whereas the amplitudes of individual harmonics depend on the pulse waveform and modulation strategy. The duty ratio D further changes the harmonic coefficients rather than uniformly increasing all spectral components as shown in Figure 10d.

Figure 9. (a) DM circuit configuration for a part of the inverter; (b) DM source based on standard PWM wave; (c) DM Noise Spectrum Schematic.

Figure 10. Effects of pulse waveform parameters on the spectral envelope (a) representative spectrum; (b) transition time; (c) switching frequency; (d) duty ratio [39].

For short interconnections and relatively low frequencies, the lumped parameter models shown in Figure 7, Figure 8 and Figure 9 are generally sufficient to describe the dominant CM and DM propagation paths. As the switching transitions of SiC devices become faster and the motor cable length increases, however, cable propagation delay can no longer be neglected, and the high-frequency behavior is more appropriately represented using a distributed parameter model. For a cable characterized by the per unit length parameters $R^{\prime }$, $L^{\prime }$, $G^{\prime }$, and $C^{\prime }$, the characteristic impedance, propagation constant, and load-end reflection coefficient can be expressed as in (16).

$$\left\{\begin{array}{l}{Z}_0\left(f\right)=\sqrt{{\displaystyle \frac{R^{\prime }+j2\pi L^{\prime }}{G^{\prime }+j2\pi C^{\prime }}}}\\ \gamma \left(f\right)=\sqrt{\left(R^{\prime }+j2\pi L^{\prime }\right)\left(G^{\prime }+j2\pi C^{\prime }\right)}\\ {\Gamma }_L\left(f\right)={\displaystyle \frac{Z_L\left(f\right)-Z_0\left(f\right)}{Z_L\left(f\right)+Z_0\left(f\right)}}\end{array}\right.$$

(16)

Accordingly, the cable length, characteristic impedance, and high-frequency impedance at the motor terminals determine not only the reflected overvoltage but also the resonant frequencies of the CM propagation network. Experiments on SiC motor drives have shown that fast switching edges and cable impedance mismatch can significantly affect both motor terminal overvoltage and switching loss [40]. More recent approaches, including active reflection cancelation [41] and the motor-side smart coil [42], exploit the propagation characteristics of the cable and process only the transient energy associated with commutation. This principle can reduce the size and power handling requirements of conventional output filters.

Cable shielding also changes the distribution of CM current. A study of a complete SiC EV powertrain showed that the length and type of the AC cable, as well as whether the DC cable is shielded, can substantially alter the system CM EMI spectrum [43]. The shield increases high-frequency coupling between the conductors and the vehicle body or enclosure. Although this can reduce the potential at certain motor terminals, it may simultaneously increase the CM current returning through the chassis. For example, in experiments with a 3 m cable, replacing an unshielded cable with a shielded cable increased the stator to ground current by approximately 25%, while the bearing voltage and bearing current decreased by about 5%. When the shielded cable length was further increased from 3 m to 10 m, the bearing voltage decreased by approximately 11%, whereas the stator to ground current increased by about 14% [44]. Related review studies have likewise indicated that cable shielding can mitigate some rotor- and bearing-related disturbances while increasing the stator to ground the CM current [45].

The influence of motor and enclosure parasitic parameters is also strongly frequency-dependent. Distributed capacitances between the winding and stator, rotor and bearings, and motor enclosure give rise to multiple resonances in the CM and DM impedances within the MHz range. Recent broadband impedance modeling has extended the valid characterization range of motor CM, DM, and phase to ground impedances from 100 Hz to 120 MHz, with the average magnitude error maintained within approximately 2.96 dB for motors of three different power ratings [46]. For a complete PMSM drive system, the experimental and modeling results in [47] showed that, on the investigated platform, the CM current in the range of approximately 150 kHz to 3 MHz was mainly governed by the motor impedance, whereas cable and inverter parasitic paths became increasingly dominant at higher frequencies. This result also indicates that the relative importance of individual system components cannot be represented by a fixed ranking across the entire EMI frequency range.

As traction systems become more highly integrated, parasitic elements that were previously distributed among separate subsystems become more strongly coupled. A recent study of an EV all in one motor drive module [48] showed that the stray inductance of the DC busbar and the capacitances of a multiport bus structure can form additional CM resonance paths, and that the dominant parameters can be identified through sensitivity analysis. The parasitic capacitance between the switching node of the power module and the heatsink or enclosure also follows the approximate relationship i_CM,pkg ≈ C_sw-chdv_sw/dt. By optimizing this parasitic capacitance in a SiC power module, the experimental study in [49] achieved an approximately 17 dB reduction in CM current while simultaneously reducing the total switching loss by 28.5%.

In automotive traction inverters, the PWM switching frequency f_s is typically in the order of tens of kilohertz, while SiC devices permit higher switching frequencies than conventional Si IGBTs because of their reduced switching losses [50]. The discrete spectral components generated by PWM occur at f_s and its harmonics nf_s, whereas the finite rise and fall times of individual switching transitions determine the spectral envelope at high frequencies. In addition, parasitic LC networks in the module, busbar, cable, motor, and chassis paths can produce resonances in the MHz range. Consequently, MHz range EMI components should be attributed to the combination of fast-edge excitation and system resonances [37]. Table 4 lists some of the factors that affect the frequency spectrum of conducted EMI noise.

Table 4. Physical roles of switching parameters in the conducted-EMI source spectrum.

Parameters	Unit	Primary Spectral Effect	Interpretation	Refs.
Switching frequency fs	kHz	Sets the spacing and location of switching harmonics nfs	Does not by itself define the high-frequency spectral bandwidth	[51,52]
Rise/fall time tr, tf	ns	Determines transition-related corner frequency fc	Shorter transitions extend appreciable spectral content to higher frequencies	[39]
Voltage/current slew rate dv/dt, di/dt	V/ns, A/ns	Determines excitation strength of capacitive/inductive coupling	Higher slew rates generally increase excitation of parasitic CM/DM paths	[15]
Duty ratio D	—	Changes harmonic coefficients of the periodic pulse	Effect is harmonic-order-dependent and not uniformly monotonic	[53,54]
Parasitic network (Leq, Ceq, Req)	—	Determines resonance/ringing frequencies and amplification	Depends strongly on package, busbar, cable, motor, filter and grounding	[38,55]

3. Mitigation of Switching-Induced Disturbances and Conducted EMI

3.1. Crosstalk in Half-Bridge Circuits

Section 2.1 shows that the primary excitation of gate crosstalk in a half-bridge circuit is the rapid voltage and current transition associated with SiC MOSFET commutation. The resulting dV_ds/dt and di_d/dt are coupled into the complementary gate loop through the Miller capacitance and parasitic inductances, producing gate-voltage disturbance.

The current crosstalk suppression methods for half-bridge circuits can be categorized into two types. The first method targets the propagation path [56] and reduces interference by adding Miller clamping circuits, which absorb the energy of the Miller current flowing through the gate. The second method addresses the interference source itself by actively adjusting the gate driving capability of the SiC MOSFETs based on operating conditions, which helps to reduce dV_ds/dt and suppress gate-voltage crosstalk in the complementary MOSFET.

3.1.1. Miller Clamp Circuit

Miller clamp circuits are among the most common and cost-effective methods for addressing crosstalk issues. These circuits establish a low-impedance path between the gate and the source, either bypassing the Miller current or clamping the gate voltage to the negative rail voltage. Typically, the driver IC includes an integrated Miller clamp circuit, though it can also be implemented using discrete components. Miller clamps are categorized based on the triggering method into two main types: passive [57,58,59,60,61,62,63] and active [64,65].

• Active Miller clamp

Active Miller clamp circuits usually regulate an auxiliary transistor using a specific control strategy that adjusts the external gate resistor or pulls the gate voltage down to a negative drive voltage or ground. A common method is to compare the indicated parameter with a reference voltage, which then produces a control signal [66]. The parameter typically monitored in active Miller clamp circuits is the gate voltage, with a reference voltage that does not surpass the gate threshold voltage [67].

Another method for active Miller clamping is clamp control based on the switching logic signals of SiC MOSFETs. In [68], the gate auxiliary circuit includes two diodes and two auxiliary MOSFETs with opposing logic, whose control signals must be synthesized from the switching logic signals of the SiC MOSFETs. The auxiliary circuit in [69] and its logic signals are shown in Figure 11. This setup introduces an auxiliary capacitor to help share charging and discharging currents flowing through C_gs. The auxiliary capacitor provides a low-impedance path while increasing the gate charge [70].

Figure 11. Gate impedance adjustment circuit using buffer capacitor: (a) circuit schematic; (b) corresponding logic signals of main device and auxiliary transistor [69].

2.

Passive Miller clamp

In passive Miller clamp circuits, the timing of intervention is determined by changes in the monitored parameters of the drive loop, which depends on passive elements and auxiliary transistors. Ref. [57] proposes a resistor-capacitor-diode (RCD)-based passive clamp circuit as shown in Figure 12. The RCD circuit is placed between the gate and source terminals. It operates as follows: when positive crosstalk occurs, as shown in Figure 12a, the Miller current flows through R_exth, making Q_clp conductive, which creates a low-impedance loop path and charges the C_clp capacitor, helping to reduce the influence of the Miller current on V_gate. When negative crosstalk occurs, it is observed to charge C_gd via the C_clp capacitor and diode D_clp, as shown in Figure 12b, which helps suppress the crosstalk. Based on similar principles, RCD-derived level-shifting and auxiliary clamping circuits have been developed to generate an appropriate negative turn-off voltage and/or provide a low-impedance path for the Miller current, thereby limiting the gate crosstalk voltage [63,71,72,73,74,75]. Active clamping methods triggered by the switching transient provide another implementation route [64].

Figure 12. Passive Miller clamp circuit: (a) positive crosstalk; (b) negative crosstalk [57].

3.1.2. Active Gate Driver

Active gate drivers (AGDs) regulate the switching trajectory by adjusting gate voltage, gate current, resistance, or capacitance according to the switching state or measured electrical variables. Their main design objective is to limit crosstalk, overshoot, and ringing while controlling switching loss [76]. The methods reviewed here are grouped according to the controlled gate parameter and the use of open or closed loop feedback.

• AGD methodologies based on parameter tuning

In the case of SiC MOSFETs, the switching speed can be appropriately limited to reduce crosstalk. Based on differences in adjustment parameters, the AGD methods can be classified into four types.

VGSDVC (Variable Gate-Source Driving Voltage Circuit): The purpose of the VGSDVC is to directly adjust the gate-voltage trajectory during the switching process of SiC MOSFETs. Conventional implementations generally use predetermined gate-voltage levels or trajectories [77,78]. The AGD proposed in [79] uses three cascaded gate-drive buffers as multilevel selectors, as shown in Figure 13. The microcontroller controls access to the impedance and n resistors, which can be adjusted in 2ⁿ levels. This approach aligns with the principles of DAC and is implemented in two ways: one involves using an external resistor network as described above; the other employs an internal programmable amplifier, with its gain adjusted via software.

Figure 13. Active gate drive with adjustable gate voltage, the circuit consists of microcontroller, adjustable voltage regulator, voltage selector and current absorption circuit [79].

CGCC (Controlled Gate Current Circuit): The controlled gate current method mainly controls gate charge injection by adjusting the charge and discharge currents to the input capacitor C_iss. Its functions have been validated in [80,81,82,83,84]. A common approach involves connecting a current source branch to the gate, as shown in Figure 14. When the peak dV_ds/dt exceeds the threshold V_ref1 set by the microcontroller, V_Q1 conducts, and the current mirror output i_c is injected into the gate branch of the DUT [85]. The commanded gate current can also be generated from a programmable voltage stage, allowing the current level to be adjusted during different switching intervals.

Figure 14. Double closed-loop self-regulating AGD, consisting of control signal generating circuit, voltage controlled current source, peak sampling system and dV_ds/dt sampling circuit [80].

VGRC (Variable Gate Resistance Circuit): As discussed in 2.1, increasing the gate resistance for the Miller plateau interval effectively reduces the dV_ds/dt of the MOSFET while also setting an appropriate resistance value of interference devices, which helps lower gate-voltage crosstalk. The most common approach involves using a combination of multiple gate resistors and switches [86,87,88]. As shown in Figure 15, the microcontroller detects the switching stage by monitoring dV_ds/dt and adjusts the gate resistance accordingly by controlling the switching signal at various MOSFET switching stages.

Figure 15. Typical circuitry of variable gate resistance method [89].

VGSCAC (Variable Gate-Source Capacitor Assisted Circuit): The variable gate capacitance method controls the Miller current shunt by adjusting the value of C_gs/C_gd, which regulates the Miller plateau duration and enables the regulation of switching speed. However, a C_gs that is too large can lead to increased switching delays in the SiC MOSFET and can also result in peak gate currents that exceed the gate oxide stress limit [90]. To prevent this, it is necessary to adjust the timing of connecting the external gate capacitor to the gate-source using a control switch, as shown in Figure 16 [91,92]. Additionally, placing the gate resistor in parallel with the speed-up capacitor [93,94], as shown in Figure 16, can increase the MOSFET switching speed, reduce switching losses, and suppress surge voltages.

Figure 16. Typical variable input capacitance active gate driver structure.

2.

Control Strategies for AGD

Ensuring that power devices operate optimally with open-loop methods [86,95,96] remains challenging. Closed loop AGD introduces sensing and feedback so that the switching trajectory can be adjusted during operation [97]. The principle of AGD based on feedback control is illustrated in Figure 17 [98].

Figure 17. Block diagram of the measurement-based control [98].

By compensating for the error between the reference and feedback signals, the switching process can be actively controlled using the methods described above for adjusting the gate loop parameters [99]. Due to the rapid switching speed of SiC MOSFETs (10~100 V/ns), high resolution (sub-nanosecond delay) is also necessary for the acquisition circuit [100]. With a sufficient sampling rate of the sensing circuit and ADC, dV_ds/dt and di_d/dt are used as the indicated parameters to be controlled by PI controller to eliminate the system’s steady-state error [101].

It has been demonstrated that AGD feedback circuits can worsen crosstalk [102]. To address this, ref. [103] analyzes the mechanism of crosstalk caused by feedback circuits using the equivalent capacitance model and proposes a Crosstalk Suppression (CTS) circuit. As shown in Figure 18, the CTS effectively blocks the Voltage-Control-Current-Source (VCCS) when the MOSFET is in the freewheeling state, thus preventing crosstalk.

Figure 18. Circuit diagram of the closed-loop ACSD with CTS to suppress crosstalk [103].

This section covers techniques for crosstalk suppression in half-bridge circuits. Many manufacturers are now offering gate drivers with AGD functionality. To give readers a complete overview of inverter design, Table 5 provides a clear summary of EMI suppression methods between half-bridges and their current uses in commercial gate drivers.

Table 5. Comparison of gate loop crosstalk mitigation strategies for SiC half-bridge circuits.

Strategy	Main Implementation	Crosstalk Suppression	Cost	Integration	Refs.
Low-impedance clamp	Auxiliary capacitor + self-triggered transistors; negative-biased turn-off path	Crosstalk suppression verified with 1200 V SiC MOSFET under varying operating conditions	Low–Med.	High	[58]
	Two auxiliary capacitors reduce turn off gate impedance and bypass Miller current	Effective for both Kelvin and non-Kelvin packages	Low	High	[62]
	RCD level shifter provides a self-driven Miller current bypass	Crosstalk suppressed without extra control signal; switching loss reduce up to 16.6%	Low–Med.	High	[63]
Active Miller clamp	dv/dt detected low level active clamp	600 V/15 A, Ra = 10 Ω: positive Vgs spike ↓ 67.9%, negative spike ↓ 52.5%; total loss ↓ 3.3%	Med.	Med.-High	[64]
	Bipolar AMC bypasses both gate and source side return impedances	False turn-on suppressed in parallel 1.2-kV SiC modules; gate voltage maintained within safe range	Med.	Med.	[65]
Active gate driver (AGD)	Switching state dependent gate-loop impedance/voltage control	Crosstalk suppression with turn-on switching loss reduce up to 17%; negative gate spike reduced without slowing switching	Med–High	Med.	[69]
	Double closed loop gate current regulation using peak-voltage feedback	500 V/40 A: $V_{ds}$ overshoot ↓ 30.5%; turn-off loss ↓ 75% vs. fixed-current AGD	High	Low–Med.	[80]
	Multi-variable/programmable slew rate control framework	Enables dv/dt, di/dt, EMI and switching loss co-optimization; method dependent	High	Low–Med.	[98]

Note: ↓ indicates a reduction in the corresponding crosstalk related quantity relative to the reference or baseline case under the reported test conditions.

3.2. Common-Mode Current Suppression in Isolated Gate Driver

3.2.1. Internal Structure of Isolated Gate Driver

Equation (9) shows that CM current across the isolation interface is directly proportional to the effective coupling capacitance. For transformer-based auxiliary supplies, this capacitance is governed mainly by the overlap area, spacing, and electric field distribution between the primary and secondary windings. Planar PCB transformers can therefore be optimized to reduce coupling capacitance while satisfying power density, insulation, and loss requirements [104,105,106]. Ref. [107] proposes a PCB embedded isolated auxiliary supply that takes the transformer volume, loss, and isolation capacitance as optimization objectives and is designed through a Pareto optimal solution surface.

Additionally, one of the most effective ways to optimize the integrated structure of the PCB is to add a Faraday shield [108], whose principle is shown in Figure 19. In this method, a properly grounded conductive sheet is placed at an appropriate location between the windings to shunt the CM current.

Figure 19. CM-current flow path in transformers. (a) Without shielding (b) with grounded electrostatic shield. (c) PCB-based winding structure with shielding layer.

3.2.2. External Structure of Isolated Gate Driver

Designing a transformer reduces parasitic coupling capacitance and improves CM rejection, but PCB layout and additional design costs must be considered. Although commercially available isolated auxiliary power supplies or gate drivers can enhance integration, parasitic coupling capacitance remains a key limitation. Based on this, the following section summarizes how to mitigate CM interference of the gate driver through external structural improvements.

Adding a CM choke on the low voltage side is a common way to suppress CM interference in gate drivers. The selection of the choke needs to take into account both CM and DM characteristics [109,110]. Figure 20 illustrates that when p = C, Z_C represents the CM impedance, and K_c is the coupling coefficient with K_C = 1. Moreover, when p = D, Z_D represents the DM impedance, and K_D is the coupling coefficient with K_D = −1. This modeling decouples CM interference and DM interference.

Figure 20. Equivalent circuit for a single-phase choke. (a) Common-mode and differential-mode decomposition of the choke impedance, where Z_C and Z_D represent the corresponding modal impedances (K_C = 1, K_D = −1). (b) Equivalent circuit of the unit section Z_pi. (c) Cascade representation of the overall choke model.

The impedance of the choke to CM interference can be expressed as (17).

$$Z_{CM}=R_0+{\displaystyle \sum _{i=1}^{N_C}\frac{j\omega R_{Ci}{L}_{Ci}}{R_{Ci}-2{\omega }^2{R}_{Ci}{L}_{Ci}{C}_{Ci}+2j\omega L_{Ci}}}$$

(17)

where N_C is the number of choke winding turns, which corresponds to the number of impedance blocks Z_pi in Figure 20c; R_CI is the core resistance to characterize the hysteresis and eddy current losses; C_ci is the capacitance inside the winding; L_ci is the winding inductance; and R₀ is the external resistance. The curve of $\left|Z_{CM}\right|$ with f usually has one or more resonance peaks, so the choke achieves better suppression only for CM noise in a specific frequency range.

In the conventional half-bridge gate driver structure illustrated in Figure 6a, each driver is powered by a discrete, isolated power supply. As discussed in Section 2.2, it is necessary to create a path with reduced CM interference for I_NoiseGND2, which helps direct CM current back to the high-voltage side, thereby reducing interference on the low-voltage side signal. Based on this principle, a common approach is to cascade multiple isolated supplies to enable CM-current shunting, as shown in Figure 21a [28]. As seen in the current path diagram in Figure 21b, this topology achieves gradual attenuation of CM through a series cascading configuration of power supply branches.

Figure 21. Cascaded gate driver in half bridge. (a) Cascaded gate driver power supply configuration. (b) Equivalent circuit for Cascaded gate driver [28].

Table 6 compares representative CM-current mitigation strategies at the isolated gate driver interface in terms of the controlled coupling parameter, reported implementation performance, and principal engineering constraints.

Table 6. Comparison of CM-current suppression strategies for isolated gate driver interfaces.

Strategy	Key Approach	CM Suppression	Relative Cost	Integration	Refs.
Low-Cps isolated supply	PCB-embedded planar transformer with minimized primary secondary coupling	Cps = 1.6 pF; 85% efficiency; 72 W/in3	Med.	High	[107]
	Integrated signal power transfer with compact isolated transformer	Cps = 2.2 pF; CMTI > 100 V/ns	Med.-High	High	[111]
Electrostatic shielding	Reduce transformer interwinding capacitive coupling by field design	Reduces effective primary-secondary coupling	Low-Med.	Med.	[104]
	Grounded Faraday shield between windings	Cps: 2.2 → 1.6 pF; CM induced disturbance 0.8 → 0.6 V	Low	High	[108]
CM choke	Frequency-dependent CM impedance inserted in the return path	High-CM impedance around the designed band	Low	High	[109]
	CM/DM choke modeling for impedance suppression	Frequency-selective CM attenuation	Low	High	[110]
	CM choke integrated with resonant gate-drive supplies	CM-current reduction experimentally demonstrated; no explicit attenuation value reported	Med.	Med.-High	[112]
Cascaded isolated supply	Cascaded gate-drive supplies reshape the CM return path	ICM,pp: 5.5 → 1.6 A; 71% reduction	High	Low-Med.	[28]
	Multistage isolated supplies for series-connected devices	Exact reduction depends on cascaded architecture	High	Low-Med.	[29]

3.3. EMI Control Strategy for Electric Drive Systems

Based on the analysis presented in Section 2.3 regarding the EMI generation mechanism of the electric drive system, it can be concluded that the suppression method can be derived from both the interference source and the propagation path.

3.3.1. Conducted EMI Suppression Techniques Based on the EMI Source

PWM strategies influence conducted EMI mainly through two mechanisms. First, variations in switching frequency f_s, frequency deviation ∆f_s, and switching sequence redistribute the discrete spectral components around nf_s and their sidebands [37,51,52,113,114,115,116,117,118]. Second, PWM modifies the common mode voltage (CMV) waveform, including V_CM,pk, V_CM,RMS, and the number or magnitude of CMV transitions, thereby affecting the common-mode current through i_CM = C_p·dv_CM/dt. These mechanisms lead to three main classes of PWM based mitigation: spectrum spreading, CMV optimization, and multiobjective modulation [116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132]. Modulation also affects current harmonics, switching losses, and control performance. For example, variable switching frequency PWM (VSFPWM) changes the effective sampling and modulation behavior of the current loop, which can alter the bandwidth and phase response of the $dq$ current controller [133].

Spectrum spreading methods redistribute the discrete peaks concentrated around $n{f}_s$ and their sidebands over a wider frequency range by varying the carrier frequency or switching instants [134]. Experimental results in [135] at a modulation index of m = 0.8 show that constant switching frequency PWM (CSFPWM) produces a pronounced spectral peak of nearly 100 dBμA around 150 kHz. Random or periodic carrier modulation substantially reduces these discrete peaks, as shown in Figure 22, although the noise floor increases in parts of the 150 kHz–2 MHz range. Experiments on a WBG traction inverter in [117] similarly showed that spread spectrum modulation reduced the common mode conducted EMI peak at 160 kHz by only about 2 dB, whereas an alternative topology with an auxiliary switching leg achieved a reduction of approximately 25 dB on the same platform. Spectrum spreading is therefore most useful for discrete peaks near the carrier and its sidebands; the measured benefit remains sensitive to spreading depth, network resonances, and receiver bandwidth.

Figure 22. Qualitative comparison of various PWM schemes: CSFPWM, VSFPWM, RPWM, Normal distribution PWM(NDPWM) with modulation index 0.8 [135].

For direct suppression of common mode excitation, recent studies have increasingly optimized the CMV waveform and switching vector sequence. Representative approaches include active zero vector PWM, phase clamping PWM, zero sequence voltage injection, and optimized vector sequencing. These methods reduce CM excitation by limiting switching states with high CMV or reducing the number of CMV transitions. In [122], a 240° clamped SVPWM strategy for EV/HEV traction systems was experimentally evaluated on a 10 kW platform. Compared with conventional CSVPWM, it reduced both the CMV peak and the number of CMV pulses per switching period by 66.7%, lowered $V_{\mathrm{C}\mathrm{M},\mathrm{R}\mathrm{M}\mathrm{S}}$ by 21%, and reduced switching loss by about 85%, while maintaining a similar current THD at the maximum speed. In [123], zero sequence voltage injection was used to eliminate pulse overlap regions responsible for large CMV excursions, reducing the CMV amplitude by 50% and the number of CMV pulse edges by approximately one third. Reference [128] further showed that pulse position optimization can coordinate CMV suppression and current quality without substantial degradation of the output performance. CMV optimization directly reduces the source excitation and can be coordinated with switching loss and current quality.

To account for the influence of dead time and switching loss on CMV suppression, ref. [119] proposed modified single edge modulation (MSEM). Active voltage vector combinations are selected according to the sector, and their sequence is rearranged to reduce switching loss. The carrier frequency is also varied according to the output current phase to address differential-mode-conducted EMI. Because dead time can reintroduce CMV spikes during commutation, the pulse sequence is further corrected according to the phase current direction at the switching instant. Similarly, ref. [129] reconfigured the voltage vector sequence of a three phase PMSM drive and experimentally verified the resulting reduction in CM excitation and conducted EMI. Since the effectiveness of such methods depends on both dead time and switching loss, the optimal vector sequence remains operating point-dependent. Reference [121] proposed a software modulation method based on delay compensation. By iteratively calibrating the commutation instants of different bridge legs, CM-current pulses generated by adjacent legs are made to cancel as far as possible. The method reduced common mode conducted EMI by about 30 dB at 160 kHz and maintained approximately 15–20 dB attenuation over several MHz. It requires no additional high power filtering branch, but its performance depends on accurate commutation delay calibration and on the adopted four-leg topology.

For emerging winding configurations, the CMV generation mechanism also depends on the inverter topology [132]. For a series end winding motor drive (SWMD), ref. [120] showed that the motor-side and inverter-side CMVs differ because of the asymmetric winding connection, and proposed constant CMV PWM (CCMV-PWM) and reduced CMV PWM (RCMV-PWM). CCMV-PWM is mainly suited to the low modulation range and suppresses CMV variation by selecting voltage vectors with the same common-mode potential. RCMV-PWM expands the available vector set and can cover the full modulation range. The two strategies therefore provide complementary tradeoffs between modulation range and CM suppression. For multi inverter motor drives, ref. [130] proposed a discontinuous PWM strategy that eliminates the phase to ground CMV of a dual unit PMSM drive under ideal switching conditions by restricting the switching states that generate common mode potential. Dead time, however, still introduces short CMV spikes and therefore requires compensation.

As the coupling among CMV, switching loss, and current quality becomes more pronounced, recent studies have employed optimization-based PWM and model predictive control (MPC) to coordinate multiple objectives. In [124], low CMV virtual voltage vectors were combined with a variable DC bus for an EV PMSM drive, improving CMV, current harmonics, and switching frequency characteristics in the low-speed region. Reference [131] reconstructed the candidate voltage vectors and prediction process so that MPC for a multilevel inverter inherently suppresses CMV, avoiding the tuning problem associated with an additional CMV weighting factor. Ref. [125] further address the high dv/dt issue in SiC PMSM drives, both CMV and motor-terminal DMV are incorporated into the pulse pattern design; accounting for dead-time effects, various candidate pulse sequences are constructed based on the modulation index. This method reduces the peak line voltage at the motor terminals by approximately one-third compared to two RCMV-MPC baseline methods. Under operating conditions of 500 r/min and 10 N·m, the torque ripple is approximately 0.13 N·m and the current THD is 14.02%, all without increasing the switching frequency or computational burden.

Recent PWM optimization has therefore evolved from a single CMV amplitude metric toward multidimensional criteria that include CMV transitions, common-mode current, differential-mode voltage, THD, switching loss, and real-time computational demand. This is particularly important for SiC traction inverters, where fast switching makes the final EMI response more sensitive to dead time, parasitic parameters, and motor cable impedance. Consequently, CMV reduction and conducted noise attenuation reported for the same modulation strategy on different test platforms should not be ranked directly without considering the corresponding operating and measurement conditions. Table 7 summarizes the operating principles, experimental results, and main constraints of representative PWM methods. From an engineering perspective, spectrum spreading requires no modification of the power topology and is well suited to reducing discrete peaks around the carrier and sidebands. CMV optimized PWM directly reduces common mode excitation and can coordinate switching loss through appropriate vector and sequence design. MPC and optimized pulse patterns provide greater flexibility for multiobjective coordination, but require more detailed models, computational resources, and operating point calibration. For broadband conducted noise amplified by resonances in the cable, motor, and parasitic network, modulation optimization should therefore be combined with CM/DM filtering and common-mode return path design.

Table 7. Representative PWM strategies for EMI and CMV oriented optimization.

Category	Scheme	Main Mechanism	Representative Results	Main Trade-Offs	Refs.
Spectral spreading	Spread-spectrum modulation (SSM)	Redistribute carrier spectral peaks	−2 dB at 160 kHz	Noise floor redistribution	[117]
CMV oriented PWM	240–clamped SVPWM	Reduce high-CMV states/transitions	VCM,pk ↓ 66.7%, RMS ↓ 21%, Psw ↓ 85%	Modulation constraints	[122]
	Zero-sequence voltage injection	Modify reference/overlap regions	CMV amp. ↓ 50%, edges ↓ 33%	Operating range dependence	[123]
	PPM	Optimize pulse positions	CMV ↓ 3%, current distortion ↓ 18.5%	Moderate CMV improvement	[128]
	MSEM	Vector ordering + variable carrier + dead time compensation	CMV/DM EMI and switching loss co-optimization	Current polarity-dependent logic	[119]
	Improved vector-sequence PWM	Reorder vectors to suppress CMV excitation	Experimental conducted EMI suppression	Dead time and loss trade-off	[129]
	CCMV-PWM/RCMV-PWM	Vector combinations for SWMD	CM noise ↓ 10–20 dB	RCMV THD ↑ at low Mi	[120]
MPC	Variable DC bus CMV reduction MPC	Low-CMV virtual vectors + DC bus optimization	CMV/current harmonic/switching frequency improvement	Extra DC-DC coordination	[124]
	Inherent CMV reduction MPC	Constrained candidate vector prediction	CMV reduction with controlled computational burden	Model/computation dependence	[131]
	PPO-assisted MPC	Pulse-pattern optimization for CMV + DMV	CMV $\pm V_{DC}/6$, motor voltage peak ↓ ~1/3	Real-time implementation	[125]
Optimized CMV PWM	OP-AZSPWM	Optimizes dwell time allocation among active vectors and imposes minimum dwell-time constraint	Improved CMV and current quality; removes CMV spikes and line voltage pulse reversals	Online dwell time optimization; performance depends on modulation region	[126]
Topology modulation codesign	Enhanced VSI + optimized PWM	Introduces additional switching states and jointly optimizes modulation and power topology	CM voltage ↓ up to 95%, efficiency ↑ up to 5.5%	Different power topology	[127]

Note: ↑ and ↓ denote an increase and a reduction, respectively, in the reported quantity (e.g., CMV, RMS value, THD, switching loss, motor-voltage peak, or efficiency) relative to the corresponding reference or baseline case under the reported test conditions.

Additionally, Figure 23 illustrates the three main source-side PWM mitigation mechanisms. Spectrum spreading redistributes discrete switching harmonics, CMV-oriented modulation reduces common-mode excitation by reshaping the CMV waveform and switching sequence, and multi-objective modulation coordinates EMI suppression with switching loss, current quality, and other operating constraints.

Figure 23. Source-side principles of PWM-based conducted EMI mitigation. (a) spectrum spreading using periodic and random PWM; (b) CMV-oriented modulation and the resulting reduction in common-mode current; (c) multi-objective modulation considering EMI, switching loss, and current THD.

3.3.2. Method Based on EMI Propagation Paths

Filtering strategies in electric drives can be compared according to installation location, noise mode, and implementation form. DC filters limit noise propagation toward the high-voltage DC network, whereas AC filters primarily control the CM return path through the cable and motor and can also reduce motor terminal voltage stress.

On the DC side, CM current returns mainly through parasitic capacitances to the chassis, whereas DM noise circulates between HV+ and HV−. A CMC and $C_Y$ are therefore typically used for the CM path, while DM inductors and C_X form LC or Π networks for DM attenuation.

Designing the filter to provide a uniformly large insertion loss over the entire specified frequency range can readily lead to overdesign. Ref. [136] compared two DC-side filter designs for a PMSM drive. In the conventional design, an insertion loss of approximately 60 dB was specified over a broad frequency range from 150 kHz to 108 MHz. By contrast, a resonance targeted design focused on the dominant resonances near 1 MHz and 30 MHz. While satisfying the required attenuation, the resulting filter volume was reduced to approximately one quarter of that of the conventional design. In subsequent work, the source impedance of the motor controller was incorporated into the filter design, and compliance with CISPR 25 Level 3 was experimentally demonstrated [137]. These results indicate that the design margin of DC-side common-mode and differential-mode filters should be determined according to the actual frequency ranges of excessive emissions together with the source and load impedances.

When the size of a large CMC and the leakage current associated with C_Y become limiting factors, active and hybrid filters can reduce the required passive inductance or capacitance, at the cost of auxiliary loss, control bandwidth, and stability requirements. Ref. [138] developed a hybrid common mode filter for an EV traction inverter by cascading an active compensation stage with a high-frequency passive branch. Its capability to suppress DC-side common-mode noise was experimentally verified under high current electric drive operation. Ref. [139] employed the common mode impedance of the motor to construct a transformerless active EMI filter, in which voltage sensing and current compensation were used to reduce DC-side common-mode noise.

On the AC side, common-mode noise is mainly excited by high-frequency voltage variations that occur simultaneously at the three phase terminals with respect to the chassis. The resulting current returns through the motor housing, cable shield, and parasitic capacitances between the windings and ground. A typical three phase AC-side common-mode filter is shown in Figure 24. The three phase conductors pass through or are wound around a common magnetic core to form a CMC, while C_Y or the cable shield is used to control the high-frequency common-mode return path. In comparison, differential-mode components on the AC side mainly appear in the phase to phase voltages and currents. LC and LCL filters, as well as output dv/dt filters, can be used to suppress high-frequency differential-mode components and reduce terminal voltage stress caused by cable reflections.

Figure 24. Typical configuration of filter in electric drive systems.

Recent studies on AC side filtering for SiC electric drive systems have placed particular emphasis on reflected waves and high dv/dt under long cable conditions. Ref. [140] proposed a band stop dv/dt filter designed around the cable resonance. By introducing selective impedance near the dominant reflected wave frequency, the filter achieved motor terminal voltage suppression comparable to that of active solutions while maintaining lower loss and smaller volume. Ref. [141] employed a T type active dv/dt filter and experimentally limited the motor terminal voltage peak to approximately 1.13–1.15 pu under a 400 V DC bus, a 20 kHz switching frequency, a 2.2 kW motor, and a 12.5 m cable. Because these methods primarily address AC terminal insulation stress and reflected waves, their performance metrics differ from those used for CISPR-based conducted emission measurements at the DC terminals. Therefore, their results should not be directly compared numerically with attenuation values reported in dBμV or dBμA.

In practical traction systems, AC side EMI mitigation must also consider cable shielding and chassis return paths. Shielded cables can reduce the common mode potential at the motor terminals while simultaneously increasing common-mode current flowing through the chassis [43,44]. Therefore, filter placement should be coordinated with the shield termination and chassis connection strategy. In addition to conventional passive approaches, ref. [142] placed an active EMI filter in the motor frame to ground branch and suppressed DC-side common-mode noise by modifying the impedance of the grounding loop. Accordingly, the central objective of AC-side propagation path optimization in vehicle applications is to control the closed path of common-mode current and the impedance associated with that path.

In passive filtering, the CMC remains the core component for suppressing CM current. A typical three-phase AC-side CM filter is shown in Figure 24 [143], where the three phase conductors are wound on a common magnetic core to form a CM choke, and the C_Y capacitors provide a controlled high-frequency return path to the motor casing or chassis ground. Under CM excitation, the phase currents flow through the choke windings in the same magnetic direction, so their magnetomotive forces add in the magnetic core [144,145]. In the linear small-signal region, the inductive behavior of a CM choke can first be described using a magnetic-reluctance model, in which both the material permeability and the geometry of the magnetic flux path determine the resulting inductance [146]. The magnetic reluctance of a general core can be expressed as (18).

$${\mathcal{R}}_m\left(f\right)={\displaystyle {\oint }_l\frac{dl}{{\mu }_0{\mu }_e^{\prime }\left(f\right)A\left(l\right)}}$$

(18)

where A(l) is the local core cross-sectional area, μ₀ is the permeability of free space, and μ_0′(f) is the effective real permeability at frequency f. According to Ampere’s law, the magnetomotive force produced by an m-winding choke can be expressed as (19).

$$\mathcal{F}={\displaystyle \sum _{k=1}^m{N}_k{i}_k}$$

(19)

and the corresponding core flux is Φ = F/R_m. Therefore, the flux linkage of winding i is shown as (20).

$${\lambda }_i=N_i\Phi ={\displaystyle \sum _{k=1}^m\frac{N_i{N}_k}{R_m}{i}_k}$$

(20)

where the self and mutual inductance terms are determined by the common magnetic path. For m identical windings carrying the same CM current, i₁ = … = i_m = i_CM, the effective CM inductance seen by each winding is L_CM,ph = L_s + (m − 1)M, in which L_s is the self-inductance of one winding and M is the mutual inductance between two windings. For a symmetrical three-phase choke, L_CM,ph = Ls + 2M.

With tight magnetic coupling and small leakage inductance, M approaches the magnetizing component of L_s, so the CM inductance is substantially enhanced because the three phase magnetomotive forces reinforce each other. In contrast, under balanced differential-mode excitation, i_a + i_b + i_c ≈ 0, and the net core flux is strongly reduced. For engineering calculations, the magnetizing inductance of one winding can be conveniently written using the effective core parameters as (21).

$$L_m\left(f\right)={\mu }_0{\mu }_e^{\prime }\left(f\right){\displaystyle \frac{N_L^2{A}_e}{l_e}}$$

(21)

where N_L is the number of turns per winding, A_e is the effective magnetic cross sectional area, and le is the effective magnetic path length. For a toroidal core with inner radius ri, outer radius ro, and axial height h_c, Ampere’s law gives H(r) = N_Li/(2πr). Integrating the resulting magnetic flux over the radial core dimension yields:

$$L_m\left(f\right)={\displaystyle \frac{{\mu }_0{\mu }^{\prime }\left(f\right)N_L^2{h}_c}{2\pi }}\mathit{ln}\left({\displaystyle \frac{r_o}{r_i}}\right)$$

(22)

At higher frequencies, the choke should be described by its frequency-dependent impedance [147,148]. If the core permeability is written as μ*(f) = μ′(f) – jμ″(f), the imaginary component represents magnetic loss, while winding capacitance, leakage inductance, and other parasitic effects introduce self-resonance and modify the CM insertion impedance [144,149]. Therefore, a high value of μ′ can increase the low- and mid-frequency CM inductance, but the usable EMI attenuation range also depends on μ′(f), μ″(f), core geometry, winding configuration, parasitic capacitance, flux density, temperature, and DC-bias conditions. The relevant characteristics of commonly used magnetic materials are summarized in Table 8.

Table 8. Comparison of magnetic core materials for EMI chokes.

Category	Magnetic Characteristics	Main Advantage	Key Design Constraint	Refs.
Mn-Zn ferrite	Moderate- to high-permeability; low core loss at high frequencies	Low-cost and mature technology	Lower saturation capability; permeability decreases with frequency	[150,151]
Nanocrystalline alloy	Very high permeability; good DC bias capability	High-inductance density and compact CM choke design	Higher cost; frequency- and temperature-dependent losses	[138,139,152,153]
Amorphous alloy	High-permeability and high-saturation flux density	Suitable for high-current magnetic components	Higher high-frequency loss; thermal design becomes important	[154,155]

For traction inverters, passive filter design must balance attenuation performance against SWaP-C constraints. Reference [156] developed single-stage and two-stage integrated magnetic CM/DM filters. The single-stage design reduced PCB area and filter volume by approximately 37% and 34%, respectively, while the two-stage design achieved reductions of about 36% and 9%. Reference [157] further integrated the CM and DM magnetic paths, reducing PCB area by approximately 17.2–23% and volume by 10–17.2%. Similarly, ref. [158] electromagnetically integrated the CM inductor, DM inductor, and filter capacitors in a 100 kHz, 500 W SiC MOSFET converter. At higher power levels, ref. [159] jointly optimized planar CMC design with thermal and insulation constraints for a 100 kW SiC inverter/rectifier system, achieving a CM filter volume of only 155 cm³. The study also emphasized that magnetic core selection must account for insulation, current density, and thermal limits rather than rely on a fixed frequency criterion independent of operating conditions.

Where passive filters cannot simultaneously satisfy attenuation and volume requirements, active EMI filters (AEFs) can detect CM noise and inject a compensating current i_comp, yielding i_res = i_CM − i_comp. Recent AEFs have extended CM attenuation from the hundreds of kilohertz into the low megahertz range. The feedforward implementation in [160] achieved approximately 30 dB attenuation from 60 to 400 kHz, while the adaptive digital filter in [161] reached about 37 dB near 2 MHz. Virtual capacitance techniques can further reduce the physical $C_Y$ requirement [162]. Hybrid designs combine these active functions with smaller passive components: [163] reduced the required CMC inductance by about 73%, whereas [164] reported 10–30 dB attenuation from 150 kHz to 30 MHz together with a 76% reduction in filter volume. This benefit, however, comes with additional auxiliary loss and control complexity. More recently, a negative inductance hybrid structure used a sensing transformer to provide both compensation and an equivalent negative inductance [165], further illustrating the trend toward coordinated design of active branches and passive magnetic components.

Table 9 summarizes the filtering methods used in electric drives.

Table 9. Comparison of representative EMI filtering strategies for electric drive.

Implementation	Strategy	Location/Mode	Principle	Representative Reported Result	Main Trade-Off	Refs.
Passive	Impedance-aware passive filter	DC/CM + DM	Filter parameters optimized using source/load impedance and dominant resonances	60 dB IL over 150 kHz–108 MHz; targeted design reduces size to ~1/4	Impedance variation; possible overdesign	[136,137]
	Integrated passive filter	DC/CM + DM	CM/DM magnetic paths and passive components are integrated to increase power density	PCB area ↓ 17–37%; volume ↓ 9–34%	Parasitics; saturation; thermal coupling	[156,157,158,159]
Active	Active CM EMI filter	DC/CM	Sensed CM noise is canceled by injected compensation current/voltage	30 dB attenuation over 60–400 kHz; >42 dB at 150 kHz	Bandwidth; stability; auxiliary loss	[139,160,162]
	Digital adaptive AEF	DC/CM	Adaptive narrow band filters track dominant switching harmonics	>500 kHz effective bandwidth; up to ~37 dB at 2 MHz	Sampling delay; DSP burden; robustness	[161]
	Band stop dv/dt filter	AC/terminal stress	Selective impedance suppresses cable reflection resonances	Comparable overvoltage mitigation with lower loss/volume than conventional passive filters	Cable/resonance dependence	[140]
	Active dv/dt filter	AC/terminal stress	Active output stage controls voltage transition and reflected wave peak	Motor-terminal peak limited to 1.13–1.15 pu	Extra power stage; control complexity	[141]
Hybrid	Hybrid CM EMI filter	DC/CM	Active compensation and reduced passive network share the attenuation requirement	LCM ↓ 73%; 10–30 dB over 150 kHz–30 MHz; volume ↓ 76%	Stability; active loss; integration complexity	[133,138,158,159,160,163,164,165]

Note: ↓ indicates a reduction in the corresponding filter-related quantity relative to the reference or conventional design under the reported test conditions.

In summary, these mitigation techniques act at different points along the propagation chain of high dv/dt switching disturbances, and their evaluation metrics vary accordingly. Gate loop methods primarily focus on V_gs disturbance, false turn on margin, and switching loss. Isolation and gate-drive supply techniques are mainly evaluated in terms of parasitic coupling capacitance, common-mode current, and CMTI. At the system level, PWM and filtering methods further involve CMV, conducted emissions, THD, efficiency, and SWaP-C. Table 10 provides a systematic comparison of the main mitigation targets, performance benefits, and engineering tradeoffs of representative approaches based on reported experimental results.

Table 10. System-level comparison of mitigation techniques for switching-induced disturbances and conducted EMI.

Mitigation Level	Strategy	Controlled Quantity	Representative Evidence	Main Penalty	Deployment Evidence	Refs.
Gate loop	Miller clamp	Vgs, Miller current	False turn-on/Vgs spike suppression	Clamp loss; timing	Automotive gate driver ICs	[36,37,38,39,40,41,42,43,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75]
	Active gate driver	dv/dt, di/dt, overshoot	Adaptive switching waveform control	Sensing bandwidth; delay	Automotive/research prototypes	[77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,166]
Isolation interface	Low Cps supply/shielding	Cps, isolation CM current	Reduced capacitive CM coupling	Insulation; transformer design	Isolated gate-drive supplies	[104,105,106,107,108]
	CM choke/cascaded supply	ZCM, CM return path	Frequency-selective CM attenuation	Resonance; volume	Gate-drive prototypes	[28,109,110]
System source	Spread spectrum PWM	Spectral peaks	Attenuation at the resonant frequency	Noise floor redistribution	Traction inverter experiment	[122]
	CMV oriented PWM	CMV, CM current	Reduce VCM,pk, VCM,RMS, and Psw	THD; modulation constraints	EV/HEV traction experiment	[120,122,123,128,129,130]
	MPC/optimized PWM	CMV, DMV, THD	Reduce CMV and terminal peak	Computation; model dependence	SiC motor-drive experiment	[124,125,126,127,128,129,130,131,132,167]
Propagation path	Passive CM/DM filter	Terminal CM/DM noise	Balancing insertion loss (150 kHz–108 MHz) and filter size	Volume; impedance sensitivity	EV PMSM drive	[136,137]
	Integrated passive filter	CM/DM impedance, SWaP-C	Reduce PCB area and volume	Parasitics; thermal; saturation	High-power prototypes	[156,157,158,159]
	Active/hybrid filter	CM noise, filter volume	Increase insertion loss in specific frequency band; reduce size	Stability; auxiliary loss	Converter/motor-drive prototypes	[138,139,160,161,162,163,164,165]

4. Development Trends of Suppression Methods

To keep up with the trend toward higher power density [168] and higher voltage [169] in EVs, EMI suppression measures are also evolving toward greater integration and multi-domain codesign. This trend is becoming more pronounced with the transition from 400 V to 800 V platforms and the increasing use of 1200 V SiC devices in traction inverters [170]. Recent 800 V SiC traction prototypes have achieved power densities of approximately 60–86 kW(kVA)/L through compact busbars, integrated DC link structures, and electrothermal codesign [171,172], while six-phase SiC traction architectures have demonstrated peak power densities of approximately 70 kW/L [173]. Under these conditions, the available volume for conventional post-stage EMI filtering becomes increasingly limited, and EMI constraints need to be considered together with electrical, thermal, packaging, and mechanical design.

For the gate-drive and isolation interface levels, the main trend remains higher integration and adaptive regulation. Closed loop AGD continues to develop toward higher-bandwidth control of dv/dt, di/dt, and switching overshoot [174,175,176], while integration into gate-driver ICs can reduce external components and propagation delay. In parallel, isolated auxiliary supplies are evolving toward planar, PCB-embedded, and wireless structures that jointly optimize isolation capacitance, power density, and conversion efficiency [107,177]. For automotive SiC drives, these developments must additionally satisfy CMTI, insulation, delay, thermal, and functional-safety requirements. The Miller clamp method is already well established and commonly integrated into commercial gate-driver ICs [178]; therefore, its future development is not discussed separately.

At the system source level, PWM development is gradually extending from carrier-frequency manipulation toward multi-objective optimization. The increasing computational capability of the main controller enables programmed and predictive PWM strategies to coordinate CMV, current quality, switching loss, and terminal-voltage stress [113,179]. Recent studies further combine topology and modulation degrees of freedom to reduce the CM source before the filter stage. For example, quasi-two-level switching has achieved up to approximately 12 dB reduction in CM emissions around 1 MHz in a CISPR-25 based test configuration [180]. These results support joint design of modulation, topology, and the required filter attenuation before the power stage is finalized. Furthermore, soft switching provides another approach to reducing switching loss and transient switching stress by limiting the voltage-current overlap during commutation, and has been extensively investigated in high-frequency converter applications such as photovoltaic inverters and wireless power transfer systems [181,182,183].

For the propagation path, compact passive magnetics remain important. Higher permeability and saturation capability continue to support the reduction in CM choke volume [153,184], while recent research increasingly emphasizes frequency-dependent permeability, winding parasitics, thermal constraints, and integrated CM/DM magnetic structures. Active and hybrid filters provide another route to higher attenuation density. A recent hybrid EMI filter developed specifically for automotive traction inverters reduced the magnetic-component volume by approximately 50% while maintaining comparable filtering performance [185]. Complete 800 V/550 kVA SiC traction inverter prototypes have also begun to integrate the DC-link, CM/DM EMI filter, sensing, and control hardware within a common automotive design boundary [186].

Increasing integration of the inverter, motor, busbar, and cooling structure also changes the CM impedance network. In x-in-1 electric-drive modules, the shorter physical distance between subsystems reduces interconnection volume but increases parasitic coupling density and can introduce new CM resonances. Recent studies on all-in-one EV motor drive modules have identified DC bus stray inductance and multiport bus capacitor parasitics as dominant contributors to CM-current resonances [48]. Accordingly, wideband parasitic models are increasingly calibrated using impedance or multiport measurements rather than relying solely on nominal component values or CAD extraction [187]. Together with package level capacitance optimization [49], these approaches indicate a shift toward resonance-aware EMI prediction during the early design stage.

Higher controller bandwidth also enables adaptive and localized EMI mitigation. Digital active EMI filters can adjust compensation according to the operating condition; recent adaptive FIR-based implementations have achieved more than 25 dB CM noise suppression over approximately 200 kHz–6 MHz [188]. On the motor side, active reflection cancelation and smart coil approaches process only the high-frequency transient energy associated with cable reflections [41,42], providing a potential alternative to bulky full power output filters. For automotive deployment, however, the benefits of active and adaptive methods must be balanced against sampling delay, auxiliary loss, stability, failure modes, and qualification requirements.

The major development directions are summarized in Table 11.

Table 11. Emerging trends and automotive constraints of EMI mitigation in SiC traction inverters.

Driving Factor	Development Direction	Main Automotive Challenge	Refs.
800 V+/high power density	Electrothermal and EMC co-design of inverter, busbar and DC link	Thermal coupling; insulation; limited filter volume	[170,171,172,173,189]
x-in-1 integration	Resonance-aware multiport parasitic modeling	Dense coupling; model accuracy	[48,187]
Gate drive/isolation integration	Adaptive AGD and low Cps isolated supplies	Delay; CMTI; functional safety	[107,174,175,177]
Source-filter co-design	Topology/PWM jointly designed with required filter attenuation	Control complexity; operating range dependence	[180]
Compact EMI filtering	Integrated passive and active/hybrid filters	Stability; auxiliary loss; qualification	[185,186]
Cable/motor-side mitigation	Local reflection and terminal-stress suppression	Cable dependence; reliability	[40,41,42]
Adaptive EMI control	Software defined/digital active filtering	Sampling bandwidth; fail safe operation	[188]
Standards aware design	Measurement calibrated models and compliance-oriented optimization	Detector/RBW/layout consistency	[16,17,18,19]

5. Conclusions

This review examines the major switching-induced electromagnetic disturbances and conducted EMI mitigation techniques relevant to SiC traction inverters. The reviewed phenomena are organized into three representative source–path–victim paths spanning the gate loop, isolation interface, and inverter/powertrain terminals.

(1) At the gate loop, rapid dV_ds/dt and di_d/dt couple through the Miller capacitance and parasitic inductances into the complementary MOSFET, producing positive or negative gate-voltage disturbances. Miller clamps provide a low-impedance path for the coupled current, while active gate drivers regulate the switching trajectory to coordinate crosstalk, overshoot, and switching loss.

(2) At the isolation interface, the voltage transient of the floating power domain drives CM current through the parasitic capacitances of the isolated auxiliary supply and gate driver. Reducing these capacitances, adding CM impedance, or reshaping the return path can reduce the disturbance transferred to the low-voltage reference and control circuits.

(3) At the inverter and powertrain terminals, CM and DM emissions depend jointly on the switching source and the frequency-dependent impedance network formed by the DC link, package, cables, motor, chassis, and filters. PWM and CMV optimization act on the source, whereas passive, active, and hybrid filters modify the propagation path. Their effectiveness must be evaluated together with operating condition, measurement configuration, loss, volume, and integration constraints.

Future traction inverter design is expected to place greater emphasis on coordinated electrical, thermal, mechanical, and EMC design for 800 V and highly integrated platforms. Adaptive gate control, topology and modulation optimization, impedance-aware filtering, and measurement calibrated parasitic models are likely to play complementary roles rather than provide a single universal EMI solution.

The scope of this review is limited to disturbances associated with inverter switching and their relevant propagation paths. Detailed radiated EMI, motor electromagnetic design, cable EMC design, and immunity of the complete vehicle are outside the main scope.