Zero Photovoltaic Leakage Current Boost Inverter Using Modified Symmetrical Switch Common Ground Topology with Lower Device Stress

Abstract

The transition to clean photovoltaic sustainable generation sources has motivated several developments in required power electronics interface systems. The conventional solution is based on two cascaded conversion stages, leading to reduced efficiency, inevitable leakage currents, and/or a high number of required components. Another solution is the use of integrated two-stage solutions suffering from asymmetrical switch structures, discontinuous input side currents, and/or complex modulation and control requirements. This paper presents a modified configuration with symmetrical six switches based on the common ground boost inverter solution. Furthermore, the proposed solution presents a continuous input side current and a simple modulation strategy. Moreover, the proposed CG topology offers a reduction of the current stress on the power switch by diverting the load current away from the power switch during the inductor charging. The operation, modulation, and control of the developed solution are presented in the paper, including comprehensive performance comparisons with boost inverter solutions in the literature. Simulation and experimental prototype-based results confirm the advantages and superiority of the proposed topology over existing topologies.

1. Introduction

The transition to clean and environmentally friendly sustainable energy solutions, especially in power generation and transportation sectors, has brought different motivations to developing efficient power electronic solutions [1]. Power electronic conversion systems represent a crucial element in photovoltaic (PV) generation as the highest contributing renewable source in global records [2,3]. Power electronics DC–DC converters based on isolated solutions have been reviewed in [4]. The conventional solution for integrating PV systems with this utility is the cascaded boost inverter with a two-level inverter system [5]. This configuration enables the separation of control objectives among the two converters and facilitates the extraction of maximum power (MP) on the DC side and the injection of high-quality current on the AC side [6]. The control of this configuration is crucial in hybrid PV with energy storage systems [7,8]. However, this solution does not afford maximum efficiency to many of the required components [9,10]. Moreover, this configuration has inevitable common mode voltages (CMVs) due to the switching modulation of different semiconductor switches [11]. The CMVs with the stray capacitances between the PV panels and the earth generate leakage currents in the PV systems, which affect humans and equipment [12]. Furthermore, grid codes have set a limit for the permissible generated leakage currents in PV systems [13].

Several topologies and modulation schemes have been presented in the literature for the reduction of resulting leakage currents in PV systems [14]. Some methods are based on modulation techniques [15], including space-vector modulation [16]. A space vector modulation has been presented for leakage current reduction in induction motor drives in [17] with a parallel configuration of full-bridge converters. An improved over-modulation scheme for suppressing common-mode voltages and, hence, reducing leakage current has been proposed in [18] for three-level NPC inverter systems. However, these methods need complex calculations and face some limitations in several topologies, in addition to their inability to fully mitigate leakage currents. The increasing number of components and requirements of complex control and modulation strategies hinder the widespread adoption of leakage-current-reduction topologies in the literature [19]. Moreover, they may not be able to totally eliminate leakage currents [20]. The modulation schemes developed for leakage current reduction possess asymmetrical switching schemes and topology structures [21]. Among the presented methods, the common ground (CG) PV inverter topologies [22], also named double-grounded (DG) inverters, have found broad interest [23]. The CG-based topologies include a direct connection between the neutral wire of the grid side and the negative wire of the PV panel side [24]. This, in turn, provides a zero CMV at all operating conditions, leading to the total elimination of existing leakage current components [25].

A topology based on the virtual DC-link bus has been developed in [26]. A switched capacitor cell is used to generate the negative voltage level, while it is mainly charged during positive voltage level generation [27]. Another topology using the charge pump concept has been presented in [28]. The current stress on some switches can be considered a relative disadvantage; however, it can be mitigated through appropriate design methodologies. Another charge-pump circuit concept was introduced in [29], but the two-stage charge transfer mechanism significantly increases the number of required power components. A notable inverter with a common ground configuration was proposed in [30], featuring a reduced switch count and utilizing a unipolar pulse-width modulation (PWM) strategy. Additionally, a multi-level common ground transformerless inverter was presented in [31], which eliminates the need for switched capacitors. This topology offers a lower switch count compared to conventional designs but requires a higher input voltage compared to full-bridge-based topologies.

The topology proposed in [32] introduces a straightforward and practical approach by integrating the boost converter and single-phase inverter within a common ground configuration, effectively mitigating leakage current. However, one of the power switches experiences significant current stress due to the combined flow of load current and input current through the boost switch. Additionally, a prominent feature of modern boost inverters is the reliance on half-bridge configurations. Consequently, this paper proposes a CG boost inverter design with symmetrical switches, aiming at reducing current stress and enhancing the efficiency of generation systems.

A seven-level, three-fold boosting of a low input voltage CG inverter has been presented in [33]. The presented topology can achieve three times the voltage gain while eliminating leakage currents. However, the topology employs ten power switches, a diode, and two capacitors. Furthermore, the topology uses asymmetrical components due to the different voltages of DC capacitors. Another solution has been presented in [34] for reducing component voltage stresses and reducing the number of components. However, the presented solution suffers from the discontinuous DC input side current, which affects the PV side current stresses and its MPPT control. Another topology based on zeta inverter using non-electrolytic capacitors has been presented in [35]. Similarly, the topology has a discontinuous DC input side current problem. Another topology has been provided in [36] using only four power switches, a single inductor, and a single virtual DC capacitor. The topology offers a solution for the discontinuous DC input side current problem. However, the virtual DC capacitor has a high degree of ripple and is difficult to control.

In [37], a new nine-level CG topology has been presented. The topology uses eight power switches, two power diodes, and two virtual DC link capacitors. Another topology based on a reduced number of power switches has been presented in [38] using a flying inductor principle. However, the inductor current stresses are very high, and the inductor contains a high AC component. A topology with only three power switches has been proposed in [39]. However, the topology employs six diodes, two inductors, and three DC capacitors. Furthermore, the topology provides a discontinuous input side current.

It is clear from the above discussion that the majority of existing topologies suffer from an increased number of components and/or present a discontinuous input-side current. Further modifications and improvements of topologies are essential with CG connections. Moreover, reducing the number of employed components and maintaining a symmetrical device structure is crucial for industrializing CG inverters. Stimulated by these critical issues, this paper provides a new CG inverter topology that offers the following benefits:

• The proposed topology provides similar performance to split source inverter topology while preserving lower current stress for the connected power switch to the boost inductor. In addition, the proposed topology possesses the common ground configuration/connection; thus, the leakage current is eliminated.
• The proposed topology employs symmetrical power switches with complementary pulses using half-bridge modules with a simultaneous operation. Employing available half-bridge modules enables straightforward implementation with minimal additional design effort.
• The proposed topology uses a simpler approach for signals generator by using hybrid sinusoidal and constant PWM, providing a constant duty cycle to control the charging and discharging of boosting inductor $L_b$.

The remaining sections of the paper are organized as follows: Section 2 presents the new proposed circuit and its operating modes. The voltage gain and PWM generation for the newly proposed topology are given in Section 3. The obtained simulation and experimental prototype results are provided in Section 4, enhanced with performance comparisons of the proposed topology and existing CG solutions in the literature in Section 5. Section 6 provides dynamical closed-loop simulation results of the proposed topology. Finally, the conclusions of the paper are provided in Section 7.

2. Proposed CG Boost Inverter

2.1. Zero-Leakage Current PV Inverter Topology

The recent advancements in transformerless inverter (TLI) topologies for PV applications have made them preferred solutions. TLIs possess higher power densities compared to transformer-based solutions, as well as having smaller sizes, and lower costs. A significant issue with TLIs is the leakage currents resulting from parasitic capacitances between the metal parts of the panel and the ground. The amount of leakage currents is a function of the common-mode voltages resulting from the power electronic conversion stages.

A perfect solution to completely eliminate leakage currents in PV systems is through specific topologies and/or modulation techniques that maintain the CMV constant or equal to zero. Therefore, the amount of leakage current is completely eliminated in PV systems. Among the various presented solutions, the common ground (CG)-based power inverter solutions have shown superior performance and power quality, with zero leakage current and high efficiency. The CG topologies are also referred to as doubly grounded (DG) topologies.

Inherently, the CG solutions possess a direct connection between the negative PV side terminal and the neutral side terminal of the grid. Consequently, the common-mode voltage remains constant during operation, and the parasitic capacitance between the PV array and ground is not excited by high-frequency switching components. As a result, leakage current is inherently eliminated by structure, consistent with the operating principle of common-ground transformerless inverters reported in the literature [21,40].

A generalized representation of the CG concept is shown in Figure 1. The circuit includes the parasitic capacitance ($C_{PV}$) connected between the negative port of the PV panels and the neutral point of the AC port [12]. In addition, the ground impedance ($Z_{ground}$) is included in the circuit equivalent model. With this connection, it is ensured that the CMV, the primary cause of leakage current, remains constant without requiring high switching components. With the inclusion of the direct CG short-circuit in the configuration, the modeled impedance $Z_{ground}$ and capacitance $C_{PV}$ are clamped, resulting in the cancellation of the expected ground leakage current components accordingly. Therefore, zero leakage current components are obtained through employing the TLI based on the CG configuration.

Figure 1. Principle of zero leakage current PV inverter topology.

2.2. Development of Proposed CG Topology

Figure 2 shows the power circuits of the latest developed solution in ref. [32] and the proposed CG topology. The CG boost inverter depicted in Figure 2a is designed to merge the basis of the boost converter with the full bridge inverter. In order to improve the operation of Figure 2a, its boost leg, which consists of three series-connected switches, is analyzed first. One of the three switches must be turned OFF in order to avoid short circuits, as shown in Figure 3. The inductor charging and the load current flow in $S_3$, thus the current stress of this switch is high. By replacing the boost leg of Figure 2a, a new half-bridges boost inverter is proposed in Figure 2b. The proposed configuration achieves the required switching states as derived in Figure 4. The proposed topology consists of three half-bridges: boost inductor $L_b$, decoupling capacitor C, and output filter inductor $L_f$. The following subsection explains the operation of the proposed symmetrical switches-based CG boost inverter.

Figure 2. The CG boost inverter topology: (a) Conventional topology with asymmetrical stresses, and (b) Proposed topology.

Figure 3. Switching state during inductor charging for the conventional topology with asymmetrical stresses: (a) First state with the circuit clamped at the upper side, and (b) Second state with the circuit clamped at the lower side.

Figure 4. Switching states for the proposed topology: (a) Inductor charging in the state [0], (b) Inductor charging in the state [+1], (c) Inductor charging in the state [−1] with the inductor current flows through $S_3$ only, and (d) Inductor discharging in the state [0].

2.3. Operation and Switching States

To simplify the operation, Figure 4 shows the switching status of the proposed topology. It is worth noting that the proposed topology simplifies the inverter design by utilizing half-bridge modules and reduces the inverter power losses. During the positive half cycle, the number of switches conducting the load current is reduced. Additionally, diverting the load current away from $S_3$ leads to reducing the current stress on this switch. Therefore, reduced power losses and, hence, a higher lifetime of the switch are achieved using the proposed topology.

The charging and discharging of the inductor are managed by leg c (boost leg) to facilitate the input voltage boosting process. Meanwhile, legs a and b (inverter legs) are responsible for delivering current to the load.

In State 1, the lower switches of legs a and b are turned OFF, resulting in an output inverter voltage $V_{ab}$ of 0 V, as illustrated in Figure 4a. During this state, the inductor $L_b$ is charged through $S_3$ as follows:

$$V_L=L_b{\displaystyle \frac{di}{dt}}$$

(1)

In State 2, the lower switch of leg b is turned ON, producing an output inverter voltage $V_{ab}$ = $+V_C$, as shown in Figure 4b. Conversely, in State 3, $V_{ab}$ = $-V_C$ when the lower switch of leg a is turned ON as illustrated in Figure 4c. Throughout States 1, 2, and 3, the inductor $L_b$ continues to charge via $S_3$. It is worth noting that the load current does not pass through $S_3$ during the inductor charging current. Thus, the current stress of this switch is reduced.

When the inductor discharges, the inverter transitions to State 4, where the lower switches of both legs a and b are turned ON, and $S3$ is turned OFF as shown in Figure 4d. This configuration allows the inductor to release its stored energy into the capacitor network. The voltages across the inductor and capacitors during this discharge phase can be expressed as in (2).

$$V_L=L_b{\displaystyle \frac{di}{dt}}=V_{dc}-V_C$$

(2)

As the boost inductor $L_b$ is charged and discharged with constant duty cycle D, the step-up voltage from the input to the capacitor network is not affected by the sinusoidal modulation. By applying volt-second balance across inductor $L_b$, the capacitor voltage $V_C$, similar to the operation of the conventional boost converter, is calculated as:

$$V_C={\displaystyle \frac{V_{dc}}{1-D}}$$

(3)

The constant duty cycle D is given by:

$$D={\displaystyle \frac{V_{\mathrm{dc},\mathrm{ref}}}{V_{tri,p}}}$$

(4)

where $V_{dc,ref}$ is a constant reference, and the duty cycle as a function of time is written as:

$$d=D{T}_s$$

(5)

3. Voltage Gain Calculation and PWM Generation

3.1. Derivation of Voltage Gain

The inverter voltage $V_{inv}$ is related to the capacitor voltage $V_C$. Therefore, the effective DC gain is computed as in (7).

$$V_{inv}=V_C={\displaystyle \frac{V_{dc}}{1-D}}$$

(6)

Which can be rearranged as follows:

$${\displaystyle \frac{V_{inv}}{V_{dc}}}={\displaystyle \frac{1}{1-D}}$$

(7)

The fundamental peak output voltage $V_o$ of the proposed is calculated as:

$$V_{o,p}=M{V}_{inv}={\displaystyle \frac{M}{1-D}}{V}_{dc}$$

(8)

where M = $V_{ref,p}$/$V_{tri,p}$ is the modulation index. The duty cycle generated by the sinusoidal reference can be written as a function of time as follows:

$$m=Msin\left(\omega t\right).T_s$$

(9)

The overall gain of the proposed boost inverter can be computed in (10). In order to avoid operation in the over modulation region, which leads to elevated THD, the maximum allowable modulation index is constrained by D.

$$G={\displaystyle \frac{M}{1-D}},M\le D$$

(10)

3.2. Modulation Strategy

The sinusoidal modulation with constant PWM offers a simplified approach by separates the control of the boost and inverter operation, where the duty cycle directly regulates the DC voltage gain and manage the charging and discharging of the inductor $L_b$. The sinusoidal modulation shapes the AC output. This structure simplifies the control design by reducing coupling and avoids the need for complex multi-loop coordination, where the DC–DC voltage boosting is independent of the sinusoidal modulation used to control the AC output. This decoupling significantly streamlines circuit analysis, allowing the standard equations of a conventional boost converter to be directly applied. Figure 5 illustrates the key waveforms of the modulation and the switching status summarized in Table 1. In the meantime, one leg (a or b) operates at a line frequency, resulting in lower losses. The switch state in each half cycle is summarized in Table 2.

Figure 5. Key waveforms of sinusoidal modulation with constant PWM.

Table 1. Switching states of the proposed topology.

State	Output Voltage	Modes	${\mathit{S}}_1$  ${\mathit{S}}_2$  ${\mathit{S}}_3$
[0]	0	Discharging	1 1 0
[+1]	$V_C$	Charging	0 1 1
[0]	0	Charging	1 1 1
[−1]	$-V_C$	Charging	1 0 1

Table 2. Switch states in each half cycle.

Switch	Positive Half Cycle	Negative Half Cycle
Leg a ($S_1$, $\overline{S_1}$)	PWM	ON/OFF
Leg b ($S_2$, $\overline{S_2}$)	ON/OFF	PWM
Leg c ($S_3$, $\overline{S_3}$)	PWM	PWM

3.3. Current and Voltage Stresses of Switches

The peak current and voltage for each device of the proposed topology are summarized in Table 3. It is worth highlighting that the proposed not only achieves the boosting with CG configuration by using three half-bridges but also reduces the current stress of the boost switch by one power switch in comparison to the common ground boost inverter presented in [32].

Table 3. Comparison of device stress and overall total stress between conventional and proposed boost inverter topologies.

Topology	Switch	Max Current	Max Voltage	Total Stress
Conventional Topology	$S_1,S_1^{\prime }$	$I_o$	$V_C$	$I_o{V}_C$
	$S_2,S_2^{\prime }$	$I_{\mathrm{in}}$	$V_C$	$I_{\mathrm{in}}{V}_C$
	$S_3$	$I_{\mathrm{in}}+I_o$	$V_C$	$\left(I_{\mathrm{in}}+I_o\right)V_C$
	Overall Total	–	–	$\left(3I_o+3I_{\mathrm{in}}\right)V_C$
Proposed Topology	$S_1,S_1^{\prime }$	$I_o$	$V_C$	$I_o{V}_C$
	$S_2,S_2^{\prime }$	$I_o$	$V_C$	$I_o{V}_C$
	$S_3,S_3^{\prime }$	$I_{\mathrm{in}}$	$V_C$	$I_{\mathrm{in}}{V}_C$
	Overall Total	–	–	$2\left(2I_o+I_{\mathrm{in}}\right)V_C$

Using power balance and the voltage gain $V_o/V_{\mathrm{dc}}=m/(1-D)$, the maximum dc input current is given by $I_{\mathrm{in}}={\displaystyle \frac{m}{2(1-D)}}{I}_o$. For example, at m = D = 0.8, the overall stress for the conventional topology is 9, while the stress for the proposed is 8. Figure 6 shows a comparison of the total stress factor at different modulations.

Figure 6. Comparison of the total stress factor.

4. Simulation and Experimental Results

4.1. Simulation Results

A case study was conducted using MATLAB/SIMULINK 2024b to evaluate the proposed system. For a fair comparison, the same parameters are used for both the topology of the latest topology presented in [32] and the proposed topology. The simulation parameters included an input DC voltage of 50 V, an output filter inductance of 10 mH, a switching frequency of 20 kHz, and a boost inductor of 2 mH. The duty cycle of both simulations was set to 0.75 to produce 200 V across the capacitor, as shown in Figure 7. The simulation results, presented in Figure 8, show the inductor current $I_L$ and the output current $I_{out}$ for both topologies. The better inductor current is achieved in the case of the proposed topology. The boost switch current illustrated in Figure 9 demonstrates that the proposed topology effectively reduces the current stress on switch $S_3$ compared to [32].

Figure 7. Comparison of the capacitor and the inverter voltage for: (a) The proposed topology, and (b) The conventional topology with asymmetrical stresses.

Figure 8. Comparison of the input and the output current for: (a) The proposed topology, and (b) The conventional topology with asymmetrical stresses.

Figure 9. Comparison of the boost switch S3 for (a) The proposed topology, and (b) The conventional topology with asymmetrical stresses.

4.2. Experimental Results

In order to verify the proposed topology, an experimental prototype was designed using three half-bridges and tested in the lab. A Texas Instruments DSP (TMS320F28035) was employed to generate the sinusoidal PWM scheme. The system specifications are listed in Table 4. The experimental evaluation was conducted by varying the modulation index and duty cycle to examine the operating characteristics and voltage gain capability of the proposed converter, while maintaining identical hardware configuration, switching frequency, and ambient conditions to ensure measurement consistency. Figure 10 shows the measured average capacitor voltage of 147 V when the input voltage is set to 40 V, which is approximately 6 V lower than the analytical value, with modulation index m = 0.74 and the duty cycle D = 0.74. The corresponding average inductor current and load current are 1.25 A and 0.58 A rms, respectively, indicating continuous inductor current operation with a relatively constant current ripple. Figure 11 illustrates the performance at higher power with an input voltage of 50 V, where the average inductor current reaches 3.7 A and the load current is 1.95 A rms. Hence, the acquired input power and output power are approximately 185 W and 171 W, resulting in an efficiency of approximately 92%.

Table 4. Experimental specifications.

Specification	Value
Input DC voltage, $V_{dc}$	40–60 V
Boost inductor, $L_b$	1.2 mH
DC link capacitor, C	1 mF
Output filter, $L_f$	2 mH
RLoad, $R_L$	45–125 $\Omega$
Switching frequency, $F_{sw}$	20 kHz

Figure 10. Experimental results at $V_{in}$ = 40 V, and $P_{in}$ = 50 W.

Figure 11. Experimental results at $V_{in}$ = 50 V, and $P_{in}$ = 185 W.

Further tests were performed by increasing the duty cycle D to 0.8 and 0.85, leading to capacitor voltages of 225 V and 400 V, as shown in Figure 12 and Figure 13, respectively, confirming the high voltage gain capability of the proposed topology.

Figure 12. Experimental results at $V_{in}$ = 50 V, and $P_{in}$ = 145 W.

Figure 13. Experimental results at $V_{in}$ = 60 V, and $P_{in}$ = 200 W.

The current stress of the boost switch $S_3$ was experimentally measured and is illustrated in Figure 14. The results show that the maximum current stress is approximately 5 A, which corresponds to the inductor current, while the peak output current is about 2.5 A. This confirms that the output current is diverted away from the boost switch, validating the reduced device stress characteristic of the proposed topology.

Figure 14. The current stress through the boost switch $S_3$, and the inductor current.

5. Performance Comparison

Table 5 provides a comparative analysis of recent common-ground boost inverters with similar functionality, focusing on their ability to achieve voltage boosting while maintaining a common ground configuration. The proposed inverter incorporates an additional switch, which plays a crucial role in minimizing current stress compared to [26,28,32]. The topologies in [33,34,35,37,38,39,41] provide zero leakage current; however, they suffer from discontinuous inductor current and asymmetrical required semiconductor switches. The proposed topology preserves continuous inductor current and uses symmetrical switches. Furthermore, the proposed topology does not require diodes, compared to the topologies in [33,34,35,37,39,42].

Table 5. Comparison of proposed topology with featured existing topologies in the literature.

Topology	Levels	Leakage Current	Symmetry	Input Current	Complexity		No. of Components
					Circuit	Control	S	D	L	C
[32]	3	Zero	No	Continuous	Low	Low	5	0	1	1
[32]	3	Zero	No	Continuous	Low	Low	5	0	1	1
[34]	3	Zero	No	Discontinuous	Moderate	Moderate	6	1	1	2
[35]	3	Zero	No	Discontinuous	Moderate	Moderate	6	3	2	3
[38]	3	Zero	Yes	Discontinuous	Moderate	Moderate	4	0	1	1
[36]	3	Zero	No	Continuous	Simple	Simple	4	0	1	2
[39]	3	Zero	No	Discontinuous	High	High	3	6	3	3
Proposed	3	Zero	Yes	Continuous	Low	Low	6	0	1	1

Note: Circuit complexity refers to the inherent circuit complexity and overall hardware requirements. Control complexity denotes the difficulty of implementing modulation and control strategies.

6. Closed-Loop Performance

To validate the dynamic performance of the proposed topology in grid-connected mode, a simulation case study with a finite control set model predictive controller (FCSMPC) has been designed. The complete closed-loop controller stages are shown in Figure 15. The control stage has to regulate the DC-link voltage at its reference ($v_{DC}$ = $v_{DC,ref}$), which is made by a separate PI controller. The closed loop has to control DC-input current at its reference, which is determined mainly by the MPPT algorithm ($I_L$ = $I_{L,ref}$). In addition, control of the injected AC-side grid current is essential to generate sinusoidal grid-following current based on active $P_{ref}$ and reactive powers $Q_{ref}$ ($i_o$ = $i_{o,ref}$). The control of $I_L$ and $i_o$ is made using FCSMPC control, based on the presented basis in [42]. Closed-loop case study parameters are shown in Table 6.

Figure 15. Closed-loop control stages using cascaded PI and FCSMPC method.

Table 6. Closed-loop case study parameters.

Parameter	Value
Input DC-side voltage ($V_{in}$, $V_{PV}$)	75 V
DC-link reference voltage $v_{DC}$	400–420 V
$L_1$ DC-side inductance	3.5 mH
AC grid frequency $f_l$	50 Hz
AC-peak voltage	311 V
AC filter’s inductance $L_f$	3.5 mH
AC filter’s resistance $R_f$	50 m$\Omega$
FCSMPC Sampling frequency $f_s$ (=$1/T_s$)	50 kHz

The considered scenarios are:

1.

Case 1: step change in reference input power with a change in the inductor current reference from 15 A to 35 A. The results of this case are shown in Figure 16.

Figure 16. Performance of the closed-loop FCSMPC controller with the proposed topology at step change in inductor current from 15 A to 35 A reference. (a) Inverter voltage. (b) Grid current and scaled voltage. (c) DC-link regulation. (d) Inductor input current control.

2.

Case 2: step change in DC-link reference voltage with a change in the reference from 400 V to 420 V, as shown in Figure 17.

Figure 17. Performance of the closed-loop FCSMPC controller with the proposed topology at step change in dc-link reference from 400 V to 420 V. (a) Inverter voltage. (b) Grid current and scaled voltage. (c) DC-link regulation. (d) Inductor input current control.

3.

Case 3: step down in reference input inductor current reference from 35 A to 25 A. The results of this case are shown in Figure 18.

Figure 18. Performance of the closed-loop FCSMPC controller with the proposed topology at step change in inductor current from 35 A to 25 A reference. (a) Inverter voltage. (b) Grid current and scaled voltage. (c) DC-link regulation. (d) Inductor input current control.

4.

Case 4: step in reactive power injection reference from 0 VAR to 1000 VAR. The results of this case are shown in Figure 19.

Figure 19. Performance of the closed-loop FCSMPC controller with the proposed topology at reactive power injection from 0 to 1000 VAR. (a) Inverter voltage. (b) Grid current and scaled voltage. (c) DC-link regulation. (d) Inductor input current control.

6.1. Case 1: Input Power Increased

The results of this scenario are shown in Figure 16. The inverter output voltage is shown in Figure 16a. It can be seen that the injected AC current in Figure 16b is sinusoidal and follows the grid side voltage, even if there is a step increase in the input power from the DC source. In addition, the regulated DC-link voltage follows the reference 400 V signal in both cases, as shown in Figure 16c. The input inductor current in Figure 16d tracks the reference current change from 15 A to 35 A quickly and accurately, owing to the FCSMPC method. The results demonstrate the dynamic performance of the topology in response to a step-change increase in input power from PV panels.

6.2. Case 2: Change of DC-Link Reference Voltage

In this scenario, the reference signal for DC-link regulation is changed from 400 V to 420 V. Because there are no changes in input power or reactive power, the DC and AC currents remain constant in this scenario. DC-link regulation is achieved quickly, with minimal peak overshoot, due to the PI control design, as shown in Figure 17c. In addition, there are no fluctuations or transients in the DC and AC currents in this scenario, as shown in Figure 17b and Figure 16d, respectively.

6.3. Case 3: Input Power Decreased

The corresponding results for this scenario are shown in Figure 18. The reference input current is decreased from 35 A to 25 A as shown in Figure 18d. The FCSMPC achieves fast response and accurate tracking in both cases with high performance during the step change. In addition, the regulation of AC current and DC-link voltage are preserved at their references as shown in Figure 18b and Figure 18c, respectively.

6.4. Case 4: Reactive Power Injection to the Grid

In this scenario, the dynamic performance of the proposed topology and the designed controllers is tested under a reactive power injection of 1000 VAR. The inverter output voltage is shown in Figure 19a. It can be seen that the AC current has a phase shift from the grid voltage and tracks the reference current signal, as shown in Figure 19b. Furthermore, the DC-link voltage regulation is free from fluctuations and transients in this scenario, as shown in Figure 19c. As there is no change in the input-side active power, Figure 19d shows a constant, transactions-free DC-side current tracking.

7. Conclusions

Modern boost inverters extensively employ half-bridge configurations due to their modularity and suitability for high-power-density applications. This paper presented a symmetrical switching topology derived from the common-ground boost inverter using a half-bridge structure. The proposed converter provides voltage boosting while preserving a common-ground configuration, as confirmed through analytical derivation of the operating principle, voltage gain, and modulation limits. Compared with conventional common-ground boost inverters, the proposed topology reduces the peak current stress on the main boost switch from $I_L$ + $I_{out}$ to $I_L$ resulting in a lower overall device stress and improved reliability. These advantages are verified by steady-state and switching waveforms obtained from both simulation and experimental results, which closely match the theoretical analysis. The simple complementary gating scheme further supports practical implementation and integration with renewable energy systems. Overall, the analytical, simulation, and experimental results demonstrate the effectiveness and practical applicability of the proposed topology. Future research includes developing an industrial version of the proposed topology, measuring power density and loss breakdown, and studying its efficiency across various operating conditions.