Enhancing Scalability and Reliability of 3D ONoCs Through Optimized Routing and Mathematical Modeling

Abstract

The scalability of multiprocessor networks on-chip is restricted by the performance of on-chip interconnects. Optical networks-on-chip (ONoCs) offer ultra-high bandwidth and energy-efficient solutions for these bottlenecks. Although 2D ONoCs have several advantages, scalability is a challenge because of limited chip area; hence, recently, research has been focused on 3D integration. This paper presents a novel 3D ONoC architecture based on two newly designed routers, the Horizontal Dimension Order Routing Aware Router for intra-layer communication and the Vertical Optical Router for inter-layer connectivity. To evaluate the performance of the routers and the proposed ONoC, comprehensive mathematical models are developed for insertion loss, crosstalk noise, and signal-to-noise ratio (SNR) measurements. The results show that the proposed design reduces average insertion loss by 31.28% and improves worst-case SNR by 9.23% compared with existing 3D ONoC designs. It also outperforms traditional designs in terms of Bit Error Rate (BER). The hybrid switching approach is used for XYZ dimension order routing, enabling high-speed data transmission and avoiding the need for buffering and its latency. Furthermore, the results show that vertical chip expansion improves SNR and BER over horizontal expansion, taking a step toward reliable, high-performance all-optical computing.

1. Introduction

In recent years, integrating multiple processing cores into a single multiprocessor system-on-chip (MPSoC) has significantly increased processor computational power. The overall performance of these systems is increasingly determined not merely by individual processor speed but by the efficiency of the underlying communication fabric [1,2]. To overcome the limitations of traditional interconnects, optical networks-on-chip (ONoCs) have emerged as a promising alternative that provides ultra-high processing with minimal transmission latency, smaller size, and low power consumption [3].

Previous research primarily focused on 2D ONoC architectures, which face critical challenges for scalable solutions due to their limited chip surface area [4,5,6]. Therefore, demand for multicore and multilayer processors is increasing, driving research toward three-dimensional (3D) interconnect technologies that use stacked photonic and electronic layers to maintain a compact footprint while providing high capacity. To optimize the performance of 2D ONoC architectures, researchers have proposed various micro-ring resonator (MRR)-based five-port optical routers [7,8,9,10,11,12,13]. These architectures primarily focus on reducing insertion loss, minimizing crosstalk noise, and enabling non-blocking communication. Several researchers have performed analytical modeling of 2D mesh, folded-torus, and fat-tree ONoCs [14,15,16,17,18] and optical switching [19] technologies.

3D ONoC architectures typically use six seven-port routers to support vertical routing [20,21,22,23,24,25,26,27,28]. The concept of 3D optical NoCs was introduced by [21]. A structured 3D mesh-based architecture for multiprocessor systems was proposed, and the work was further extended by incorporating topology design and adaptive [22] routing in 3D torus ONoCs [26]. Furthermore, ref. [27] proposed a low-insertion-loss, non-blocking micro-ring-based optical router, and ref. [23] introduced a dimension-order-routing-based non-blocking router (DORR) for 3D photonic networks. The authors of [28] presented reliability through fault-tolerant routing mechanisms for ONoCs. However, despite these advances, research on analytical modeling for 3D ONoCs remains limited. Existing studies primarily focus on structural design, routing strategies, or individual parameters such as insertion loss, but lack a unified analytical framework that simultaneously models insertion loss, crosstalk noise, SNR, and BER across multilayer communication paths.

To tackle these limitations, we propose a novel 3D ONoC architecture that differs from existing designs [23,27,28] by employing two specially optimized routers: a six-port Horizontal Dimension Order Routing Aware Router (HDORAR) for intra-layer communication and a three-port Vertical Optical Router (VOR) for inter-layer communication. Our approach reduces routing complexity and insertion loss in vertical paths and also enhances the scalability of ONoCs. We also developed analytical models to analyze insertion loss, crosstalk, and SNR for intra-layer and inter-layer communication. These models enable accurate BER estimation. Compared with the 3D ONoC approaches in [20,21,22,23,24,25,26,27,28], this work separates planar HDORAR and vertical VOR functions and focuses on network-level physical-layer analytical modeling. The remainder of this paper is organized as follows: Section 2 describes the proposed routers and 3D ONoC architecture. Section 3 provides the detailed mathematical models. Section 4 provides quantitative analysis, and Section 5 concludes the paper.

2. Architecture of 3D ONoC Using HDORAR and VOR

The proposed 3D ONoC comprises a multicore multilayer architecture with a U × V × W mesh topology. It consists of an electronic layer containing processing elements for control and a photonic layer for high-speed optical communication. Through-Silicon Photonic Vias (TSPVs) provide vertical optical connections between stacked layers. This architecture is a network of Intellectual Property (IP) cores linked via special optical routers arranged in a 4 × 4 × 3 mesh topology. To optimize communication efficiency, the architecture separates routing responsibilities: the Horizontal Dimension-Order Routing-Aware Router (HDORAR) handles intra-layer switching, and the Vertical Optical Router (VOR) handles inter-layer connections. The HDORAR is a six-port router that interconnects neighboring routers and a local core within the same layer. It utilizes an optimized internal fabric consisting of 14 waveguide crossings, 16 micro-ring resonators (MRRs), and 16 waveguide bends, as shown in Figure 1. This optimized router uses fewer components than conventional 3D routers [21]; hence, it reduces insertion loss and crosstalk accumulation [22,29,30].

Figure 1. Horizontal Dimension-Order Routing-Aware Router (HDORAR).

Minimizing these components is essential, as waveguide crossings and MRRs are primary sources of insertion loss and crosstalk noise. For vertical communication, the three-port VOR, as shown in Figure 2, interconnects routers across multiple layers. The vertical layer spacing is treated independently of the horizontal router pitch; each inter-layer transition includes a technology-dependent loss and, when required, a vertical crosstalk coefficient. Unlike conventional multi-port routers, the VOR is a simplified three-port router dedicated to inter-layer communication, which significantly reduces routing complexity and vertical insertion loss.

Figure 2. Vertical Optical Router (VOR).

By integrating these routers, we create a novel 3D ONoC architecture for a 4 × 4 × 3 mesh topology, as shown in Figure 3. This architecture uses TSPVs to enable efficient vertical connectivity between multiple photonic layers. Existing 3D ONoC architectures reported in [23,27,28] use the same router for both intra-layer and inter-layer communication, whereas the proposed architecture separates these functions using HDORAR and VOR, reducing the number of photonic components and improving scalability.

Figure 3. Architecture of 4 × 4 × 3 3D ONoC.

The system employs a hybrid switching approach in which the electronic control unit manages path setup, and the photonic path transmits high-speed optical data through the reserved path without buffering. This hybrid switching permits efficient path setup while maintaining high-speed optical data transmission. During setup, each hop reserves the requested output only if it is available. If the requested resource is busy, the source releases the partial reservations and retries after a random backoff interval. An end-to-end acknowledgment confirms the path before optical data transmission.

The XYZ dimension order routing algorithm governs path selection. In this work, non-blocking refers to admissible input–output paths inside the router fabric. Simultaneous end-to-end circuit requests can still contend for shared optical links. We implement XYZ routing using HDORAR for X–Y traversal and VOR for Z-direction communication. In the proposed architecture, there is a unique ID (a, b, c) to each processor, where a ϵ {1, 2, 3, … U}, b ϵ {1, 2, 3,…V}, c ϵ {1, 2, 3, … W}, and the same ID is used for its local router, which facilitates a straightforward addressing across the 3D grid.

To illustrate the operation, consider the longest path in a 4 × 4 × 3 network from processor (1,1,1) to (4,4,3). Initially, the control unit at the source node (1,1,1) generates a path-setup packet. After the receiver accepts it, the required MRRs along the path activate. The optical signal is then transmitted sequentially through the X-dimension to the router at (4,1,1), then switched into the Y-dimension until it arrives at (4,4,1). Finally, the VOR switches the data into the Z-dimension, moving it from the first layer to the third layer, where the optical router at (4,4,3) receives it and delivers it to the local processor. This example illustrates deterministic route construction; it does not imply zero contention for simultaneous network requests. The dimension-order approach ensures high-speed, reliable data movement while maintaining signal integrity across the interconnects.

3. Mathematical Modeling

The architectural diversity of 3D ONoCs requires mathematical models to enable accurate quantitative analysis. The performance of these networks is governed by their physical layer components, where the integration of optical waveguides, crossings, and MRRs introduces signal degradation. Consequently, we first perform comprehensive mathematical modeling at the router level and then at the network level to evaluate insertion loss, crosstalk noise, and SNR. The parameters used in this study are given in Table 1.

Table 1. Parameters used for the study.

Parameter	Value	Reference
$L_c$	0.15 dB	[23]
$L_b$	0.005 dB	[23]
$L_{on}$	0.5 dB	[23]
$L_{off}$	0.005 dB	[23]
$L_{wg}$	0	Assumption
$k_x$	−38.5 dB	[15]
Inter-layer transition loss	0	Assumption
TSPV loss	0	Assumption
PD responsivity	0	Assumption
laser power	1 mW	[15]

3.1. Mathematical Modeling for Performance of the Optical Router

This section details the modeling of a six-port optical router within a 3D ONoC. The ports are indexed as 0 (Core), 1 (West), 2 (North), 3 (East), 4 (South), and 5 (Vertical). The 3D ONoC considered for modeling has a general size of U × V × W. The horizontal and vertical inter-router links are treated separately. The first parameter considered is the insertion loss for the router R₁($x,y,z$) from the ith port to the jth port, and it is given as

$$L_{(i,j)}\left(x,y,z\right)={\{}_{L_{(i,j)}^{R1}\left(x,y,z\right)L_p^{H}j\ne 0}^{L_{(i,0)}^{R1}\left(x,y,z\right)j=0}$$

(1)

where $i,j\epsilon \left\{0,1,\dots \dots \dots ,5\right\},x\epsilon \left\{1,2,\dots \dots \dots U\right\},y\epsilon \left\{1,2,\dots \dots \dots ,V\right\},z\epsilon \left\{1,2,\dots \dots \dots ,W\right\}$ and H is the hop length, i.e., the length between the routers of ONoC. $L_{(i,j)}^{R1}\left(x,y,z\right)$ represents the insertion loss of router R₁($x,y,z$) from the ith port to jth port, given by

$$L_{(i,j)}^{R1}\left(x,y,z\right)=S_{L(i,j)}\left(x,y,z\right)L_p^{w_{l(i,j)}(a,b,c)}$$

(2)

This loss includes switching loss $S_{L(i,j)}\left(x,y,z\right)$ and propagation loss $L_P$ for the waveguide length $w_{l(i,j)}(x,y,z)$. For chip size c, the hop length for U × V × W ONoC is obtained by

$$H\cong \sqrt{{\displaystyle \frac{C}{U\times V\times W}}}$$

(3)

The switching loss of an optical router from the input port to the output port is determined by the cumulative loss incurred by physical components along that specific internal path. Switching loss from the ith port to the jth port of the router is obtained using the number of waveguide crossings $N_{c(i,j)}$, the number of bends $N_{b(i,j)}$, the number of MRRs in the ON state $N_{on(i,j)}$, and the number of MRRs in the OFF state $N_{off(i,j)}$ in the path and written as

$$S_{L(i,j)}\left(x,y,z\right)=N_{c(i,j)}{L}_c+N_{b(i,j)}{L}_b+N_{on(i,j)}{L}_{on}+N_{off(i,j)}{L}_{off}$$

(4)

where $L_b,$ $L_c$, $L_{off}$, and $L_{on}$ represent bending loss, crossing loss, and insertion loss of MRR in the OFF state and the ON state, respectively. The resulting output power at the jth port of R₁($a,b,c$) when power input $P_i^{in}$ is applied is given by

$$P_{(i,j)}^o\left(x,y,z\right)=P_i^{in}\left(x,y,z\right)L_{\left(i,j\right)}(x,y,z)$$

(5)

where $L_{\left(i,j\right)}$ is the total insertion loss for the selected path. To accurately quantify signal degradation, the router’s operational status, $S_{\left(i,j\right)}(x,y,z)$, must be defined. The status of router R₁($x,y,z$) indicates whether optical data can be received on other ports while optical data is transferred from the ith port to the jth port, and is represented as $S_{\left(i,j\right)}(x,y,z)$. To understand this, assume $I_p^0, I_q^0, I_r^0, I_s^0, I_t^0 \mathrm{a}\mathrm{n}\mathrm{d} I_u^0$ are the input ports for the output ports $I_0^1, I_1^1, I_2^1, I_3^1, I_4^1 and I_5^1$ respectively. The status $S_{(3,2)}\left(x,y,z\right)(I_{-1}^0,I_{-1}^0,I_3^0,I_{-1}^0,I_1^0,I_4^0)$ for the east port to north port path indicates that optical signals are available at the north port, south port, and vertical port due to signal applied at the east port, west port, and south port, respectively. Here, −1 indicates that the signal is not available at that output port; therefore, the core, east, and west ports are free. This status is necessary to identify crosstalk noise in a particular router path. $C_{(i,j)}\left(x,y,z{S}_{\left(i,j\right)}(x,y,z)\right)$ is the crosstalk noise added under the status $S_{\left(i,j\right)}(x,y,z)$ to the optical signal traveling from the ith port to the jth port, and is given by

$$\begin{array}{c}{C}_{(i,j)}\left(x,y,z, S_{(i,j)}\left(x,y,z\right)\right)=\\ P_0^{in}\left(x,y,z\right)k_{(i,j,0)}\left(S_{(i,j)}\left(x,y,z\right)\right) +P_1^{in}\left(x,y,z\right)k_{(i,j,1)}\left(S_{(i,j)}\left(x,y,z\right)\right)+\\ P_2^{in}\left(x,y,z\right)k_{(i,j,2)}\left(S_{(i,j)}\left(x,y,z\right)\right)+P_3^{in}\left(x,y,z\right)k_{(i,j,3)}\left(S_{(i,j)}\left(x,y,z\right)\right)+\\ P_4^{in}\left(x,y,z\right)k_{(i,j,4)}\left(S_{(i,j)}\left(x,y,z\right)\right)+P_5^{in}\left(x,y,z\right)k_{(i,j,5)}\left(S_{(i,j)}\left(x,y,z\right)\right)\end{array}$$

(6)

$k_{(i,j,m)}$ is the path crosstalk noise coefficient from the ith port to the jth port introduced by the input optical signal $P_m^{in}\left(x,y,z\right)$ at the mth port in the optical router R₁($x,y,z$) under $S_{(i,j)}\left(x,y,z\right)$ status, and it is written as

$$k_{(i,j,m)}\left(dB\right)={L_b}^{N_{b\left(k,l\right)}}{L_c}^{N_{c\left(k,l\right)}}{L_{on}}^{N_{on\left(k,l\right)}}{L_{off}}^{N_{off\left(k,l\right)}}{L}_{wg}{k}_x$$

(7)

where $L_{wg}$ is the waveguide loss, and k_x is the crosstalk coefficient of the crossing waveguide or MRR. Linear transmission factors along the leakage path are shown in (7). In this work, we consider first-order crosstalk, and we do not explicitly consider power that leaks through another device. Higher-order crosstalk can be added recursively if it is considered.

3.2. Mathematical Modeling for Performance of 3D Optical Network-on-Chip

After developing the mathematical model for individual optical routers, the framework is extended to the 3D ONoC network level to enable system-wide reliability assessment. For a source-to-destination route P, the total insertion loss is the sum of the dB losses of the router paths, horizontal waveguide segments, and vertical transitions. In the U × V × W 3D ONoC, signal integrity is dictated by the cumulative effect of physical-layer degradations across multiple layers. At the network level, the source-to-destination insertion loss $L_{(s,d)}$ for the 3D ONoC is defined as the summation of the insertion losses of all routers encountered along the routing path in the X, Y, and Z dimensions:

$$L_{(s,d)}=\sum L_x^{R1}+\sum L_y^{R1}+\sum L_z^{R1}$$

(8)

where $L_x^{R1}$, $L_y^{R1}$, and $L_z^{R1}$ represent the insertion losses of the router R₁ for the s to d path in the x, y, and z directions, respectively. This model accounts for the hop length and the specific internal losses of the HDORAR and VOR architectures. Different paths in U × V × W ONoC with six-port and three-port optical routers for SNR analysis are considered. Because the ONoC has multiple layers, more paths are available for data transmission. We used four different longest paths, each with different possible crosstalk noise, to analyze the effect of insertion loss and crosstalk noise on the ONoC SNR.

• Path 1: Transmission from the processor of router R₁(1,1,1) to the processor of router R₁(U, V, W). As an outer-side path, it typically experiences the lowest cumulative crosstalk noise.
• Path 2: Transmission from the processor of router R₁(1,1,1) to the processor of router R₁(U − 1, V, W).
• Path 3: Transmission from the processor of router R₁(1,2,1) to the processor of router R₁(U, V, W).
• Path 4: Transmission from the processor of router R₁(1,2,1) to the processor of router R₁(U − 1, V, W). Being an inner-side path, it is subjected to the highest crosstalk noise due to the high density of surrounding active waveguides and routers.

While mathematical models are developed for all four paths, this work presents a detailed analysis of Path 4 to demonstrate the worst-case performance scenario. The modeling process begins with a generalized mathematical framework. It is subsequently refined by applying the specific physical parameters of the HDORAR and VOR architectures, including their optimized counts of waveguide crossings and MRRs. This can be extended for any path in a similar 3D ONoC.

Network-level performance is ultimately determined by the SNR, the ratio of received signal power to accumulated noise power at the destination node. The SNR for the fourth path is given by

$${SNR}_{(1,2,1)(U-1,V,W)}=10\mathit{log}({\displaystyle \frac{{\mathit{SP}}_{(1,2,1)(U-1,V,W)}}{{\mathit{NP}}_{(1,2,1)(U-1,V,W)}}})$$

(9)

Moreover, the Bit Error Rate (BER) is a critical metric for assessing ONoC reliability, as it is directly dictated by the SNR and cumulative crosstalk noise. For an On-Off Keying Non-Return to Zero (OOK-NRZ) modulation scheme, the BER is modeled as

$$BER={\displaystyle \frac{1}{2}}erfc\left({\displaystyle \frac{1}{2\sqrt{2}}}\sqrt{SNR}\right)$$

(10)

The signal power is derived by applying the network-level insertion loss to the input power, while the noise power is the summation of all first-order crosstalk (and potentially infinite-order crosstalk) leaked into the primary signal path from concurrent data streams. Using XYZ dimension-order routing, this modeling approach enables quantitative assessment of any transmission path within the 3D ONoC, ensuring the architecture meets stringent Bit Error Rate (BER) requirements for reliable high-speed computing. Figure 4 illustrates the fourth transmission path within the 4 × 4 × 3 3D ONoC architecture, and in this diagram:

Figure 4. Fourth path of 3D ONoC.

▪

Red hexagons represent the six-port intra-layer routers (HDORAR).

▪

Black triangles denote the three-port vertical routers (VOR) used for inter-layer communication.

▪

Vertical orange lines indicate the TSPVs that interconnect the layers.

▪

The solid violet line traces the primary signal path.

▪

Green dotted lines indicate crosstalk noise propagation from concurrent data transmissions.

The diagram highlights the inner-side path from processor R₁(1,2,1) to R₁(U − 1, V, W), modeled specifically to analyze the effects of high-intensity crosstalk and insertion loss on the system’s SNR.

Crosstalk noise generated in the routers of the fourth path (R₁(1,2,1) to R₁(U − 1, V, W)) under status $S_{(i,j) }\left(x,y,z\right)$ is represented by $C_{(i,j)\_4th}\left(x,y,z,{ S}_{(i,j) }\left(x,y,z\right)\right)$. So, crosstalk noise from the ith port to the jth port for the whole path is obtained as below:

For $x=1, y=2,z=1$

$$C_{(0,3)}=P_{in}(L_{\left(0,4\right)}{L}_P^H{k}_{\left(0,3,2\right)}+L_{\left(0,2\right)}{L}_P^H{k}_{\left(0,3,4\right)}+L_{\left(0,1\right)}{L}_P^H{k}_{\left(0,3,3\right)}+{ L}_{(0,5)}{L}_{(6,8)}{L}_P^H{k}_{(0,3,5)})$$

(11)

For $x\in \left(2,U-2\right), y=2, z=1$

$$C_{(1,3)}=P_{in}(k_{\left(1,3,0\right)}+{L_{\left(0,4\right)}{L_P^{H}k}_{\left(1,3,2\right)}+L_{\left(0,2\right)}{L}_P^H{k}_{\left(1,3,4\right)}+L}_{\left(0,1\right)}{L}_P^H{k}_{\left(1,3,3\right)}+L_{(0,5)}{L}_{(6,8)}{L_P^{H}k}_{(1,3,5)})$$

(12)

For $x=U-1, y=2, z=1$

$$C_{(1,2)}=P_{in}(k_{\left(1,2,0\right)}+L_{\left(0,4\right)}{L}_P^H{k}_{\left(1,2,2\right)}+{L_{\left(0,2\right)}{L}_P^H{k}_{\left(1,2,4\right)}+L}_{\left(0,1\right)}{L}_P^H{k}_{\left(1,2,3\right)}+L_{(0,5)}{L}_{(6,8)}{L}_P^H{k}_{(1,2,5)}).$$

(13)

For $x=U-1, y\in \left(3,V-1\right), z=1$

$$C_{(4,2)}=P_{in}\left(k_{\left(4,2,0\right)}+L_{\left(0,3\right)}{L}_P^H{k}_{\left(4,2,1\right)}+L_{\left(0,4\right)}{L}_P^H{k}_{\left(4,2,2\right)}+L_{\left(0,1\right)}{L}_P^H{k}_{\left(4,2,3\right)}+{ L}_{\left(0,5\right)}{L}_{\left(6,8\right)}{L}_P^H{k}_{\left(4,2,5\right)}\right)$$

(14)

For $x=U-1, y=V, z=1$

$$C_{(4,5)}={ P}_{in}(k_{(4,5,0)}+L_{(0,3)}{L}_P^H{k}_{(4,5,1)}+L_{(0,1)}{L}_P^H{k}_{(4,5,3)}+L_{(0,5)}{L}_{(6,8)}{L}_P^H{k}_{(4,5,5)})$$

(15)

For

$$x=U-1, y=V, z\in \left(2,W-2\right)$$

(16)

$$C_{(8,7)\_1}=P_{in}{L}_{(0,5)}{L}_P^H{k}_{(8,7,6)}$$

For $x=U-1, y=V, z=W-1$

$$C_{(8,7)\_2}=P_{in}(L_{(0,5)}{L}_P^H{k}_{(8,7,6)}+L_{(0,5)}{L}_P^H{k}_{(8,7,7)})$$

(17)

For $x=U-1, y=V, z=W$

$$C_{(5,0)}={ P}_{in}(k_{(5,0,0)}+L_{(0,2)}{L}_P^H{k}_{(5,0,4)}+L_{(0,1)}{L}_P^H{k}_{(5,0,3)}+L_{(0,3)}{L}_P^H{k}_{(5,0,1)})$$

(18)

Noise power in the fourth path is obtained using crosstalk noise and insertion loss in the path and is given by

$$\begin{gathered} {NP}_{\left(1,2,1\right)\left(U-1,V,W\right)}=C_{\left(0,3\right)}\left(1,2,1\right)L_{\left(1,3\right)}^{U-3}{L}_{\left(1,2\right)}{L}_{\left(4,2\right)}^{V-3}{L}_{\left(4,5\right)}{L}_{\left(8,7\right)}^{W-2}{L}_{\left(5,0\right)}{L}_P^{H(U+V+W-5)} \\ {+L}_{\left(1,2\right)}{L}_{\left(4,2\right)}^{V-3}{L}_{\left(4,5\right)}{L}_{\left(8,7\right)}^{W-2}{L}_{\left(5,0\right)}\left({\displaystyle {\sum }_{m=2}^{U-2}}{L}_{\left(1,3\right)}^{U-2-m}{L}_P^{H(U+V+W-4-m)}{C}_{\left(1,3\right)}\left(m,2,1\right)\right) \\ +C_{\left(1,2\right)}\left(U-1,2,1\right)L_{\left(4,2\right)}^{V-3}{L}_{\left(4,5\right)}{L}_{\left(8,7\right)}^{W-2}{L}_{\left(5,0\right)}{L}_P^{H(V+W-3)} \\ +L_{\left(4,5\right)}{L}_{\left(8,7\right)}^{W-2}{L}_{\left(5,0\right)}\left({\displaystyle {\sum }_{n=3}^{V-1}}{L}_{\left(4,2\right)}^{V-1-n}{L}_P^{H(V+W-1-n)}{C}_{\left(4,2\right)}\left(U-1,n,1\right)\right) \\ {+C}_{\left(4,5\right)}\left(U-1,V,1\right)L_{\left(8,7\right)}^{W-2}{L}_{\left(5,0\right)}{L}_P^{H(W-1)} \\ +L_{\left(5,0\right)}\left({\displaystyle {\sum }_{o=2}^{W-2}}{L}_{\left(8,7\right)}^{W-2-o}{L_P^{H(W-o)}C}_{\left(8,7\right)\_1}\left(U-1,V,o\right)\right) \\ +{ L}_{(5,0)}{L}_P^H{C}_{(8,7)\_2}\left(U-1,V,W-1\right)+C_{(5,0)}(U-1,V,W) \end{gathered}$$

(19)

Signal power at the output port of the last router in the path can be obtained using input power and insertion loss and written as

$${SP}_{(1,2,1)(U-1,V,W)}=P_{in}{L}_{(0,3)}{L}_{(1,3)}^{U-3}{L}_{(1,2)}{L}_{(4,2)}^{V-3}{L}_{(4,5)}{L}_{(8,7)}^{W-2}{L}_{(5,0)}{L}_P^{H(U+V+W-5)}$$

(20)

3.3. Mathematical Model of Fourth Path Using HDORAR and VOR

The general mathematical model of the 3D ONoC is applied to the ONoC designed using the HDORAR and VOR. The fourth path is used to model crosstalk noise and SNR. Figure 5 shows the fourth-longest path along with crosstalk noise at various locations in the HDORAR- and VOR-based 3D ONoC. The crosstalk noise for this path at various locations is written below as ${C\prime }_{(i,j)}$. It is evident that, due to the efficient design of optical routers, crosstalk noise at some locations in the path is reduced to zero.

Figure 5. Fourth path of 3D ONoC using HDORAR and VOR.

For $x=1, y=2, z=1$

$${C\prime }_{(0,3)}=P_{in}(L_{(0,4)}{L}_P^H{k}_{(0,3,2)}+L_{(0,2)}{L}_P^H{k}_{(0,3,4)}+L_{(0,5)}{L}_{(6,8)}{L}_P^H{k}_{(0,3,5)})$$

(21)

For $x\in \left(2,U-2\right), y=2, z=1$

$${{C\prime }_{(1,3)}=P}_{in}(k_{\left(1,3,0\right)}+{L_{\left(0,4\right)}{L}_P^H{k}_{\left(1,3,2\right)}+L_{\left(0,2\right)}{L_P^{H}k}_{\left(1,3,4\right)}+L}_{\left(0,1\right)}{L_P^{H}k}_{\left(1,3,3\right)}+L_{(0,5)}{L}_{(6,8)}{L}_P^H{k}_{(1,3,5)})$$

(22)

For $x=U-1, y=2, z=1$

$${C\prime }_{(1,2)}=0$$

(23)

For $x=U-1, y\in \left(3,V-1\right), z=1$

$${C\prime }_{(4,2)}=P_{in}(k_{\left(4,2,0\right)}+L_{\left(0,3\right)}{L}_P^H{k}_{\left(4,2,1\right)}+L_{\left(0,1\right)}{L}_P^H{k}_{\left(4,2,3\right)}+{ L}_{(0,5)}{L}_{(6,8)}{L}_P^H{k}_{(4,2,5)})$$

(24)

For $x=U-1, y=V, z=1$

$${C\prime }_{(4,5)}=P_{in}(L_{(0,3)}{L}_P^H{k}_{(4,5,1)}+L_{(0,1)}{L}_P^H{k}_{(4,5,3)}+L_{(0,5)}{L}_{(6,8)}{L}_P^H{k}_{(4,5,5)})$$

(25)

For $x=U-1, y=V, z\in \left(2,W-2\right)$

$${C\prime }_{(8,7)\_1}=0$$

(26)

For $x=U-1,y=V,z=W-1$

$${C\prime }_{(8,7)\_2}=0$$

(27)

For $x=U-1, y=V, z=W$

$${C\prime }_{(5,0)}=P_{in}(k_{(5,0,0)}+L_{(0,1)}{L}_P^H{k}_{(5,0,3)}+L_{(0,3)}{L}_P^H{k}_{(5,0,1)})$$

(28)

Noise power in the fourth path is given by

$$\begin{gathered} {NP}_{\left(1,2,1\right)\left(U-1,V,W\right)}={C\prime }_{\left(0,3\right)}\left(1,2,1\right)L_{\left(1,3\right)}^{U-3}{L}_{\left(1,2\right)}{L}_{\left(4,2\right)}^{V-3}{L}_{\left(4,5\right)}{L}_{\left(8,7\right)}^{W-2}{L}_{\left(5,0\right)}{L}_P^{H(U+V+W-5)} \\ {+L}_{\left(1,2\right)}{L}_{\left(4,2\right)}^{V-3}{L}_{\left(4,5\right)}{L}_{\left(8,7\right)}^{W-2}{L}_{\left(5,0\right)}\left({\displaystyle {\sum }_{m=2}^{U-2}}{L}_{\left(1,3\right)}^{U-2-m}{L}_P^{H(U+V+W-4-m)}{C\prime }_{\left(1,3\right)}\left(m,2,1\right)\right) \\ +L_{\left(4,5\right)}{L}_{\left(8,7\right)}^{W-2}{L}_{\left(5,0\right)}\left({\displaystyle {\sum }_{n=3}^{V-1}}{L}_{\left(4,2\right)}^{V-1-n}{L}_P^{H(V+W-1-j)}{C\prime }_{\left(4,2\right)}\left(U-1,n,1\right)\right) \\ {+C\prime }_{(4,5)}\left(U-1,V,1\right)L_{(8,7)}^{W-2}{L}_{(5,0)}{L}_P^{H(W-1)}+{C\prime }_{\left(5,0\right)}(U-1,V,W) \end{gathered}$$

(29)

where

$$\begin{array}{l}{K}_{(0,3,2)}=L_{Poff}^3{L}_C^3{K}_{C_{1x2}}{L}_P^D+L_{Poff}^4{L}_C^4{K}_P{L}_P^D, K_{(0,3,3)}=0, K_{(0,3,1)}=0,\\ K_{(0,3,4)}={L_{Poff}K}_{C_{2x2}}{L}_P^D, K_{(0,3,5)}=L_{Poff}^3{L}_C^4{L_{b}K}_C{L}_P^D,\\ K_{(1,3,0)}=L_{Poff}^4{L}_C^2{L_b^{3}K}_{C_{1x2}}+L_{Poff}^5{L}_C^4{L_b^{3}K}_P, K_{(1,3,1)}=L_{Poff}^4{L}_C^2{K}_C{L}_P^D+L_{Poff}^4{L}_C^4{L_{b}K}_P{L}_P^D,\\ K_{(1,3,3)}=L_{Poff}^2{L}_C^2{L_b^{2}K}_C{L}_P^D, K_{(1,3,2)}=L_{Poff}^3{L}_C^3{K}_{C_{2x1}}{L}_P^D,\\ K_{(1,3,5)}=L_C^2{L_{Poff}{L}_{b}K}_{C_{1x2}}{L}_P^D, K_{(1,2,0)}=0, K_{(1,2,2)}=0, K_{(1,2,3)}=0, K_{(1,2,5)}=0,\\ K_{(4,2,0)}=L_{Poff}{L_{C}K}_{C_{2x2}}, K_{(4,2,1)}=(K_P+L_{Poff}^2{L_{C}K}_C)L_P^D,\\ K_{(4,2,2)}=0, K_{(4,2,3)}=L_{Poff}^2{L}_C^3{L_b^{2}K}_{C\_2x1}{L}_P^D,\\ K_{(4,2,5)}={{L_{C}L}_{Poff}{L}_{b}K}_C{L}_P^D+L_{Poff}^3{L}_C^5{L_b^{3}K}_P{L}_P^D,\\ \begin{array}{c}{K}_{(4,5,0)}=0,K_{(4,5,2)}=0,K_{(4,5,1)}={({L_{Poff}^{2}L}_C^2{L}_b K_P+L_{Poff}^{3}L}_C^3{L_b^{2}K}_{C\_1x2}+\\ L_{Pon}{L_{Poff}^{4}L}_C^4{L_b^{2}K}_P)L_P^D,K_{(4,5,3)}={{(K}_P+L}_{Poff}^2{L}_C{L_b^{2}K}_C)L_P^D,K_{(4,5,5)}={L_{Poff}^{3}L}_C^5{L_b^{3}K}_P{L}_P^D,\end{array}\\ K_{(8,7,6)}=0,K_{(8,7,7)}=0,K_{(5,0,0)}={L_{Poff}K}_C,K_{(5,0,4)}=0,K_{(5,0,3)}={L_{Poff}^{3}L}_C^4{L_b^{2}K}_{C\_2x1}{L}_P^D,\\ K_{(5,0,1)}={L_{poff}K}_{C1x2}{L}_P^D.\end{array}$$

and

$$\begin{array}{l}{L}_{(1,3)}=L_{Poff}^5{L}_C^5{L}_b^2,L_{(1,2)}=L_{Pon},L_{(4,2)}=L_{Poff}^5{L}_C^4{L}_b^2,\\ L_{(4,5)}={L_{Pon}L}_{Poff}^6{L}_C^3{L}_b^4,\\ L_{(8,7)}=L_{Poff}^2,L_{(5,0)}=L_{Poff}^4{L}_C^5{L}_b^4,L_{(0,2)}=L_{Poff}^3{L}_C^4{L}_{Pon}{L}_b^2,L_{(0,3)}=L_{Poff}^5{L}_C^3{L}_{Pon}{L}_b^3,\\ L_{(0,4)}=L_{Poff}^3{L}_C^2{L}_{Pon}{L}_b,L_{(0,1)}=L_{Pon},L_{(0,5)}=L_{Poff}^8{L}_C^5{L}_b^4,L_{(6,8)}=L_{Pon},\\ L_{(6,7)}=L_{Poff}^2{L}_C{L}_{Pon}{L}_b\end{array}$$

4. Quantitative Analysis of 3D Optical Networks-on-Chip

The operational efficiency and reliability of the proposed 3D ONoC architecture are evaluated through a rigorous quantitative analysis of key physical-layer metrics: insertion loss, crosstalk noise, and SNR. To determine the architecture’s scalability and performance limits, we calculate the worst-case insertion loss for the longest data transmission paths across various network dimensions and compare them. The reported results are physical-layer scaling for selected paths.

4.1. Insertion Loss Analysis

The 3D mesh structure, using the HDORAR for intra-layer switching and the VOR for inter-layer connectivity, was considered for insertion-loss analysis. Insertion loss is critical because it directly determines the minimum optical power required from the laser source to meet the photodetector’s sensitivity and maintain a target BER. As shown in Figure 6, the insertion loss increases with the topology size due to the increased number of waveguide crossings, bends, and MRRs along the transmission path.

Figure 6. Insertion loss for different topology sizes using the proposed HDORAR-based 3D ONoC (red) and the method reported in [27] (blue).

For a 3 × 3 × 3 ONoC, the proposed design achieves an insertion loss of 4.70 dB, whereas the architecture in [27] incurs a loss of 5.90 dB. For a larger 6 × 6 × 4 topology, the proposed architecture exhibits 8.96 dB of loss compared to 11.37 dB for the design in [27]. In a vertical expansion from a 3 × 3 × 3 to a 3 × 3 × 4 topology, the proposed design shows a negligible increase in loss (from 4.706 dB to 4.707 dB). In contrast, the conventional design increases from 5.905 dB to 6.215 dB. This demonstrates that the three-port VOR effectively mitigates the signal degradation in inter-layer communication.

At the network level, the results show that, for scalable solutions, 3D integration offers more advantages than 2D expansion. For example, a 6 × 6 × 3 topology (108 cores) generates an insertion loss of 8.966 dB, while a 5 × 5 × 4 topology (100 cores) results in only 7.547 dB. This shows that layer-based expansion is architecturally superior to adding processing elements horizontally, as it reduces hops and physical components in the primary signal path. Overall, the proposed architecture using HDORAR and VOR achieves an average insertion-loss reduction of 31.28% compared to traditional 3D ONoC designs.

4.2. Worst-Case SNR Analysis for 3D ONoC

We conducted the worst-case SNR analysis for the four identified longest transmission paths across different ONoC dimensions. Path 4 is a constructed first-order crosstalk stress case rather than a traffic-average worst case; the reported plots do not include higher-order leakage. Figure 7 illustrates that, for smaller network sizes, Path 1 has the lowest SNR because it is the physically longest link. As the ONoC topology scales, the SNR for all paths reduces as the number of active waveguide crossings and MRRs increases. Although Path 1 maintains the highest insertion loss across all paths, its SNR becomes relatively better than other paths in larger networks. This is because it is an outer-side path and experiences significantly lower cumulative crosstalk interference than inner-side paths like Path 4, which is subjected to noise from a higher density of surrounding active components. These results show that as 3D ONoC density increases, crosstalk noise, including higher-order noise, eventually becomes the primary bottleneck for communication reliability.

Figure 7. Worst-case SNR versus topology size for proposed 3D ONoC.

Figure 8 shows the output power obtained at the destination nodes for each selected path for different 3D ONoC dimensions. Path 1 exhibits the minimum output power because it incurs the highest cumulative insertion loss, whereas Path 4 has the highest output power among the four longest paths, reflecting low signal losses.

Figure 8. Output power vs. topology size for proposed 3D ONoC.

Figure 9 illustrates the SNR performance of the proposed 3D ONoC relative to output power and noise power for Path 4. For HDORAR- and VOR-based architectures, signal attenuation is reduced while maintaining lower crosstalk noise, ultimately resulting in a superior SNR across 3D data paths.

Figure 9. SNR vs. noise and output power in 3D ONoC.

Figure 10 shows the comparison of worst-case SNR for different sizes of 3D ONoCs. The worst-case SNR of the ONoC with HDORAR and VOR is compared with an ONoC designed based on the router presented in [3], which has the lowest insertion loss among routers reported in the literature. The performance of both ONoCs is nearly similar for a lesser number of cores. As the number of cores increases, the proposed ONoC outperforms the others, showing a 9.23% improvement in worst-case SNR.

Figure 10. Worst-case SNR versus number of cores for the proposed HDORAR-based 3D ONoC (red) compared with the method reported in [27] (blue).

The SNR for an ONoC of size 7 × 7 × 7 (343 cores) is 17.8235 dB, while for 5 × 5 × 15 (375 cores), it is 21.6161 dB. It shows that vertical expansion provides superior performance and compactness compared to horizontal scaling for high-density ONoCs. Figure 11 shows that the proposed architecture improves the SNR by 12.38% over traditional designs, highlighting the efficiency of the VOR in vertical connectivity while maintaining a more compact physical footprint. These values indicate a favorable vertical-scaling trend. The real stacked implementation may add technology-dependent TSPV/inter-layer losses.

Figure 11. SNR for vertical expansion of the proposed HDORAR-based 3D ONoC (red) compared with the method reported in [27] (blue).

A comparative BER analysis was conducted to evaluate the communication reliability of the proposed 3D ONoC against the benchmark architecture. For the selected topology, the proposed design achieves a BER of 3.58 × 10⁻¹⁰ for a 5 × 5 × 5 size, significantly outperforming the benchmark BER of 2.52 × 10⁻⁸.

We further investigated the impact of vertical scaling by increasing the core count along the Z-dimension. For the 5 × 5 × 25 configuration, the proposed ONoC maintains a superior BER of 4.26 × 10⁻¹⁰ while the design results in a BER of 9.15 × 10⁻⁹. These results demonstrate that the proposed architecture effectively meets high-fidelity communication requirements.

5. Conclusions

This work introduced a novel 3D ONoC architecture that effectively addresses the scalability and communication bottlenecks of modern MPSoCs by utilizing a bifurcated router design. Developing the six-port HDORAR for intra-layer switching and the three-port VOR for inter-layer connectivity provides a more compact, less complex alternative to unified router structures. We develop detailed mathematical models for various performance metrics. The results demonstrate significant performance gains, with the proposed design achieving a 31.28% reduction in average insertion loss and a 9.23% improvement in worst-case SNR. The study also shows that vertical expansion of ONoCs outperforms horizontal scaling, maintaining higher SNR and BER with a smaller physical footprint and enabling practical implementation of reliable, energy-efficient, high-performance interconnects for future all-optical computing environments.