Hardware-Aware Quantum Kernel Design Based on Graph Neural Networks

Abstract

Quantum kernels hold significant promise for achieving computational advantages in quantum machine learning (QML), yet their effectiveness critically depends on the design of expressive and hardware-compatible feature maps, a challenge that is particularly pronounced in Noisy Intermediate-Scale Quantum (NISQ) devices with limited qubits, gate errors, and restricted connectivity. In this work, we propose a hardware-aware methodology for automated quantum kernel design that integrates quantum device characteristics with learning-based evaluation. Specifically, candidate quantum circuits explored within the hardware-aware circuit space are represented as directed acyclic graphs (DAGs) encoding hardware-specific information such as gate operations, qubit interactions, and noise properties, while a dual graph neural network (GNN) predictor is employed to estimate key surrogate metrics, including probability of successful trials (PST) and kernel-target alignment (KTA), enabling efficient and accurate assessment of circuit fidelity and kernel performance to facilitate the identification of task-specific quantum kernels. Furthermore, feature selection is incorporated to reduce input dimensionality and ensure compatibility with near-term devices. Extensive experiments on multiple benchmark datasets, including Credit Card (CC), MNIST-5, and FMNIST-4, demonstrate that our method consistently outperforms existing baselines in classification accuracy, effectively balancing hardware constraints and model expressivity under realistic noise conditions. These results highlight the potential of combining hardware-aware design with deep learning techniques to advance practical quantum kernel methods under hardware-calibrated noisy simulation settings.

1. Introduction

Quantum computing presents a compelling prospect for revolutionizing machine learning tasks by exploiting the fundamental properties of quantum mechanics, such as superposition, entanglement, and high-dimensional Hilbert spaces [1,2]. Quantum Machine Learning (QML), as a prominent class of quantum algorithms, has demonstrated practical applicability in diverse real-world tasks, including classification [3,4,5,6,7], generative modeling [8,9,10,11], and learning physical systems [12,13], particularly in the Noisy Intermediate-Scale Quantum (NISQ) era [14]. Recent studies have further highlighted the rapid expansion of QML from both methodological and application-oriented perspectives, including emerging research paradigms, knowledge structure analyses, future prospects, and hybrid quantum–classical applications in areas such as mental health-aware sentiment analysis [15,16]. Among various QML approaches, quantum kernel methods have attracted increasing attention due to their solid theoretical foundation and interpretability [17,18,19]. By embedding classical data into quantum states through parameterized quantum circuits, quantum kernels induce implicit feature maps capable of capturing complex nonlinear relationships beyond classical means.

Despite recent demonstrations of quantum kernel learning on real quantum devices, achieving practical quantum advantage remains challenging, particularly under the constraints of NISQ devices [20,21,22]. Inappropriate quantum circuit designs can lead to vanishing kernel similarities, reduced expressivity, and degraded generalization [23,24], thereby limiting the overall performance of quantum kernels. These issues are further exacerbated in high-dimensional settings or when circuit depth and qubit counts exceed the noise tolerance of near-term hardware. To address these challenges, prior works have explored both circuit-aware and data-aware optimization strategies. Some approaches focus on tuning variational parameters within fixed-circuit architectures [25,26,27], while others formulate quantum kernel design as a joint optimization over circuit and parameters, typically addressed using evolutionary or machine learning-based approaches [28,29,30,31]. However, these methods not only fail to account for hardware-specific constraints, such as qubit connectivity and gate noise, but also incur prohibitive computational costs when exploring large circuit design spaces.

Motivated by these limitations, there remains a critical need for approaches that can efficiently identify high-quality and task-specific quantum kernel while explicitly incorporating hardware-specific constraints. To this end, we propose a hardware-aware quantum kernel design framework based on graph neural networks. Rather than formulating quantum kernel design as a joint optimization over circuit structures and parameters, our approach decouples the process by first generating hardware-aware candidate circuits and subsequently evaluating their performance using graph neural networks (GNNs). By exploiting the graph structure of quantum circuits, the GNNs predict two surrogate metrics: the probability of successful trials (PST), which captures circuit fidelity under hardware noise, and kernel-target alignment (KTA), which correlates with downstream classification accuracy.

The proposed framework comprises four stages: generation of hardware-aware candidate circuits based on device topology and native gate sets, filtering via PST prediction to eliminate low-fidelity circuits, ranking via KTA prediction to identify high-performing kernels, and subsequent parameter optimization of the top candidates. Furthermore, to further enhance scalability, we incorporate feature selection to reduce input dimensionality and ensure compatibility with NISQ devices. Crucially, by integrating hardware information and task-dependent performance estimation within a unified learning framework, the proposed framework enables efficient identification of quantum kernels that are both hardware-compatible and task-relevant. Extensive hardware-calibrated noisy simulations based on IBM device characteristics demonstrate that the proposed approach consistently outperforms state-of-the-art baselines across diverse classification tasks and simulated hardware configurations.

Our method offers several distinctive advantages that collectively enable efficient quantum kernel design for NISQ devices:

•

Hardware awareness: Our methodology explicitly incorporates hardware topology and noise characteristics during both circuit generation and performance prediction, enabling the identification of robust and high-quality quantum circuits under hardware-calibrated noisy simulation settings.

•

Dual-GNN-based performance prediction: By employing two graph neural networks (GNN-1 and GNN-2), the proposed method efficiently predicts PST and KTA as a proxy for classification performance, achieving speedups of over 380× and 58,000× compared to direct simulation.

•

Hardware-aware candidate filtering: By filtering out low-fidelity circuits early in the pipeline, our framework mitigates the impact of gate errors and decoherence, thereby improving the robustness and reliability of quantum kernel performance on noisy devices.

•

Efficient support for high-dimensional input: The integration of feature selection techniques (e.g., mRMR) reduces input dimensionality by retaining features with high relevance and low redundancy, thereby mitigating excessive circuit depth, alleviating kernel concentration, and improving compatibility with NISQ-scale hardware constraints.

•

Superior classification accuracy: Extensive evaluations on multiple benchmark tasks, including Credit Card (CC), MNIST-5, and FMNIST-4, as well as under hardware-calibrated noise models derived from IBM devices, demonstrate that the proposed methodology consistently outperforms existing state-of-the-art methods in the considered noisy simulation settings.

The remainder of this paper is organized as follows: Section 2 reviews the necessary background on quantum computing, kernel methods, graph neural networks, and related studies on quantum architecture search and automatic quantum kernel design. Section 3 presents the proposed framework. Section 4 reports the numerical results and comparative evaluations. Finally, Section 5 concludes this paper and outlines future research directions.

2. Background

2.1. Quantum Computing

A quantum bit (qubit) can exist in a linear superposition of the two computational basis states, $\left|0\right.⟩$ and $\left|1\right.⟩$, in contrast to a classical bit that can only be in a definite state of either 0 or 1. The state of a single qubit is generally represented as $\left|\psi \right.⟩=\alpha \left|0\right.⟩+\beta \left|1\right.⟩$, where $\alpha$ and $\beta$ are complex amplitudes satisfying the normalization condition ${\left|\alpha \right|}^2+{\left|\beta \right|}^2=1$. In multi-qubit systems, the overall quantum state resides in a tensor-product Hilbert space, allowing for entangled states that cannot be factorized into products of single-qubit states. Quantum gate, as a unitary matrix, transforms the quantum state to another and preserves the norm of the quantum state. Any unitary can be decomposed into a set of basis gates. The basis gate sets explored in this study are $S=\left\{R_x,R_z,CZ,I\right\}$ and $S^{*}=\left\{R_z,X,CNOT,I\right\}$, which consist primarily of single-qubit and two-qubit gates. More detailed matrix representations can be found in Appendix A.

2.2. Mechanism of Quantum Kernel

Kernel methods provide a powerful theoretical framework for performing nonlinear and nonparametric learning tasks, owing to their generality and strong interpretability [32,33,34]. Assume that both the training and test samples are drawn from the same input–output space $\mathcal{X}\times \mathcal{Y}$. The training dataset is denoted as $\mathcal{D}={\left\{{\mathit{x}}_i,y_i\right\}}_{i=1}^n\subset \mathcal{X}\times \mathcal{Y}$, where ${\mathit{x}}_i$ represents the input features of the i-th sample and $y_i$ denotes the corresponding label. The fundamental idea of traditional kernel methods is to map input data ${\mathit{x}}_i$ from ${\mathbb{R}}^d$ to a higher-dimensional feature space ${\mathbb{R}}^q$, i.e., $\varphi \left(·\right):{\mathbb{R}}^d\to {\mathbb{R}}^q$ with $q\gg d$, such that data that are not linearly separable in the original space may become linearly separable in the transformed space. However, when q is large, explicitly computing the mapped feature vectors $\varphi \left({\mathit{x}}_i\right)$ becomes computationally expensive. To address this, kernel methods employ the kernel trick, which enables implicit computation of inner products in the feature space through a kernel function $\kappa ({\mathit{x}}_i,{\mathit{x}}_j)$. This leads to the construction of a kernel matrix $K\in {\mathbb{R}}^{n\times n}$ with entries defined as follows:

$${\left[K\right]}_{i,j}=\kappa ({\mathit{x}}_i,{\mathit{x}}_j),\forall i,j\in \left[n\right],$$

(1)

where $\kappa ({\mathit{x}}_i,{\mathit{x}}_j)$ corresponds to the inner product $⟨\varphi \left({\mathit{x}}_i\right),\varphi \left({\mathit{x}}_j\right)⟩$ if an explicit feature map exists. Using the kernel matrix, the learning task reduces to finding a hypothesis function of the form $h\left({\mathit{x}}_i\right)=⟨{\mathit{w}}^{*},\varphi \left({\mathit{x}}_i\right)⟩$. The optimal parameter ${\mathit{w}}^{*}$ is obtained by minimizing the following loss function:

$$\mathcal{L}=\lambda ⟨\mathit{w},\mathit{w}⟩+{\displaystyle \sum _{i=1}^n}{\left(⟨\mathit{w},\varphi \left({\mathit{x}}_i\right)⟩\right)}^2$$

(2)

The performance of kernel methods critically depends on the choice of the feature map $\varphi (·)$, or equivalently, the kernel function $\kappa (·,·)$. A variety of kernels have been proposed for different applications, including radial basis function (RBF) kernels, Gaussian kernels, and quantum kernels.

Compared to classical kernel methods, the key distinction of quantum kernel approaches lies in the use of quantum feature maps that embed classical data into quantum states. For an N-qubit system, a data sample ${\mathit{x}}_i$ is encoded via a parameterized quantum circuit $U_c({\mathit{x}}_i,\mathit{\theta })$ acting on the initial state ${|0⟩}^{\otimes N}$, resulting in the quantum state $\left|\phi \left({\mathit{x}}_i,\mathit{\theta }\right)\right.⟩=U_c\left({\mathit{x}}_i,\mathit{\theta }\right){\left|0\right.⟩}^{\otimes N}$. This defines an implicit feature map into a high-dimensional Hilbert space. The corresponding density operator is given by $\rho ({\mathit{x}}_i,\mathit{\theta })=|\phi ({\mathit{x}}_i,\mathit{\theta })⟩⟨\phi ({\mathit{x}}_i,\mathit{\theta })|$. A commonly used quantum kernel is defined via the Hilbert–Schmidt inner product, leading to the kernel matrix:

$${\left[W\left(\mathit{x},\mathit{\theta }\right)\right]}_{i,j}=Tr\left(\rho \left({\mathit{x}}_i,\mathit{\theta }\right)\rho \left({\mathit{x}}_j,\mathit{\theta }\right)\right),\forall i,j\in \left[n\right]$$

(3)

which corresponds to the squared overlap between quantum states for pure-state encodings. Using this kernel matrix, learning proceeds analogously to classical kernel methods. The performance of a quantum kernel critically depends on the design of the encoding circuit $U_c(·,\mathit{\theta })$, which determines the induced feature space. In practice, $U_c$ can take various forms, including predefined ansatze, hardware-efficient circuits, or randomly generated circuits from a given gate set.

2.3. Graph Neural Networks

Graph neural networks have become a powerful framework for learning over graph-structured data, where relationships among entities play a critical role in the underlying data distribution [35]. By iteratively aggregating and transforming information from neighboring nodes through message-passing mechanisms, GNNs are capable of capturing both local topology and global structural dependencies [36]. This capacity to model complex relational patterns has led to their widespread adoption across a variety of domains, including social network analysis [37], molecular property prediction [38,39,40,41], and recommender systems [42,43]. Notably, variants such as Graph Convolutional Networks (GCNs), Graph Attention Networks (GATs), and GraphSAGE have significantly advanced the state of the art in graph representation learning tasks [44,45,46,47,48]. In the context of quantum computing, quantum circuits can be naturally represented as graphs, where qubits correspond to nodes and quantum gates or couplings define the edges. This structural analogy provides a compelling motivation for applying GNNs to quantum systems, enabling efficient learning and prediction tasks grounded in the intrinsic connectivity of quantum architectures.

2.4. Automated Design of Quantum Circuits and Kernels

The performance of quantum machine learning models is strongly affected by the design of quantum circuits. In the NISQ era, this issue becomes more pronounced because quantum circuits must be constructed under limited qubit resources, restricted hardware connectivity, and device noise. Manually designing effective circuits for different tasks is therefore difficult and usually requires considerable domain knowledge. To reduce the dependence on hand-crafted circuit structures, quantum architecture search (QAS) has been explored as an automated strategy for identifying suitable quantum circuits from a predefined search space [49,50,51,52,53,54,55,56].

Existing QAS methods have shown that automated circuit design can improve the performance of quantum learning models under near-term hardware constraints. For example, QuantumSupernet searches candidate quantum architectures within a large circuit space and aims to reduce the cost of evaluating different circuit structures [56]. QuantumNAS further considers noise-adaptive circuit design, where the searched circuit is optimized together with hardware-related factors such as qubit mapping and device noise [7]. Differentiable QAS formulates discrete architecture choices in a differentiable manner, enabling gradient-based circuit architecture optimization [50], while QuantumDARTS further introduces a differentiable search strategy based on Gumbel-Softmax to reduce repeated circuit sampling and evaluation [51]. Predictor-based QAS accelerates the search process by using learned surrogate models to estimate the performance of candidate circuits [52], and graph self-supervised QAS further improves representation learning for circuit structures when labeled circuits are limited [53]. In addition, hierarchical circuit representations have been investigated to connect neural architecture search concepts with quantum circuit design [54], and reinforcement learning-based QAS has been explored for selecting circuit architectures under hardware errors [55]. EliVagar focuses on efficient circuit search for QML classification tasks [6]. It uses low cost proxies, including Clifford noise resilience, to estimate circuit noise robustness and reject low-fidelity circuits at an early stage, thereby reducing the cost of candidate evaluation. These studies indicate that automatic circuit design is useful for improving QML models, especially when the circuit structure and hardware constraints jointly affect the final performance.

Automatic quantum kernel design is closely related to QAS, but its objective is different. In quantum kernel methods, the quantum circuit defines the feature map that embeds classical data into quantum states. The quality of the resulting kernel is determined not only by the expressivity of the circuit, but also by the induced kernel matrix and its relationship with the target labels. Therefore, directly applying circuit search strategies designed for trainable quantum models may not be sufficient for quantum kernel design. KTA provides a useful criterion for measuring the agreement between a kernel matrix and the label information [34,57]. Based on this idea, QuKerNet uses a neural predictor to estimate KTA and select promising quantum kernels more efficiently than exhaustive kernel evaluation [31].

Although these studies have advanced automated circuit and kernel design, several limitations remain. Most QAS methods mainly focus on trainable quantum circuits for QML classification or variational models, while quantum kernel design requires evaluating the task-dependent quality of the induced kernel matrix. Existing automatic quantum kernel design methods have considered KTA-based kernel evaluation, but hardware-related factors, including device topology, native gate constraints, gate errors, readout errors, and circuit fidelity, are not fully incorporated into a unified design framework. In addition, direct evaluation of a large number of candidate quantum kernels is computationally expensive because kernel construction requires repeated circuit evaluations over pairs of input samples.

3. Method

We now present the proposed framework, illustrated in Figure 1, which consists of four main steps:

Figure 1. Overview of the proposed framework for hardware-aware quantum kernel design.

• Step 1 Candidate Circuits Generation: A subset of qubits is first selected based on device topology and noise characteristics to ensure favorable connectivity and reduced noise impact. Based on this hardware-aware selection, a large set of candidate quantum circuits is generated under the native gate set and connectivity constraints of the target device.
• Step 2 PST Prediction: A graph neural network (GNN-1) is employed to predict PST, which serves as a proxy for circuit fidelity. This enables early rejection of low-fidelity candidates, effectively retaining circuits with higher fidelity potential.
• Step 3 KTA Prediction: A second graph neural network (GNN-2) is designed to estimate the KTA, a surrogate metric for classification accuracy, over the high-fidelity circuits identified in Step 2. The top-k circuits with the highest predicted KTA values are selected for further refinement.
• Step 4 Final Training and Kernel Selection: A classical optimizer is then employed to train the parameters of the top-k circuits, selected based on high KTA and PST values. The circuit achieving the best task-specific classification performance is chosen as the final quantum kernel.

For clarity, the four-step framework is grouped into three components: candidate circuit generation (Step 1, Section 3.1); GNN-based metric prediction (Steps 2–3, Section 3.2); and final training and kernel selection (Step 4, Section 3.3). Although the proposed pipeline contains several interacting components, each component is introduced to address a different bottleneck in hardware-aware quantum kernel design. The candidate circuit generation module defines a hardware-compatible search space by incorporating device topology, native gate constraints, and noise characteristics. The PST predictor is used as a fidelity-oriented filter to remove candidate circuits that are likely to be unreliable under the target noise model. The KTA predictor is then applied to the remaining circuits to estimate the task-dependent quality of the induced quantum kernel. Finally, the downstream training and evaluation stage selects the final kernel according to actual classification performance. Therefore, PST and KTA are not used as final optimization objectives, but as complementary screening criteria for reducing the cost of searching over a large candidate circuit space.

3.1. Candidate Circuit Generation

The generation of candidate quantum circuits consists of three stages. First, a subset of qubits is selected from the quantum device by jointly considering topological connectivity and noise characteristics of both qubits and their couplings, with the goal of identifying a low-noise subgraph that improves hardware efficiency and circuit fidelity. Second, candidate circuits are constructed on the selected qubits under the native gate set and connectivity constraints of the device, where each quantum gate is applied only to physically connected qubits, thereby implicitly satisfying qubit mapping and avoiding the insertion of SWAP gates during compilation, which reduces circuit depth and mitigates noise accumulation. Third, parameterized quantum gates are introduced at different positions within the circuits to enable flexible data embedding, enhancing the expressivity and performance of the resulting quantum kernels.

3.1.1. Subgraph Selection in Device Topology

Due to heterogeneous noise levels across qubits and their couplings in quantum devices, we select a subset of N qubits that are less susceptible to noise, thereby improving hardware efficiency and enhancing circuit fidelity. Figure 2 shows example subgraphs with $N=4,5,7,$ and 8 extracted from the 133-qubit IBM Torino topology.

Figure 2. Subgraphs with $N=4,5,7$ and 8 selected from the 133-qubit IBM Torino topology.

Selecting a subgraph with N qubits requires jointly considering multiple hardware-specific factors, including single-qubit gate errors, readout errors, two-qubit gate errors between coupled qubits, and qubit connectivity. The objective is to identify a subgraph with high gate fidelity and strong connectivity while maintaining low readout error. By incorporating device-specific noise information, this selection strategy ensures that the resulting quantum circuits are hardware-aware. Detailed procedures are provided in Appendix B.

3.1.2. Generating Candidate Circuits Based on the Subgraph

After selecting a high-fidelity subgraph G, we generate M candidate quantum circuits under the structural constraints of G and the native gate set S supported by the device, ensuring hardware-aware circuit construction. As illustrated in Step 1 of Figure 1, candidate circuits are generated from a subgraph of the IBM Torino using the gate set $S=\left\{R_x,R_z,CZ,I\right\}$. Detailed procedures are provided in Algorithm 1. During circuit generation, the placement of two-qubit gates between coupled qubits is guided by their gate errors. Specifically, the probability of inserting a two-qubit gate between qubits $q_i$ and $q_j$, denoted as $P(q_i,q_j)$, is defined as follows:

$$\begin{array}{c}P\left(q_i,q_j\mid e_j\right)={\displaystyle \frac{1/e_j}{{\sum }_{j}1/e_j}}\end{array}$$

(4)

where the two-qubit gate error $e_{ij}$ corresponds to the edge $q_i{q}_j$ in the subgraph G. Single-qubit gate errors are neglected, as two-qubit gate errors are typically an order of magnitude larger and thus dominate circuit performance. Since circuit construction is explicitly guided by noise information, the resulting circuits are inherently hardware-aware.

After generating the candidate circuits, a lightweight optimization step is applied to fuse consecutive parameterized gates whenever possible, reducing circuit redundancy. By iteratively applying the procedure in Algorithm 1 together with this optimization step, a large pool of hardware-aware candidate circuits can be efficiently generated, providing a strong foundation for subsequent GNN-based evaluation and optimal circuit selection.

Algorithm 1 Generate candidate circuit

Require: Device subgraph $G\left(\left\{V_i\right\},\left\{E_j\right\}\right)$; 2-qubit gate error $\left\{e_j\right\}$; The gate set S; The number of gates P. Ensure: Candidate circuit C.        for k in range(P) do            Sample a gate $g_k$ uniformly from the set S▹ Sample a gate to be added, e.g., $R_x$, $R_z$, or $CZ$.             if $g_k$ is a 1-qubit gate then                 Select a qubit $q_i\in \left\{V_i\right\}$ uniformly at random from the subgraph G    ▹ Select a qubit from the subgraph as the target qubit of the quantum gate.                   Append $g_k\left(q_i\right)$ to C             else if $g_k$ is a 2-qubit gate then                 Select a pair of qubits $q_i,q_j$ from subgraph G according to the probability distribution $P\left(q_i,q_j\mid e_j\right)$        ▹ 2-qubit gate placement is guided by the associated error $e_j$.                   Append $g_k\left(q_i{q}_j\right)$ to C             end if       end for       return C

3.1.3. Data Embedding in Circuits

Inspired by the advantages of randomized data embedding over fixed strategies [6], we adopt a simple yet effective embedding scheme, as illustrated in Figure 3. Specifically, in each quantum circuit, a subset of parameterized single-qubit gates is randomly selected for data encoding, with each selected gate corresponding to one input feature. To ensure full data coverage, the number of embedding gates is set to be no smaller than the input dimensionality. In addition, we prevent consecutive mergeable parameterized gates from encoding different data, thereby avoiding redundant operations after circuit simplification.

Figure 3. Illustration of randomized data embedding in parameterized quantum circuits.

For high-dimensional data, such as image classification tasks (e.g., MNIST with 784 features), direct embedding would require a large number of quantum gates, resulting in deep circuits with many qubits. This not only exceeds the capability of NISQ devices but also exacerbates the vanishing kernel similarity issue, leading to degraded performance. To address this, we incorporate a feature selection step in the preprocessing stage to reduce the input dimensionality. Specifically, the max-relevance and min-redundancy (mRMR) method is employed to project the data from d to p dimensions ($p\ll d$), thereby significantly reducing the number of required embedding gates. This strategy mitigates kernel concentration effects and enables more effective utilization of high-dimensional data on NISQ devices. It should be noted that mRMR is adopted here as a practical preprocessing strategy rather than as an optimal quantum-aware feature selection method. The retained feature dimension is chosen to balance information preservation and NISQ compatibility: retaining more features may preserve more classical information but requires more embedding gates and deeper circuits, whereas retaining fewer features reduces circuit cost but may discard useful information. Since mRMR selects features according to classical relevance and redundancy criteria, it does not guarantee that all features that could be useful for a specific quantum feature map are preserved. Therefore, the feature selection step may introduce information loss, and its influence should be interpreted as part of the trade-off between data representation and hardware feasibility.

3.2. Metrics Prediction Based on Graph Neural Networks

To predict the probability of successful trials (PST) under device noise and the corresponding performance metric, kernel-target alignment (KTA), we design two graph neural networks (GNNs), referred to as GNN-1 and GNN-2. Although GNN-1 and GNN-2 share the same graph representation of quantum circuits, they predict two fundamentally different metrics. GNN-1 estimates the PST, which reflects the hardware-dependent fidelity of candidate circuits under the target noise model. In contrast, GNN-2 predicts the KTA, which evaluates the task-dependent quality of the induced quantum kernel through its alignment with the target labels. Since these two prediction targets are governed by different objectives and information sources, we employ two independent GNN models rather than a shared multi-task architecture. This design allows each model to specialize in its corresponding prediction task while providing a clearer interpretation of the two complementary evaluation criteria. While the two models share a similar overall architecture, they differ in specific design choices due to their distinct prediction objectives. Below, we describe the GNN framework in detail, including dataset preparation, graph representation, node features, target definitions, and model architecture.

3.2.1. Construction of the Dataset

The primary motivation for constructing GNN-based predictors is to enable rapid evaluation of a large number of candidate circuits after training on a relatively small dataset. To this end, we adopt a random sampling strategy to construct the training set, where a subset of circuits is selected from the previously generated pool of candidates. To ensure consistency and completeness, all qubits are initialized in the $|0⟩$ state, and measurement operations are included in each circuit, as illustrated in the left panel of Figure 4. This formulation also facilitates the incorporation of device-specific noise characteristics, such as readout errors, into the node features.

Figure 4. Schematic of quantum circuit-to-graph transformation for GNN-based prediction.

3.2.2. Graph Construction

Motivated by the structural similarity between quantum circuits and graphs, we represent quantum circuits as directed acyclic graphs (DAGs). In this formulation, nodes correspond to qubits, quantum gates, or measurement operations, while edges encode the temporal ordering of operations from left to right. As illustrated in Figure 4, circuits generated on IBM Torino are transformed into graph representations, with each two-qubit gate modeled as a single node to preserve its joint operation. This transformation can also be implemented using existing toolkits, such as Qiskit and PyZX, with appropriate configuration.

3.2.3. Node Features

For each node in the graph, we construct a feature vector to encode its associated properties. The features include the node index, node type, target qubit, tag, relaxation time ($T_1$), and dephasing time ($T_2$) of the target qubit, as well as gate error and readout error. The specific feature configurations used for GNN-1 and GNN-2 are illustrated in Figure 5. The feature vectors for both GNN-1 and GNN-2 have a length of 31. It is worth noting that the length of the feature vectors can be manually configured based on either the maximum number of qubits in the circuits or specific requirements, ensuring that each circuit can be properly encoded. In the example shown in Figure 5, we set the maximum supported qubit number to 16, which results in a final feature vector length of 31. The first part of the feature vector encodes the index, which is used for node sorting. The next three parts are one-hot encodings representing the node type, target qubit, and tag, respectively. The node type distinguishes different types of nodes, including initial input qubit, measurement, $R_x$ gate, $R_z$ gate, $CZ$ gate, and identity (I) gate. For example, the one-hot code 000010 indicates that the node corresponds to a $CZ$ gate. The target qubit labels the index of the qubit affected by the operation, and its length can be expanded according to practical needs. The tag distinguishes whether a gate is used for data embedding, switching from 0 to 1 for embedding gates. In addition to capturing the topological connections between circuits, another advantage of GNNs is their ability to incorporate hardware noise information, which is primarily achieved through node feature vectors. In our method, the last seven elements of each node’s feature vector are dedicated to describing the noise characteristics of the quantum hardware. During model training, GNN-1 incorporates these noise features to predict the fidelity-related metric, allowing the model to implicitly learn how device noise affects circuit performance, and enabling early rejection of poor-performing circuits. In contrast, GNN-2 focuses on the predicting performance-related metric, with the last 7 elements of its feature vectors zero-filled to exclude noise information. The noise parameters are based on real quantum devices such as IBM Torino, IBM Perth, and IBM Nairobi. Specifically, the first 4 elements represent the relaxation time ($T_1$) and dephasing time ($T_2$) for the two involved qubits, the 5th element encodes the gate operation error, and the final two elements capture the readout errors. For nodes without associated noise characteristics, the corresponding values are set to zero. For instance, measurement nodes have their $T_1$, $T_2$, and gate error fields set to zero. Figure 5 shows the complete feature vector representation of a $CZ$ gate node for both GNN-1 and GNN-2.

Figure 5. Node feature vectors of GNN–1 and GNN–2 for $CZ$ gate.

3.2.4. Target Values

To evaluate the impact of noise on quantum circuits, we consider fidelity, a standard metric that quantifies the closeness between quantum states. In the presence of noise, fidelity measures the deviation between the state produced by a noisy circuit and its noiseless counterpart. A large deviation indicates that the circuit is significantly affected by noise and may yield unreliable outputs. However, estimating fidelity typically requires quantum state tomography, which is computationally expensive. To circumvent this limitation, we adopt the probability of successful trials (PST) [58] as a proxy metric, which has been shown to provide accurate estimates of circuit fidelity. The PST is defined as follows:

$$PST={\displaystyle \frac{T_{initial}}{T_{total}}}$$

(5)

where $T_{\mathrm{initial}}$ denotes the number of trials that return the initial state ${|0⟩}^{\otimes N}$, and $T_{\mathrm{total}}$ is the total number of trials. Rather than directly estimating fidelity, we append the inverse of each circuit to itself and apply the resulting circuit to the initial state ${|0⟩}^{\otimes N}$. The PST is then obtained as the fraction of measurement outcomes corresponding to the initial state, as illustrated in Figure 6. The resulting PST values are used as target labels for training GNN-1.

Figure 6. Schematic illustration of PST estimation via circuit inversion.

GNN-2 is designed to predict the kernel-target alignment (KTA), a metric that has been shown to correlate positively with training accuracy [31], and thus serves as a reliable surrogate for model performance. Before introducing KTA, we briefly review the concept of kernel alignment, originally proposed in [34], which measures the similarity between two kernel matrices, $K_1$ and $K_2$:

$$KA\left(K_1,K_2\right)={\displaystyle \frac{{⟨K_1,K_2⟩}_F}{\sqrt{{⟨K_1,K_1⟩}_F{⟨K_2,K_2⟩}_F}}}$$

(6)

where ${⟨K_1,K_2⟩}_F$ denotes the Frobenius inner product between two matrices, which is given by:

$${⟨K_1,K_2⟩}_F={\displaystyle \sum _{i=1}^l}{\displaystyle \sum _{j=1}^l}{\kappa }_1\left(x_i,x_j\right){\kappa }_2\left(x_i,x_j\right)$$

(7)

where l denotes the size of the kernel matrix, and $\kappa (x_i,x_j)={\left[K\right]}_{i,j}$ represents the $(i,j)$-th entry of the kernel matrix K. For classification tasks, an ideal target matrix is defined as $K^{*}=y{y}^T$, where $y={(y_1,y_2,\dots ,y_l)}^T$ denotes the label vector of the training set $\mathcal{D}$. The kernel-target alignment (KTA) is then defined as the alignment between the kernel matrix K (e.g., induced by the quantum kernel) and the target matrix $K^{*}$:

$$KTA\left(K\right)=KA\left(K,K^{*}\right)={\displaystyle \frac{{⟨K,y{y}^T⟩}_F}{\sqrt{{⟨K,K⟩}_F{⟨y{y}^T,y{y}^T⟩}_F}}}$$

(8)

Since ${⟨A,B⟩}_F=Tr\left(A^{T}B\right)$ and $K^T=K$, substituting them into Equation (8) yields the following formula:

$$KTA\left(K\right)={\displaystyle \frac{Tr\left(Ky{y}^T\right)}{\sqrt{Tr\left(K^2\right)Tr\left({\left(y{y}^T\right)}^2\right)}}}={\displaystyle \frac{y^{T}Ky}{l\sqrt{Tr\left(K^2\right)}}}$$

(9)

Here, l denotes the length of the label vector y. For multi-class classification tasks (including the binary case), the ideal target matrix $K^{*}$ can be constructed as follows [57]:

$${\left[K^{*}\right]}_{i,j}=\left\{\begin{array}{cc}1\hfill & y_i=y_j\hfill \\ {\displaystyle \frac{-1}{c-1}}\hfill & y_i\ne y_j\hfill \end{array}\right.$$

(10)

where c ($c\ge 2$) denotes the number of classes. KTA provides a task-dependent criterion for evaluating whether a kernel matrix is consistent with the label information. A larger KTA value usually indicates that the induced kernel matrix has a stronger alignment with the target labels on the given dataset. However, KTA should be regarded as a useful proxy rather than a rigorous guarantee of optimal downstream classification performance. The final classification accuracy may also be affected by hardware noise, parameter optimization, and the generalization behavior of the learned decision function. Therefore, in this work, KTA is used to rank and screen candidate quantum kernels instead of serving as a sufficient condition for optimal classification accuracy. Since constructing kernel matrices from quantum circuits remains computationally expensive, we employ GNN-2 to directly predict KTA and use the predicted values for efficient candidate evaluation.

3.2.5. Construction of GNNs

We adopt similar graph neural network (GNN) architectures for GNN-1 and GNN-2, as illustrated in Figure 7. Both models employ a four-layer message-passing structure, with each layer augmented by an attention mechanism to adaptively weight edges during propagation, thereby enhancing the representation of circuit characteristics. LeakyReLU is used as the activation function between layers.

Figure 7. Architecture of GNN-based predictors for quantum circuit evaluation.

After graph-based feature extraction, average pooling is applied over the representations of key nodes, excluding input and measurement nodes. The pooled features are then concatenated with the output of a three-layer fully connected network that processes global circuit features. The resulting representation is fed into a multilayer perceptron (MLP) to produce the final prediction.

While the overall architectures are shared, GNN-1 and GNN-2 differ in their global feature inputs. Specifically, GNN-1 uses $(g_1,k_1,z_1)$, where $g_1$ denotes the total number of gates, $k_1$ the number of two-qubit gates, and $z_1$ the circuit depth. In contrast, GNN-2 uses $(g_2,k_2,z_2)$, where $g_2$ denotes the total number of gates, $k_2$ the number of two-qubit gates, and $z_2$ the number of embedding gates. These task-specific global features align with the distinct prediction objectives of the two models, thereby improving predictive performance.

It should be noted that the proposed framework does not rely on a specific graph neural network. In this work, we adopt a graph attention network-based message passing architecture because the attention mechanism enables adaptive aggregation of neighboring node information with different importance, which is particularly suitable for heterogeneous quantum circuit graphs containing different gate types and hardware attributes. Other graph learning architectures, such as graph convolutional networks (GCNs), GraphSAGE, or graph transformers, may also be applicable. A systematic comparison among different graph, however, is beyond the scope of the present work and will be investigated in future studies.

3.3. Final Training and Kernel Selection

This step aims to identify the most effective quantum kernel for the target classification task. Based on the results of Steps 2–3, we select the top-k candidate circuits with high predicted PST and KTA values. These circuits are then trained on the target task, where the circuit structure is fixed and only the parameters are optimized from scratch using the Adam optimizer. After training, the classification performance of each circuit is evaluated on the test set, and the circuit achieving the highest accuracy is selected as the final quantum kernel.

It should be emphasized that PST and KTA are used as complementary surrogate criteria for candidate filtering and ranking, rather than as final guarantees of downstream classification performance. PST reflects the fidelity-related robustness of a circuit under hardware noise, while KTA measures the task-dependent alignment between the induced kernel matrix and the label information. These two metrics capture different aspects of a candidate quantum kernel. A circuit with high PST may still have limited discriminative capability if the induced kernel matrix is not well aligned with the target labels. Conversely, a circuit with high KTA may still suffer from hardware noise when implemented on a noisy quantum device. Therefore, the proposed framework does not assume that maximizing PST and KTA always leads to the optimal classifier across all datasets and quantum learning tasks. Instead, PST and KTA are used to reduce the candidate space and retain promising circuits for subsequent training and evaluation. The final quantum kernel is still selected according to the downstream classification performance after parameter optimization.

This design also clarifies the attribution of the final performance. The hardware-aware generation stage, PST-based filtering, KTA-based ranking, and final downstream selection are not interchangeable modules. Instead, they act at different stages of the pipeline and address different sources of difficulty, including hardware feasibility, noise robustness, task relevance, and final predictive performance. Consequently, the performance gains reported in the experiments should be understood as the result of the complete hardware-aware kernel design pipeline. We do not claim that any single component alone is sufficient to guarantee the observed improvement across all datasets and hardware backends.

4. Experiment

In this section, we present a comprehensive experimental evaluation of the proposed framework. This study is organized into two parts. The first evaluates the predictive performance and computational efficiency of the proposed graph neural networks, GNN-1 and GNN-2 (Section 4.1). The second assesses the overall performance of our methodology against recent state-of-the-art methods across multiple datasets (Section 4.2).

4.1. Predictive Performance of the Graph Neural Networks

Model and Training Setups: In the default setup, both GNN-1 and GNN-2 adopt a four-layer graph neural network architecture with attention mechanisms integrated into each layer, following the design of graph attention networks. This enables adaptive weighting of neighboring nodes during message passing. At the final layer, average pooling is applied over key nodes (excluding input and measurement nodes) to obtain a 31-dimensional representation. This representation is concatenated with a global feature vector produced by a three-layer fully connected network, where each hidden layer has 12 units.

The concatenated vector is then passed through a multilayer perceptron (MLP) with hidden layer sizes of 256, 128, and 64 to generate the final prediction. LeakyReLU with $\alpha =0.02$ is used as the activation function throughout the network. Training is performed using the Adam optimizer with a learning rate of 0.01, a batch size of 512, and the mean squared error (MSE) as the loss function for 200 epochs. During preprocessing, node features are normalized using Min–Max scaling across the dataset. The predictive performance is evaluated using the coefficient of determination ($R^2$), defined as follows:

$$R^2=1-{\displaystyle \frac{{\sum }_{i=1}^N{\left(y_i-{\widehat{y}}_i\right)}^2}{{\sum }_{k=1}^N{\left(y_i-\overline{y}\right)}^2}}$$

(11)

where ${\widehat{y}}_i$ denotes the predicted value for the i-th sample, $y_i$ is the corresponding ground-truth value, $\overline{y}$ is the mean of the ground-truth values, and N is the number of samples in the test set.

The hyperparameters of both GNN models, including the number of graph neural network layers, hidden dimensions, learning rate, batch size, and training epochs, are selected empirically according to the prediction performance on a validation subset of the training data. After this tuning process, the same hyperparameter configuration was fixed for all datasets and hardware settings throughout the experiments to ensure consistency and fair comparison.

Dataset Setup: Following the methodology described in Section 3.1, we generate 50,000 candidate circuits, from which 5000 are randomly sampled to construct the dataset for training GNN–1 and GNN–2. Among these, 4000 circuits are used for training and the remaining 1000 for testing. Although surrogate metrics (PST and KTA) are employed to reduce the cost of label generation, their large-scale computation remains time-consuming, a trade-off that will be further examined in the subsequent runtime analysis.

The main computational bottleneck in constructing the GNN training dataset lies in label generation rather than in GNN inference. For PST labels, each candidate circuit must be concatenated with its inverse circuit and evaluated under the corresponding hardware-calibrated noise model. The cost therefore increases with the number of candidate circuits, the circuit depth, the number of shots, and the complexity of noisy simulation. For KTA labels, the cost is even higher because constructing a kernel matrix requires repeated evaluations over pairs of input samples. If the training subset used for kernel evaluation contains n samples, each candidate quantum kernel requires $O\left(n^2\right)$ circuit evaluations before the KTA value can be computed. This explains why direct KTA evaluation is substantially more expensive than PST estimation. In the proposed framework, these expensive labels are generated only for a sampled subset of candidate circuits to train the surrogate models. Once trained, the GNN predictors can be reused to rapidly evaluate a much larger pool of candidate circuits.

For GNN-1, the noise models used during training are derived from real quantum hardware, including several 7-qubit devices (IBM Perth, IBM Lagos, IBM Nairobi, and IBM Jakarta), as well as the 133-qubit IBM Torino. The considered noise sources include gate errors, relaxation time ($T_1$), dephasing time ($T_2$), and readout errors. In addition, all 7-qubit devices share the same native gate set $S^{*}=\left\{R_z,X,\mathrm{CNOT},I\right\}$.

To evaluate the predictive performance of GNN-1 and GNN-2 for PST and KTA prediction, respectively, we conduct simulations across different system sizes with $N=4,5,7,$ and 8 qubits. Although these scales are relatively small, they are sufficient to demonstrate the effectiveness of the proposed approach under NISQ-relevant conditions. Extending the framework to larger quantum systems will be the subject of future work, potentially leveraging tensor-network-based simulations [59] and direct evaluations on real quantum hardware.

As shown in Figure 8, simulations are carried out on corresponding quantum devices: IBM Perth for $N=4$, and IBM Torino for $N=5,7,$ and 8. For visualization purposes, 100 samples are randomly selected from the test set in each case, while the coefficient of determination ($R^2$) is computed over the full test set.

Figure 8. Scatter plots of predicted PST and KTA values with $N=4,5,7$ and 8.

The results in Figure 8 demonstrate that both GNN-1 and GNN-2 achieve high prediction accuracy, with $R^2$ exceeding 0.97 for PST and 0.95 for KTA. The high accuracy of GNN-1 in predicting PST under hardware noise is attributed to the inclusion of noise information in the node feature vectors, which enhances the model’s ability to learn noise-informed representations. Moreover, we observe that KTA values are tightly clustered, while PST values exhibit a broader distribution. This implies that quantum kernels with similar KTA values, i.e., theoretically similar classification performance, can exhibit significantly different results on real hardware due to noise. This observation further justifies our strategy of early rejection of low-fidelity candidate circuits based on PST prediction.

To further demonstrate the efficiency of our approach, we evaluate the computational speedup achieved by GNN-1 and GNN-2 in circuit performance estimation. Specifically, we compare the inference time for 100 GNN-1 predictions of PST with the time required for direct PST computation, and similarly compare the inference time for 100 GNN-2 predictions of KTA with that of direct KTA evaluation. As shown in Figure 9 and summarized in Table 1, the results clearly highlight the substantial efficiency gains of the proposed approach. Note that the y-axis in Figure 9 is presented on a logarithmic scale.

Figure 9. Comparison of runtime of prediction and direct calculation for PST and KTA.

Table 1. Runtime of Prediction and Direct Calculation for PST and KTA.

Metric	Prediction ($·\mathit{s}$)	Calculation ($·\mathit{s}$)	Speedup
PST	$0.0012\pm 0.0000$	$0.4572\pm 0.0845$	$\mathbf{381}\times$
KTA	$0.0012\pm 0.0000$	$70.0540\pm 22.2887$	$\mathbf{58},\mathbf{378}\times$

Compared to direct computation, GNN-1 and GNN-2 achieve speedups of $381\times$ and $58,378\times$ for PST and KTA prediction, respectively. This comparison reflects the inference cost of the trained GNNs relative to the expense of explicit computation. Rather than a direct algorithmic acceleration, the improvement arises from replacing costly evaluations with learned surrogate models, enabling rapid performance estimation once training is completed.

Such a paradigm is particularly advantageous when direct computation becomes prohibitively expensive, allowing for efficient evaluation of a large number of candidate circuits and making large-scale quantum kernel screening feasible. The computational cost of the GNN models is mainly associated with offline training. For a fixed training dataset, the training cost scales with the number of circuit graphs, the number of graph nodes and edges determined by the circuit size and depth, the hidden dimension of the GNN layers, and the number of training epochs. In contrast, after training is completed, inference only requires a forward pass on each candidate circuit graph and is therefore much cheaper than explicit PST or KTA computation. This distinction is important for scalability; the proposed method does not remove the initial cost of generating representative labeled circuits, but amortizes this cost over the subsequent screening of a much larger candidate pool. Therefore, the framework is most beneficial in scenarios where many candidate circuits need to be evaluated for the same or similar hardware configuration and circuit generation rule. In addition to computational efficiency, we further examine the scalability of GNN-1 and GNN-2 with respect to the number of qubits, with detailed results provided in Appendix C.

While the above results demonstrate substantial computational speedup, the efficiency gain should be interpreted together with the prediction accuracy of the surrogate models. The GNN predictors are useful only when the approximation errors remain sufficiently small for reliable candidate screening. As shown in Figure 8, both GNN-1 and GNN-2 achieve high prediction accuracy on test circuits, with $R^2$ exceeding 0.97 for PST and 0.95 for KTA. Therefore, the large runtime reduction reported in Table 1 does not come at the cost of a severe loss of predictive reliability within the considered circuit search space.

It should also be noted that the proposed GNN predictors are used for filtering and ranking candidate circuits, rather than as the final evaluator of quantum kernel performance. After GNN-based prediction, the top-k candidate circuits with high predicted PST and KTA values are further trained and evaluated in the downstream classification task. This design mitigates the influence of occasional prediction errors, since the final quantum kernel is selected based on downstream performance rather than solely on a single predicted score.

4.2. Performance of Our Framework on Benchmarks

Model and Training Setups: After evaluating candidate circuits using GNN-1 and GNN-2, we select the top-k circuits with high KTA and PST values. In our experiments, $k=10$, corresponding to the top 10 high-performing quantum kernels. These circuits are then fine-tuned by optimizing their parameters from scratch. The training objective is to maximize classification accuracy using support vector machines (SVMs) constructed from the corresponding quantum kernels. Parameter optimization is performed using the Adam optimizer with a learning rate of 0.01.

We further evaluate the proposed method across multiple noisy simulators incorporating hardware-calibrated noise models derived from IBM Perth, IBM Lagos, IBM Nairobi, IBM Jakarta, and IBM Torino. Performance is compared against seven representative baselines. Each method is evaluated over 10 independent runs, and the results are reported as mean values with error bars indicating the standard deviation (SD).

Random Quantum Kernel: A total of 25 quantum kernels are randomly sampled from the gate set, with their circuit depths matched to those generated by the proposed method. Each kernel is trained independently, and the one achieving the highest classification accuracy is selected as the representative quantum kernel for each simulation run.

Training Embedding Kernels (TEK) [25]: This baseline adopts a fixed-circuit structure with parameter optimization. In our setup, each TEK kernel is composed of six blocks, including encoding blocks and training blocks. Each block consists of two layers of single-qubit gates followed by a layer of two-qubit gates arranged in a ring topology. Specifically, on 7-qubit devices, the single-qubit layers comprise an X layer (applying X gates to all qubits) followed by an $R_z$ layer, whereas on the IBM Torino device, an $R_x$ layer is used instead of the X layer, followed by an $R_z$ layer.

In the encoding blocks, dimension-reduced and normalized input features are embedded into the circuit by assigning them to the phases of parameterized gates after scaling by $\pi$. Once all features have been encoded, any remaining parameterized gates continue the embedding process by reusing the feature vector in a cyclic manner. The parameters in the training blocks are subsequently optimized to further refine the behavior and performance of the resulting quantum kernel.

Radial Basis Function Kernel (RBFK) [60,61]: A widely used classical kernel with the kernel matrix defined as ${\left[K\right]}_{i,j}=exp\left(-\gamma {∥x_i-x_j∥}^2\right)$, where $\gamma$ is a hyperparameter. In the simulations, $\gamma$ is set to the reciprocal of the input feature vector dimension, which serves as a reasonable heuristic to balance the sensitivity of the kernel.

QuantumSupernet [56]: Most hyperparameters follow the settings in [56], with one modification: we replace full-batch gradient descent with mini-batch gradient descent (batch size = 32) to ensure efficient and thorough parameter updates during SuperCircuit training. During the construction of the SuperCircuit, we prohibit the occurrence of consecutive quantum gates that can be merged or canceled, such as repeated 1-qubit gates of the same type applied consecutively.

QuantumNAS [7]: We adopt the same hyperparameter settings as in [7] for both SuperCircuit training and evolutionary search. The gate set is adapted to match the constraints of each target quantum device.

EliVagar [6]: This method also incorporates early rejection of low-fidelity circuits. We follow the hyperparameter settings provided in [6] and adapt the gate set to match the supported operations of the target quantum devices.

QuKerNet [31]: This baseline is a recent neural predictor-based approach for quantum kernel design. In our experiments, we follow the hyperparameter settings reported in [31] and simulate the circuits using noise models derived from real quantum hardware. The method employs a multilayer perceptron (MLP) to predict the kernel-target alignment (KTA) of quantum circuits represented in matrix form.

Data encoding follows a sequential scheme, where an initial subset of parameterized gates is used to embed the input features, while the remaining parameters are optimized during training. Similar to our approach, a top-k selection strategy is adopted, with the same value of k used for fair comparison.

To ensure a fair comparison, all quantum baselines are evaluated under the same data preprocessing, qubit-number setting, hardware constraints, and noise assumptions as the proposed method. Specifically, for each benchmark task, the same train/test split, feature selection procedure, and feature normalization are used for all methods. The quantum baselines are configured to use the same number of qubits as the proposed method, and their gate sets are adapted to the native or supported operations of the corresponding target backend whenever applicable. All quantum methods are evaluated using the same hardware-calibrated noisy simulator derived from the target IBM device characteristics. When the logical circuits generated by a baseline are incompatible with the target hardware connectivity, Qiskit’s default mapping and routing strategies are applied for compilation. Specifically, logical qubits are mapped to physical qubits in a sequential manner, and SWAP gates are heuristically inserted to satisfy hardware connectivity constraints. The classical RBF kernel baseline does not involve quantum circuits, gate sets, or hardware noise models; therefore, these hardware-related constraints are not applicable to RBFK. Nevertheless, RBFK is evaluated using the same train/test split and the same dimension-reduced input features as the quantum methods.

Dataset Setup: We evaluate the proposed method on three quantum machine learning (QML) benchmark tasks: Credit Card (CC) fraud detection (binary classification), MNIST-5 (five-class classification over digits 0–4), and FMNIST-4 (four-class classification over T-shirt, Trouser, Bag, and Ankle Boot).

For MNIST-5 and FMNIST-4, balanced datasets are constructed by selecting 2000 training samples and 400 test samples from each dataset. The original 784-dimensional images are reduced to 40 dimensions using the minimum Redundancy Maximum Relevance (mRMR) algorithm [31].

For the CC task, 1000 samples are drawn while ensuring that at least 5% correspond to fraudulent transactions. The dataset is randomly split into training and test sets with a 70/30 ratio. The original 28-dimensional features are reduced to 14 dimensions using mRMR.

The same mRMR-selected features and the same normalized input data are used for the proposed method and all baseline methods so that the comparison is not affected by different feature selection settings. The choice of 14 retained features for the CC task is made to keep the number of embedding gates and the resulting circuit depth compatible with the considered NISQ-scale circuits. We acknowledge that classification performance may depend on the retained feature dimension. Increasing the number of retained features may preserve more information but would also increase the circuit depth and noise accumulation, whereas using fewer features may reduce circuit cost at the expense of losing task-relevant information. A systematic sensitivity analysis over different retained feature dimensions is therefore an important direction for future work.

The three benchmark datasets are selected to cover different data modalities and classification settings under NISQ-compatible experimental conditions. The CC task represents tabular binary classification with class imbalance, while MNIST-5 and FMNIST-4 represent multi-class image classification tasks with different visual patterns and feature distributions. These datasets therefore provide representative test cases for evaluating whether the proposed hardware-aware quantum kernel design framework can work across both tabular and image-based QML benchmarks. Nevertheless, we acknowledge that these datasets do not cover all possible quantum learning scenarios. Therefore, the experimental results should be interpreted as evidence of effectiveness on representative benchmark tasks, rather than as a complete demonstration of broad generalizability across arbitrary datasets and quantum learning tasks.

To validate the performance advantage of the quantum kernels discovered by our framework, we conduct experiments on multiple benchmark tasks under different hardware configurations.

For the 4-qubit Credit Card (CC) task, experiments are performed on two IBM quantum devices with different scales: a 7-qubit device (IBM Perth) and a 133-qubit device (IBM Torino), where only a 4-qubit subset is used in each case. As shown in Figure 10, the proposed methodology achieves the highest classification accuracy among all compared methods, with more pronounced improvements on the larger IBM Torino device. The more pronounced improvement observed under the IBM Torino-derived noise model reflects the combined operation of hardware-aware subgraph selection and circuit generation, PST- and KTA-based candidate screening, and downstream parameter optimization.

Figure 10. Classification accuracy of different methods on the Credit Card (CC) task under noisy simulation.

We further evaluate the 7-qubit MNIST-5 task using five hardware-calibrated noisy simulators derived from IBM Perth, IBM Lagos, IBM Nairobi, IBM Jakarta, and IBM Torino, where a 7-qubit subset is used for each simulated backend. As shown in Figure 11, our method consistently outperforms all baselines in terms of classification accuracy, while also exhibiting improved stability as indicated by smaller error bars. On 7-qubit devices, the limited hardware scale constrains the effectiveness of hardware-aware qubit selection due to the prevalence of noisy qubits. Nevertheless, the complete framework maintains strong performance across these simulated backends. Under the IBM Torino-derived noise model, the performance advantage becomes more pronounced, suggesting that the integrated pipeline can more effectively utilize the heterogeneous topology and noise profile represented in the simulated backend.

Figure 11. Classification accuracy of different methods on the MNIST-5 classification task under noisy simulation.

For the FMNIST-4 task, which requires 8 qubits, experiments are conducted on IBM Torino. As shown in Figure 12, the proposed scheme continues to achieve significantly higher classification accuracy compared to competing methods, further demonstrating its effectiveness in larger and more complex settings.

Figure 12. Classification accuracy of different methods on the FMNIST-4 classification task under noisy simulation.

5. Conclusions

In this work, we proposed a hardware-aware framework for quantum kernel design that leverages graph neural networks to evaluate and select task-specific quantum circuits under the constraints of NISQ hardware. By incorporating real device topology, noise characteristics, feature selection, and GNN-based surrogate evaluation into a unified workflow, the proposed approach provides an efficient strategy for constructing quantum kernels within the considered NISQ-scale settings. The dual graph neural network models enable fast prediction of circuit fidelity and kernel-related performance metrics, thereby reducing the cost of candidate circuit screening. The experimental results on representative classification benchmarks suggest that the integrated hardware-aware workflow can improve quantum kernel performance under hardware-calibrated noisy simulation settings. Accordingly, the observed improvements should be interpreted as the outcome of the integrated framework, rather than as evidence of the independent contribution of any individual component.

These results further indicate that combining learning-based strategies with hardware-aware design can help narrow the gap between theoretical quantum kernel models and hardware-constrained implementations. Nevertheless, hardware-calibrated noise models remain an approximation of real device behavior. Although they provide a more realistic evaluation setting than ideal noiseless simulations, they cannot fully capture all effects present on physical quantum processors, including calibration drift, crosstalk, shot-to-shot fluctuations, and backend queue-time variations. Therefore, practical deployment on real noisy quantum devices still requires further validation through direct hardware experiments when sufficient device access and stability are available.

The proposed framework also has several limitations. First, its scalability is limited by the cost of generating reliable PST and KTA labels for representative candidate circuits. Although GNN inference is efficient after training, label generation and model recalibration may be required when moving to substantially larger circuit sizes, deeper search spaces, or different quantum hardware. Second, the current feature selection stage relies on mRMR, which is a classical relevance-redundancy criterion rather than a quantum-aware feature selection strategy. While this step helps reduce circuit depth and improve compatibility with NISQ-scale devices, it may discard features that are useful for certain quantum feature maps.

Future work will therefore focus on reducing the cost of label generation, improving transferability across circuit sizes and hardware platforms, and evaluating the framework under more diverse hardware-constrained settings. In particular, the scalability results in Appendix C indicate that prediction accuracy may degrade when models trained on smaller circuits are directly applied to larger qubit regimes. This suggests that future large-scale applications will require representative labeled circuits from the target regime, together with retraining, fine-tuning, or transfer-learning strategies to maintain reliable surrogate prediction. Moreover, we will explore the generalization of learned quantum kernels across broader datasets, different feature distributions, and more diverse quantum learning tasks. Extending the framework to quantum systems beyond the reach of classical simulation remains an important long-term direction, but such deployment will require direct validation on real quantum hardware and careful consideration of device access, calibration stability, and time-dependent noise effects.