Search Results (359)

To prevent the collapse of strip waveguides caused by complete undercut during hydrofluoric acid (HF) release in SOI-based cavity optomechanical accelerometers, we propose using rib waveguides as the on-chip optical transmission medium. Based on a 250-nm-thick SOI wafer, we systematically analyze the photonic crystal (PhC) microcavity, rib waveguide transmission, edge coupling, mode conversion to the PhC waveguide, and evanescent coupling. The PhC microcavity has a quality factor of 2.26 × 10⁵ at 1549.15 nm. The optimized rib waveguide (rib width 500 nm, rib height 220 nm) shows a transmission loss of 0.16 dB over 5000 μm. The rib-to-PhC waveguide coupling efficiency is 94.3% (0.25 dB loss), and a 90-μm-long tapered edge coupler achieves 65% efficiency (1.9 dB loss). The total optical path loss (including two edge couplers, rib waveguide transmission, and rib-to-PhC taper) is 4.21 dB. While maintaining optical performance comparable to strip waveguides, the rib waveguide design significantly improves post-release structural integrity at the design level. This work provides a viable optical circuit design foundation for reliable monolithically integrated cavity optomechanical accelerometers, with device fabrication and full system-level characterization planned as future work. Full article

An integrated spray-coated bi-layer lift-off process using the same positive photoresist is investigated for thick Ti patterning on structured MEMS wafers. Compared with conventional spin coating, spray coating provides more conformal photoresist coverage on wafers with 30–50 µm surface topography and reduces the local top–bottom thickness variation from approximately 30% to below 5%. By combining spray coating, heated-chuck drying, and flood exposure of the first resist layer, the integrated process improves thickness retention of the bi-layer resist and enables controlled lateral dissolution during development. After optimizing the development time, a lateral undercut of approximately 3.5 µm was obtained, which is consistent with the expected “T-shaped” resist profile. Representative 600 nm thick Ti patterns were fabricated on structured silicon wafers using this process. The results indicate that the proposed process is a feasible route for local thick-metal patterning on structured MEMS substrates under the present experimental conditions. Full article

Silicon carbide (SiC) is a key material for next-generation miniaturized devices and MEMS operating in harsh environments. This paper presents a comprehensive investigation of anisotropic damping mechanisms in heteroepitaxial 3C-SiC double-clamped beam resonators for MEMS applications. Unlike conventional isotropic loss-factor models, which assign a single scalar damping coefficient to all deformation directions, the proposed framework employs a full 6 × 6 loss-factor tensor expressed in Voigt notation, implemented within the COMSOL Multiphysics finite element environment. The tensor formulation enables the direction-dependent description of energy dissipation, capturing the coupling between shear and normal strain modes that arises from the (111) crystallographic orientation and from the heteroepitaxial defect structure of 3C-SiC grown on silicon substrates. The effects of film thickness, effective Young’s modulus, and residual stress on elastic modulus, resonance frequency, and Q-factor are systematically analyzed across five wafers (w1–w5, thickness range 293–890 nm). Experimentally calibrated anisotropic loss-factor matrices are extracted via least-squares fitting to measured Q-factors, and their Frobenius norms are found to correlate negatively with resonance frequency. The anisotropic model reduces Q-factor prediction errors to below 1% for all wafers, significantly outperforming the isotropic approach, particularly for films thicker than 600 nm. These results demonstrate that an accurate treatment of directional dissipation is essential for the design of high-Q resonators and high-sensitivity strain sensors targeted at geophysical monitoring applications. Full article

Corrosion of carbon steel components represents a major economic and safety challenge in industrial applications, motivating the development of protective thin film coatings with optimized deposition parameters. This study investigates the deposition of nickel nitride (Ni-N) thin films on AISI 1016 carbon steel and silicon (111) wafers by reactive radio-frequency (r.f.) magnetron sputtering at three power levels: 150, 175, and 200 W. Surface color, film thickness, roughness, crystal structure, mechanical properties, and electrochemical behavior were evaluated using optical microscopy, stylus profilometry, atomic force microscopy (AFM), X-ray diffraction (XRD), nanoindentation, and potentiodynamic polarization combined with electrochemical impedance spectroscopy (EIS). Increasing r.f.-power produced systematic surface color changes consistent with variations in film thickness, which ranged from approximately 25.0 to 50.7 nm. Higher deposition power promoted smoother surfaces, with average roughness (Ra) decreasing from 64.28 nm at 150 W to 20.62 nm at 200 W. XRD analysis revealed a monocrystalline Ni₃N hexagonal close-packed (HCP) phase at 150 W, transitioning to a dual-phase Ni₃N (HCP) and Ni₄N face-centered cubic (FCC) microstructure at 175 and 200 W. The highest hardness (11.80 ± 3.34 GPa) was recorded at 150 W, accompanied by pop-in events attributed to dislocation nucleation in the HCP lattice. Electrochemical evaluation in 3.5 wt.% NaCl solution demonstrated that films deposited at 150 and 175 W exhibited corrosion current densities and rates exceeding those of bare steel, confirming that these conditions accelerate rather than inhibit corrosion. Only the film deposited at 200 W achieved superior corrosion protection, with a corrosion current density and rate approximately 50% lower than bare steel, attributed to its denser microstructure and smoother surface morphology. These findings demonstrate that r.f. power is a critical parameter governing the properties of Ni-N thin films, and that careful optimization of deposition conditions is essential before recommending such coatings for industrial corrosion-protective applications. Full article

Piezoelectric pressure sensors for dynamic monitoring face a trade-off between charge output and measurement range, and existing high-sensitivity designs are largely confined to narrow ranges. This study presents a composite layered piezoelectric pressure sensor in which a 316L stainless-steel diaphragm drives a centrally suspended PZT-5H wafer supported by a perforated alumina gasket, with the wafer thickness and cavity radius optimized under a 10 MPa full-scale stress constraint. Over 0–10 MPa, quasi-static calibration gave a highly repeatable quadratic pressure–charge relationship ($R^2=0.99995$) with a maximum residual below 1% FS. The sensitivity is pressure-dependent: the secant sensitivity increased monotonically from 3.16 pC/kPa at 1 MPa to 5.36 pC/kPa at 10 MPa, reflecting a stress-stiffening response rather than a measurement tolerance band. The output deviation remained within 3% from 25 °C to 150 °C. Shock-tube testing yielded a resonance of ∼50 kHz and a mutually consistent 10–90% leading-edge interval of 10.12 $\mathsf{\mu }$s. Combining high charge sensitivity over a wide 0–10 MPa range with a fast transient response and stable operation up to 150 °C, the proposed sensor is suited to dynamic pressure-pulsation monitoring in fluid-power and thermal and power-plant fluid systems. Full article

Quartz is widely employed in optoelectronic and sensing applications owing to its excellent mechanical and chemical properties. However, its intrinsic transparency up to 5 μm limits its direct use as a photodetection substrate across the near- and mid-infrared spectral regions. Laser surface texturing for the fabrication of the so-called black quartz represents a promising strategy to overcome this limitation. In this work, different femtosecond (fs) laser texturing strategies were investigated on a 1 mm thick α-quartz wafer, namely uniform milling, grid-patterned grooves, and localized arrays of ablated craters. The fs-laser-treated quartz samples showed a transmittance reduction of up to 60% within the quartz transparency window in the infrared range, with crater matrices providing the most effective blackening performance. The enhanced absorption was attributed to light-trapping effects induced by the tapered crater geometry, which promotes multiple internal reflections and increased optical confinement within the substrate. The proposed strategy demonstrates a reliable, maskless, and chemical-free surface functionalization strategy for the fabrication of quartz-based substrates for broadband infrared photodetection in sensing applications. Full article

A two-step growth process was developed to fabricate a 3-inch homogeneously {100}-textured free-standing diamond wafer by microwave plasma enhanced chemical vapor deposition (MPCVD). The sequential growth process is based on a change in the growth parameter α, which is given by the growth rates on {100} and {111} facets, α = $\sqrt{3}$·(V₁₀₀/V₁₁₁). Initial growth was executed with nitrogen addition, yielding an α value close to 3 for evolutionary selection of the (100) face, followed by cessation of nitrogen addition to yield a lower α value. A homogeneously grown {100}-textured diamond over an area of ca. 175 cm² with a thickness ≥ 0.8 mm was obtained after 196 h growth. The diamond growth rate was 4.0–5.5 µm/h, which is four times higher than the conventional growth of oriented diamond. This was substantiated by optical microscopy, Raman spectroscopy, and XRD analysis. The large crystal size of 210 ± 60 µm has been assigned to the second growth step, where growth is preferentially in the <111> direction. The homogeneous {100} texture and the large crystal size are conducive to achieving high thermal conductivity, as the in-plane thermal conductivity of the polycrystalline diamond wafer was increased from ca. 850 W/(mK) to 1125 W/(mK). Full article

To address the critical challenges of edge chipping and poor processing quality in sapphire precision dicing, this paper proposes a femtosecond laser filamentation-guided dicing technology. By systematically investigating the influence of pulse overlap rate, energy, and scan counts on damage evolution, the physical differences between 343 nm UV and 515 nm visible lasers in suppressing plasma shielding and breaking through processing saturation limits are revealed. The results indicate that an extremely high pulse overlap rate (>98%) significantly inhibits lateral energy dissipation and drives the efficient propagation of the filament deep along the optical axis; furthermore, the 343 nm laser demonstrates superior removal rates and localisation compared to the 515 nm laser. Using super-resolution imaging, the precision cleavage cross-section is clearly categorised into four evolutionary stages: general ablation, filament ablation, transition, and mechanical cleavage. To mitigate morphological degradation induced by multiple scans, a sacrificial-layer-assisted strategy is innovatively proposed to achieve spatial damage transfer and in situ self-polishing, effectively eliminating longitudinal damage striations and residual stress-induced hackles. Finally, taper-free, high-precision separation of 1 mm × 450 μm micro-units is successfully achieved on a 220-μm-thick sapphire wafer. This technology not only achieves ultra-low-loss dicing but also establishes a highly efficient, contamination-free in situ characterisation paradigm for buried structures in hard and brittle materials. Full article

In this study, cathodic arc deposition was employed to synthesize CrAlN/TiSiN nanostructured multilayer coatings on silicon wafer substrates. The effects of the multilayer architecture on the microstructure and corrosion resistance of the coatings were systematically investigated. The structural characteristics and performance of the deposited films were analyzed using scanning electron microscopy (SEM), energy-dispersive spectroscopy (EDS), X-ray diffraction (XRD), and electrochemical polarization measurements. The experimental results demonstrate that various CrAlN/TiSiN multilayer configurations were successfully deposited, forming dense multilayer coatings with a thickness of approximately 1–2 μm and a dominant FCC β₁-NaCl crystalline structure. The presence of nanostructured multilayer interfaces effectively inhibited columnar grain growth and contributed to microstructural refinement. XRD analysis revealed competitive growth between the (111) and (200) crystallographic orientations, indicating that the crystallization behavior is influenced by the interplay between surface energy minimization and strain energy accumulation. Contact angle measurements showed that all the coatings exhibited water contact angles exceeding 90°, indicating hydrophobic characteristics and potential anti-fouling capacity. In particular, the CrAlN outer layer structure presented lower surface free energy, which further enhances the coating system’s anti-fouling capacity. Electrochemical polarization results indicate that the corrosion current density of all the coatings remained in the order of 10⁻⁷ A/cm², demonstrating excellent chemical stability. Overall, the CrAlN/TiSiN nanostructured multilayer coatings exhibit pronounced interface strengthening and densification growth mechanisms, which effectively enhance the chemical stability of silicon-based material surfaces. These results could provide valuable insights for the structural design and optimization of high-performance protective coatings. Full article

Few-layer hexagonal boron nitride (hBN) is a promising two-dimensional dielectric for electronic and neuromorphic devices. However, its practical deployment is often hindered by the thickness nonuniformity of as-grown samples and by defects introduced during the transfer-stacking process of assembled samples. In particular, the influence of the initial hBN quality on the final stacked-film quality remains insufficiently understood. Here, we report a wafer-scale strategy for fabricating high-quality few-layer hBN based on ultraflat single-crystal hBN (USC-hBN) monolayers. Compared with transfer-stacked hBN grown on Cu foil (rough hBN), stacked few-layer USC-hBN shows a much lower surface roughness and a drastically reduced wrinkle density, indicating superior flatness and interfacial cleanliness. Furthermore, memristors fabricated from six-layer USC-hBN exhibit clearer resistive-switching behavior and a higher ON/OFF ratio than those based on rough hBN, owing to the more uniform surface/interface. These results demonstrate that source-material flatness is a critical determinant of transfer-stacked hBN quality and device performance. This work provides an effective route toward reliable integration of high-quality two-dimensional dielectric films. Full article

GaN-on-Si light-emitting devices have been widely studied in the field of opto-electronics, while their optical performance and characterization accessibility are severely limited by the strong visible light absorption of the native silicon substrate. Conventional substrate transfer technologies often suffer from inherent thermal, optical, or mechanical bottlenecks. In this study, we developed a robust wafer-level substrate transfer strategy for 8-inch green GaN-on-Si light-emitting device wafers, utilizing a hybrid planarization process combined with SiO₂–SiO₂ direct bonding. The hybrid planarization precisely eliminated the 900 nm macroscopic steps, achieving sub-nanometer surface roughness for high-yield wafer bonding. We systematically investigated the physical evolution during substrate removal. Results indicate that the removal of the thick native silicon and high-stress buffer layers effectively released the additional in-plane biaxial compressive stress within the multiple quantum wells (MQWs), thereby mitigating the quantum-confined Stark effect (QCSE). Benefiting from the elimination of the light-absorbing silicon substrate and the incorporation of a built-in back-surface reflector (BSR), the transferred devices achieved a remarkable 1.9-fold enhancement in relative optical performance, albeit with an inherent trade-off of increased reverse leakage current while preserving basic diode functionality. Furthermore, optothermal dynamic analysis at high injection levels suggests a potential localized thermal bottleneck at the thick SiO₂ bonding interface, where a hypothesized heat-induced spectral red shift may counteract the carrier-screening blue shift. This work provides a feasible wafer-level substrate transfer process for GaN-on-Si devices and offers systematic experimental insights into stress relaxation and optothermal behaviors during the substrate transfer process. Full article

To address the main challenges in thickness estimation of SiC epitaxial layers from infrared reflectance spectra, including refractive index dispersion, multi-beam interference, and spectral uncertainty, this study develops a physics-constrained inversion framework for reflectance spectrum-based analysis. For the measured spectra, Savitzky–Golay filtering is first used to suppress spectral noise, and Gaussian fitting is then employed to improve the localization of interference extrema. The Sellmeier equation is introduced to characterize refractive index dispersion, and the layer thickness is obtained together with the dispersion parameters through nonlinear least squares fitting. To account for spectra affected by higher-order internal reflections, a multi-feature confidence-based identification strategy is further constructed, and an adaptive filtering procedure is introduced for multi-beam interference correction. A Monte Carlo perturbation analysis with ±0.1% peak perturbations and Gaussian noise is additionally performed to assess the robustness of the inversion results. Using SiC datasets measured at two incident angles, the proposed framework reduces the inter-angle deviation of the thickness estimates from 1.14% to 0.08% after multi-beam correction. The results support the effectiveness and robustness of the proposed workflow for the main SiC application scenario considered in this study. In addition, silicon wafer spectra are included as a supplementary transfer test to examine whether the multi-beam identification and correction strategy can be applied beyond the SiC example, rather than as a comprehensive cross-material validation of the framework. Full article

Josephson junctions are key elements in superconducting qubits. Their efficient wafer-scale characterization is crucial for process control and optimization, motivating analysis approaches that extend beyond conventional cryogenic measurements. In this work, we demonstrate that room temperature (RT) capacitance and current–voltage measurements, combined with appropriate data analysis, enable extraction of relevant junction parameters such as oxide thickness, tunnel coefficient, and interfacial defect density. Furthermore, different charge transport mechanisms can be identified from detailed current–voltage analysis. We evaluate our characterization technique using tunnel junctions fabricated on 200 mm wafers in a complementary metal–oxide–semiconductor (CMOS)-compatible subtractive process. The results show a homogeneous average oxide thickness across the wafer with a variation below 3%. A dependence of the tunnel coefficient on oxide thickness indicates a stoichiometry gradient within the oxide. Additionally, low interfacial defect densities in the range of 70–5000 defects/cm² are observed in our junctions, increasing with decreasing oxide thickness, suggesting that wet etching used for thickness control introduces interfacial trap states. Our study highlights the importance of advanced RT characterization for extracting tunnel junction parameters on the wafer scale, enabling effective process monitoring and optimization in industrial superconducting qubit manufacturing. Full article

The crystallinity of cubic silicon carbide (3C-SiC) epilayers is improved through the use of a novel wafer bonding and regrowth technique resulting in a reduction in planar defects. The process involves the epitaxial growth of a 3–6 µm thick 3C-SiC seed on silicon (Si), which is polished and bonded to a new handle wafer before the original substrate and defective interface region of the 3C-SiC epilayer are removed. Further epitaxial growth on this Bonded Switchback template results in higher quality 3C-SiC epilayers through the reduction in crystal mosaicity, stacking fault defects, and elimination of interface voids. The process could be applied to 3C-SiC grown on both on- and off-axis substrates, and the form of the new handle has no impact on the growth process, enabling this technology to be applied to sapphire or hexagonal 4H-SiC substrates. The use of such substrates would overcome the thermal budget limitations of Si substrates for 3C-SiC heteroepitaxy and ion implantation. Bonded Switchback can improve material quality for applications in power electronics, as well as see the heterogeneous integration of 3C-SiC into other device structures, potentially leading to a new range of hybrid 3C-SiC/Si devices without the high density of defects observed at the interface between these two materials. Full article

Freestanding graphene exhibits exceptional mechanical flexibility and electrical conductivity, making it well suited for varying capacitance applications. For example, when suspended above a fixed electrode, graphene will move in response to an applied bias voltage, thereby forming a varactor or voltage-controlled capacitor. In this work, we present a very detailed and scalable fabrication process for building graphene-based variable capacitor device structures. Starting with commercially available 100 mm silicon wafers with a thick thermal oxide layer, we fabricate thousands of individually accessible freestanding graphene variable capacitors using standard semiconductor methods. The process begins with metal deposition to establish alignment crosshairs, then oxide etching to create trenches, a second metal deposition to form electrodes and bonding pads, followed by large-area graphene transfer, then patterning the graphene via oxygen plasma etching, critical point drying for suspension, and finally wire bonding our devices into a package. We use optical and atomic force microscopy characterization to confirm our design specifications were met. Electrical characterization confirms successful graphene suspension through voltage-dependent capacitance measurements. The procedure presented here successfully suspends both pure multilayer graphene as well as graphene with a thick layer of PMMA. Full article