Arbitrarily Large Area Graphene Suspension with Ultralow Standoff for Varying Capacitance Applications

Abstract

Freestanding graphene exhibits exceptional mechanical flexibility and electrical conductivity, making it well suited for varying capacitance applications. For example, when suspended above a fixed electrode, graphene will move in response to an applied bias voltage, thereby forming a varactor or voltage-controlled capacitor. In this work, we present a very detailed and scalable fabrication process for building graphene-based variable capacitor device structures. Starting with commercially available 100 mm silicon wafers with a thick thermal oxide layer, we fabricate thousands of individually accessible freestanding graphene variable capacitors using standard semiconductor methods. The process begins with metal deposition to establish alignment crosshairs, then oxide etching to create trenches, a second metal deposition to form electrodes and bonding pads, followed by large-area graphene transfer, then patterning the graphene via oxygen plasma etching, critical point drying for suspension, and finally wire bonding our devices into a package. We use optical and atomic force microscopy characterization to confirm our design specifications were met. Electrical characterization confirms successful graphene suspension through voltage-dependent capacitance measurements. The procedure presented here successfully suspends both pure multilayer graphene as well as graphene with a thick layer of PMMA.

1. Introduction

Recent developments in ultralow power electronics have markedly reduced the power requirements of sensor systems to the microwatt range during active mode and to the nanowatt range in standby mode [1,2,3,4]. For applications with low duty cycles, the average power consumption is only marginally higher than standby mode [5]. These remarkable breakthroughs have enabled the possibility of powering sensors without batteries and instead harvesting its power needs from the local environment. Readily available power sources include temperature gradients, mechanical vibrations, and light [6,7,8,9,10,11].

Initial designs for mechanical energy harvesting used a varying capacitance system as an electrostatic generator [12]. Subsequent advancements demonstrated the viability of microelectromechanical systems (MEMSs) utilizing electrostatic and piezoelectric properties to harvest energy from environmental vibrations [8,13,14,15].

Due to its novel properties, graphene is a strong candidate for use in low-power energy harvesting systems. For example, graphene is an atomically thin, very flexible, and optically transparent [16,17,18,19,20]. It is also very durable with the highest tensile strength [21], and a very high Young’s modulus [22,23,24,25]. It is also metallic [26,27,28]. When doped, it is ferromagnetic at room temperature [29,30]. Additionally, the number of atomic layers in a graphene sheet can be tuned based on growth conditions, which affects all of these fundamental properties [31,32,33,34].

Graphene’s metallic yet transparent properties have already proven useful for solar energy harvesting. When an interface is created between graphene and silicon a Schottky barrier naturally forms [35]. Thus when light passes through graphene a photocurrent is generated. Numerous studies have demonstrated the efficacy of graphene for fabricating Schottky solar cells and characterized the role of graphene thickness, doping, and surface texture [36,37,38,39,40,41,42,43]. Our group has also developed a fabrication process for graphene solar cells, and it purposely mimics the strategy presented here [44]. This allows for the potential fabrication of a single graphene device that can harvest both solar and kinetic energy. Our group also demonstrated that graphene solar cells can power a sensor without using batteries [45].

The usefulness of graphene’s two-dimensional nature extends beyond its ability to be transferred onto a rigid silicon surface for solar cell fabrication. When made freestanding, graphene naturally self-compresses to form an array of ripples, which was famously thought to be impossible [46]. Ripples in graphene have been extensively studied with theoretical methods such as kinetic Ising models [47,48], Monte Carlo [49,50], density functional theory [51,52], and molecular dynamics [53,54]. Graphene ripples have also been heavily experimentally studied using scanning tunneling microscopy [55,56], atomic force microscopy (AFM) [57,58], and transmission electron microscopy [59].

From all the above studies and others, we know that graphene ripples are in constant motion [60,61,62]. Few-layer graphene has a thickness of about 1 nm and, hence, is extremely flexible [63,64,65,66]. For comparison, the thinnest cantilevers, which are designed to fluctuate in response to stimuli, have a beam thickness of about 10 nm [67]. As a result, the flexural rigidity of graphene is about three orders of magnitude lower than these cantilevers [68,69]. Flexural rigidity not only depends on thickness, but also on Young’s modulus and Poisson’s ratio. The responsiveness of freestanding graphene to its environment has allowed it to be used for thermal sensing [70,71], liquid pressure sensors [72,73], and chemical sensors [74,75]. Since freestanding graphene is in constant motion, when near a fixed electrode the pair acts as a variable capacitor being driven by local vibrations, which can be used for energy harvesting [76,77,78].

Recent advances in chemical vapor deposition graphene growth and transfer methods have enabled the fabrication of ultra-large-area suspended graphene membranes. PMMA-assisted transfers have been used to prepare high-quality monolayer and bilayer graphene membranes on through-hole substrates with diameters ranging from 10 to 750 $\mu$m [79,80]. Further improvements, including bubbling transfer, solvent replacement, and sublimation-assisted methods, have enabled suspended graphene structures with lateral dimensions extending to the millimeter scale and with high yield [81,82]. It is more difficult, but some groups have suspended large-area graphene over closed cavities [83]. For varying capacitance applications, what is needed is ultra-large area graphene suspension with an ultralow standoff.

Besides the varactor, another fascinating varying capacitance application is energy harvesting as illustrated in Figure 1. The graphene variable capacitor is on the left branch. When the graphene membrane vibrates, the separation between the membrane and the fixed electrode changes over time, which causes the capacitance to vary. A fixed DC bias voltage V and a time-dependent capacitance $C\left(t\right)$, will force electrical charges $q\left(t\right)$ to flow on and off the graphene capacitor according to the relation $q\left(t\right)=C\left(t\right)V$. When charges flow clockwise, they pass through diode D1 and charge storage capacitor C1. When charges flow counterclockwise, they will recharge the DC bias, add charge to C2, and pass through diode D2. In this way, the mechanical motion of the graphene membrane is converted to stored electrical charge. Our group recently demonstrated that a mechanically rotated variable capacitor can power a sensor. The circuit performance was extensively characterized in terms of the capacitor rotation frequency, f the capacitance variation, $\Delta C$ and the magnitude of the DC bias voltage, V [84]. A simple formula was found for the average rectified current to be $2V\Delta Cf$, and, in addition, we demonstrated that only 30 nA is required to power the latest ultralow power consuming sensors mentioned earlier.

In this study, we fabricate graphene variable capacitors by creating trenches in the oxide-coated silicon wafer, positioning fixed electrodes at the bottom of each trench, and suspending graphene over the trenches. Our group successfully suspended graphene over a trench in an earlier study [77]. However, the goal here is to increase the total area of the suspended graphene to an arbitrarily large value. To achieve this the process had to be revisited, improved, and additional steps had to be added. We present the fabrication steps in this paper as follows. We begin by depositing gold alignment markers on the surface oxide to maintain the device orientation throughout the process. We then create an array of trenches by etching away part of the oxide coating. We deposit more gold to create bonding pads attached to long metal traces at the bottom of each trench. We also create four additional bonding pads and long traces outside the trenches to create our graphene electrical contact. We transfer a sheet of graphene so it is suspended above the gold traces in the trenches but also rests on the graphene electrical contact trace. The graphene sheet is then plasma etched to remove graphene from alternating regions over the trenches to aid suspension. The final device is wire bonded into a 28-pin package and tested. The capacitance is measured using plus and minus DC bias voltages to confirm the graphene deflects with increasing electrostatic force.

2. Materials and Methods

Commercially available 100 mm silicon wafers with 1–10 $\Omega ·$cm resistivity, 500 $\mu$m thickness, $\langle 100\rangle$ orientation, and a 2 $\mu$m wet thermal oxide layer were used in this study. The wafer was first divided into four quadrants, and then each quadrant was further diced into six chips, as shown in the top left of Figure 2 and labeled 1 through 6. Each chip measures 16.6 mm × 16.6 mm and will eventually contain four identical devices prepared in parallel, as illustrated in the top right of Figure 2. After fabrication and dicing, multilayer graphene is placed on each device as shown in green in the bottom right of Figure 2. The completed device is wire-bonded into a standard 28-pin package as shown in the bottom left of Figure 2.

3. Results and Discussion

3.1. Alignment Markers

3.1.1. Alignment Marker Design

The first step in our process is to create our alignment marker design, as shown in Figure 3a. This pattern shows four devices made in parallel as mentioned earlier. Each device contains a label, four crosshair markers, and one small triangle marker. In addition, the full-chip pattern includes one large triangle marker at the bottom. A zoomed in view of one crosshair is shown in Figure 3b. It has two perpendicular rectangles measuring 400 $\mu$m by 10 $\mu$m. A zoomed in view of the single large triangle is shown in Figure 3c. It has a base and height of 1000 $\mu$m. A zoomed in view of a smaller triangle marker is shown in Figure 3d. It has a base and height of 200 $\mu$m. In general, these markers allow us to precisely align the chips into the various instruments and to align one layer to another.

3.1.2. Alignment Marker Process

An illustration of our alignment marker fabrication process is shown in Figure 4. The process begins with a clean and dry chip as illustrated in Figure 4a. Cleaning the chip involves acetone ultrasonic for 5 min, IPA ultrasonic for 5 min, DI water ultrasonic for 5 min, dry with compressed nitrogen, anneal at 180 °C for 15 min, and plasma etch for 1 min in $O_2$. A photoresist layer is then added as shown in Figure 4b. The chip is spin-coated at 2500 rpm for 1 min and baked at 110 °C for 3 min. Our alignment pattern is transferred onto the photoresist using maskless photolithography, as shown in Figure 4c. The chip is developed for 30 s, followed by rinsing in DI water for 1 min and the result is illustrated in Figure 4d. Next 5 nm of chromium followed by 45 nm of gold is deposited as illustrated in Figure 4e. Finally, lift-off is performed to remove the unexposed photoresist leaving only our metal pattern as illustrated in Figure 4f. Removing the unexposed photoresist involves stripper soak at 80 °C for 10 min, second stripper soak at 80 °C for 10 min, IPA ultrasonic for 5 min, DI water ultrasonic for 5 min, dry with compressed nitrogen, anneal at 180 °C for 15 min, and plasma etch for 1 min in $O_2$.

3.1.3. Alignment Marker Characterization

An optical image of our full chip after the metal alignment pattern is transferred is shown in Figure 5a. The four sample labels and the large triangle are relatively easy to see at this scale. A higher-magnification image of a single device on this same chip is shown in Figure 5b. The sample label, the four crosshairs, and the small triangle are visible. An AFM image of a section of a crosshair is shown in Figure 5c. AFM measurements are used to determine the achieved crosshair width and thickness. A line profile taken from the AFM image is shown in Figure 5d. The crosshair is about 10 $\mu$m wide and 50 nm thick. This metal thickness is enough for the maskless photolithography automatic alignment feature to detect. The large and small triangles are used by the person placing the chip into the maskless photolithography system.

3.2. Oxide Etch

3.2.1. Oxide Etch Pattern Design

The second step in our process is to create the oxide etch pattern design, as shown in Figure 6a. Again, the pattern creates four devices in parallel. A zoomed-in view of one device is shown in Figure 6b. Here it is easy to see that each device has 64 trenches with large square pads at one end. Above and below the array of trenches is an array of small squares. A zoomed in view of four trenches is shown in Figure 6c. The trenches are 6 $\mu$m wide and around 2000 $\mu$m in length. At the end of each trench is a large square measuring 200 $\mu$m on each side. This large square is where the bonding pad will be built. Notice we staggered the bonding pads to make more space for the wire bonder. A zoomed-in view of one of the smaller squares measuring 16 $\mu$m on each side is shown in Figure 6d. The small squares are for diagnostics and its function will be discussed later.

3.2.2. Oxide Etch Process

An illustration of our chip oxide etch process is shown in Figure 7. The process begins with a clean and dry chip as shown in Figure 7a. This chip has the gold alignment markers on it. We follow the same chip cleaning procedure discussed earlier. A photoresist layer is then added as shown in Figure 7b. We follow the same procedure discussed earlier. Our etch pattern is transferred to the photoresist using a maskless photolithography system, as shown in Figure 7c. The chip is then developed as before to reveal the pattern as shown in Figure 7d. The chip is then etched as shown in Figure 7e. The etch process involves placing the chip in a 50:1 buffered oxide etch solution which removes the exposed $Si{O}_2$ until the desired depth is achieved. Finally, lift-off is performed using the same procedure as before leaving our etched pattern in the chip, as shown in Figure 7f.

3.2.3. Oxide Etch Characterization

An optical image of our chip after etching is shown in Figure 8a. The four identical etch patterns are faint. Nevertheless, one can make out that the pattern was successfully etched into the chip. A high magnification optical image of our small square is shown in Figure 8b. An AFM image of the same square is shown in Figure 8c. A line profile taken from the AFM image is shown in Figure 8d. The small square was etched into a deep well and it is about 16 $\mu$m across. More importantly, the depth of etched well was found to be about 300 nm using AFM. This is the same etch depth achieved throughout the chip. This depth plays a critical role in the stand-off between the top surface of the chip where the graphene will be placed and the bottom of the trench. Of course, we still need to deposit a metal trace at the bottom of the trench. We do have some control over the thickness of the metal layer we deposit. As a result, next we use the thickness of the metal layer to fine tune the stand-off height.

3.3. Metal Deposition

3.3.1. Metal Deposition Pattern

The third step in our process is to create our metal deposition pattern as shown in Figure 9a. This pattern creates four devices in parallel. A zoomed-in view of one device is shown in Figure 9b. Here it is easy to see the 64 trenches with bonding pads at the end. We label each pad for easy tracking and communication purposes. Notice we also added four larger bonding pads at the outer corners of the device and connected these to each other with double traces. These will be used for electrical contact to the graphene. A zoomed-in view of our graphene electrical contact trace and one trench is shown in Figure 9c. The various dimensions are shown here as well. A zoomed-in view of the metal pattern inside the trench is shown with its dimension in Figure 9d. With this design we have one graphene electrical contact, but we have four bonding pads to choose from for both redundancy and convenience. In addition, each trench, which becomes the fixed side of a variable capacitor, has one bonding pad giving us 64 individually addressable variable capacitors with a common graphene connection. Of course, we can easily connect all 64 capacitors together in parallel to produce a single large capacitance capacitor. For that matter, once wire bonded, each package can be connected in parallel with other packages, as well. Finally, the thin trench lines used here also allow us to create a new pattern with 10 times more trenches, if desired.

3.3.2. Metal Deposition Process

An illustration of our metal deposition process is shown in Figure 10. The process is nearly identical to our alignment marker process presented earlier. This time metal will be deposited at the bottom of the etched trenches as well as on the top oxide surface. The process begins with a clean and dry chip as shown in Figure 10a. A photoresist is added as shown in Figure 10b. Our metal deposition pattern is written as shown in Figure 10c. After development, the resulting chip is as shown in Figure 10d. Next 5 nm of chromium followed by 95 nm of gold in deposited as shown in Figure 10e. We require more than 50 nm of gold for the wire bonder to work, but we can adjust this overall thickness to set the actual stand-off distance between the flexible graphene and the fixed metal electrode below it in the trench. Finally, lift-off is performed leaving only our metal pattern on top and in the trenches, as shown in Figure 10f. Once the metal deposition is completed we dice the chip into four identical devices. The final device measures approximately 8 mm by 8 mm and fits inside our device package.

3.3.3. Metal Deposition Characterization

An optical image of our chip after metal deposition is shown in Figure 11a. A zoomed-in optical image of a single device measuring about 8 mm × 8 mm with 64 trenches and the two metal traces that graphene will rest on is shown in Figure 11b. An AFM image of a metal bonding pad inside the etched trench is shown in Figure 11c. A line profile taken from the AFM image is shown in Figure 11d. From the line profile, the surface of the metal bonding pad is about 200 $\mu$m below the top of the device where the graphene will rest. Of course, this same metal thickness is also on the top metal traces and used for wire bonding and graphene contacts.

3.4. Graphene Transfer

3.4.1. Graphene Transfer Size and Placement Location

The fourth step in our process is to create the size and placement location for the graphene, as shown in Figure 12. The image shows our final device pattern with all the details. Notice the 64 trenches, the four outer crosshairs, the four outer bonding pads with the interconnecting double traces, the array of small square deep wells used for AFM depth profiling, and finally the green semitransparent graphene sheet that measures 3 mm × 5 mm. Notice the graphene partially covers all 64 trenches, simultaneously rests on the double metal trace down the center, yet avoids contacting any of the bonding pads. Our wire bonder only bonds to gold. If graphene covers the bonding pad, the wire bonder will fail to attach its wire to the bonding pad.

3.4.2. Graphene Transfer Process

An illustration of our graphene transfer process is shown in Figure 13. The process begins with a clean chip as illustrated in Figure 13a. We use the same cleaning procedure as discussed before. We cut our commercially available PMMA–graphene to size and place it in DI water where it floats, as shown in Figure 13b. Our device is placed under the PMMA–graphene and precisely aligned using tweezers as shown in Figure 13c. At this stage, the device with the PMMA–graphene is lifted out of the water and allowed to dry overnight without heating, as shown in Figure 13d. We can choose to leave the PMMA attached to the graphene or remove it before further processing. Both types of devices are useful. Pure graphene is more flexible and PMMA–graphene is thicker and more massive. To remove the PMMA, we place the entire device into acetone for 60 min as illustrated in Figure 13e. Once the device is removed from the acetone the PMMA is no longer there, as shown in Figure 13f. In the end, we make two types of devices. The first type makes suspended PMMA–graphene capacitors and the other type makes suspended pure graphene capacitors.

3.4.3. Graphene Transfer Characterization

An optical image of a single device measuring about 8 mm × 8 mm with pure graphene measure 3 mm × 5 mm on top is shown in Figure 14. The graphene partially covers most of the trenches. The graphene naturally rests on the double metal trace down the center, but does not touch any of the bonding pads.

3.5. Graphene Etch and Suspension

3.5.1. Graphene Etch Pattern

The fifth and final step in our process is to create a graphene etch pattern to aid suspension as shown in Figure 15a. A zoomed-in view of the graphene bonding pad and the adjacent trench with graphene is shown in Figure 15b. A zoomed-in view of a small section of graphene over a trench is shown in Figure 15c. At this scale it is easiest to see the graphene etch pattern. Notice we remove half the graphene covering the trenches using a 10 $\mu$m wide by 100 $\mu$m tall rectangle. The pattern is repeated every 20 $\mu$m. The array of 10 $\mu$m wide holes directly above the trenches assists with removing fluid from the trenches to aid the suspension of the adjacent 10 $\mu$m wide graphene [69].

3.5.2. Graphene Etch Process

An illustration of our graphene etch process is shown in Figure 16. The process begins with a dry device with the graphene touching both the oxide surface and the gold surface, as shown in Figure 16a. Photoresist is added just like earlier, as shown in Figure 16b. Our graphene etch pattern is written as shown in Figure 16c. After development the resulting device is shown in Figure 16d. Next the device is etched using an oxygen plasma, as shown in Figure 16e. This step is carried out in 1 min time increments until the graphene is removed as observed under an optical microscope. Finally, lift-off is performed using the same procedure as earlier, followed by soaking the device in IPA, as shown in Figure 16f.

3.5.3. Graphene Etch Characterization

An optical image of the device after oxygen plasma etching is shown in Figure 17a. A zoomed-in view of 11 trenches is shown in Figure 17b. At this scale it is easier to see the graphene has been patterned along the trenches. Essentially half the graphene was removed using a 20 $\mu$m wide repeated pattern. With half the graphene removed, the device in IPA solution is placed in our critical point dryer. This will dry the sample and leave the graphene suspended, after which the devices are wire bonded into a standard breadboard compatible package. Making the graphene freestanding was a very complex problem to solve. Initial suspension occurs because graphene floats on the surface of liquid IPA. As the liquid evaporates the graphene stays on its surface even as the level drops. Once the liquid surface reaches the bottom of the trench the graphene sticks to the gold surface at the bottom. To avoid this, we use a critical point dryer. However, the liquid IPA must be replaced with liquid $C{O}_2$ in a very short time period for the critical point dryer to work. The arrays of holes cut into the graphene every 10 $\mu$m allows for rapid fluid exchange.

3.6. Graphene Variable Capacitance

In order to confirm the graphene over the trench forms a variable capacitor, we test the structures using the circuit schematic shown in Figure 18a. The setup uses an AC voltage source with a DC voltage offset connected to a single graphene variable capacitor and an AC ammeter. We set the AC voltage frequency to 100 kHz with an amplitude of 500 mV. A plot of the change in capacitance with applied DC bias voltage for pure graphene device is shown in Figure 18b. Notice the capacitance increases by about 5 pF when either a positive or negative bias voltage is applied. This response indicates that the graphene is being pulled toward the fixed electrode due to the electrostatic force, which is attractive for both positive and negative biases. A plot of the change in capacitance with an applied DC bias voltage for a single PMMA–graphene device is shown in Figure 18c. Notice the capacitance of the PMMA–graphene responds similarly and increases by about 8 pF when either a positive or negative bias voltage is applied. Using a sensitive capacitance meter we also measure the capacitance of a single trench in time as shown in Figure 18d. Here the capacitance is about 1 pF with clear fluctuations in time.

The AC capacitance of the variable capacitor was calculated from

$$C={\displaystyle \frac{I}{f\times \pi \times V_{\mathrm{pp}}}},$$

where I is the measured AC current, f is the drive frequency, and $V_{\mathrm{pp}}$ is the peak-to-peak AC voltage. The DC offset voltage was swept from 0 to $+9$ V and from 0 to $-9$ V to characterize both the PMMA–graphene devices and the pure graphene devices.

We use an ultra-precise capacitance meter to make these measurements. It uses probes and a three-wire method to shield the leads, and as a result it is capable of measuring the capacitance down to the attoFarad level. For the wire bonded samples, there is parasitic capacitance; however, from the formula presented earlier, the current is only due to the changing capacitance in time. The results presented in Figure 18 are for a single trench. One can wire all 64 graphene variable capacitors together in a single package to boost the signal.

4. Conclusions

In this study, we presented a detailed fabrication process for producing an array of graphene-based variable capacitors for varying capacitance applications. Starting with a 100 mm diameter silicon wafer with a thermal oxide layer, thousands of variable capacitors were made, with 64 individually accessible graphene variable capacitors per packaged device. First, we diced the 100 mm wafer to a size that allowed us to produce four devices in parallel, then we added metallic alignment markers, followed by etching trenches into the oxide surface, depositing metal inside the trenches, and placing multilayer graphene over the trenches. Using oxygen plasma etching we patterned the graphene and suspended it using a critical point dryer. We successfully suspended both pure graphene and PMMA–graphene. The variable capacitors were wire bonded into a 28-pin package and tested. A single graphene suspension has capacitance variations of about 5 pF as a DC bias voltage is applied and forces the graphene closer to the fixed electrode below it.