Search Results (45)

The development of an integrated circuit faces the challenge of the physical limit of Moore’s Law. One of the most important “Beyond Moore” challenges is the scaling down of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) versus their increasing static power consumption. This is because, at room temperature, the thermal emission transportation mechanism will cause a physical limitation on subthreshold swing (SS), which is fundamentally limited to a minimum value of 60 mV/decade for MOSFETs, and accompanied by an increase in off-state leakage current with the process of scaling down. Moreover, the impacts of short-channel effects on device performance also become an increasingly severe problem with channel length scaling down. Due to the band-to-band tunneling mechanism, Tunnel Field-Effect Transistors (TFETs) can reach a far lower SS than MOSFETs. Recent research works indicated that TFETs are already becoming some of the promising candidates of conventional MOSFETs for ultra-low-power applications. This paper provides a review of some advances in materials and structures along the evolutionary process of TFETs. An in-depth discussion of both experimental works and simulation works is conducted. Furthermore, the performance of TFETs with different structures and materials is explored in detail as well, covering Si, Ge, III-V compounds and 2D materials, alongside different innovative device structures. Additionally, this work provides an outlook on the prospects of TFETs in future ultra-low-power electronics and biosensor applications. Full article

To address the severe gate-induced drain leakage (GIDL) issue in fully depleted germanium-on-insulator (FD-GeOI) multi-subchannel tunneling field-effect transistors (MS TFETs), this paper proposes a stepped gate oxide (SGO) structure. In the off-state, the SGO structure effectively suppresses GIDL by reducing the electric field intensity at the channel/drain interface while simultaneously decreasing gate capacitance to reduce static power consumption. Based on an accurate device model, a systematic investigation was conducted into the effects of varying the thickness and length of the SGO structure on TFET performance, enabling the optimization of the SGO design. The simulation results demonstrate that, compared to normal MS TFETs, the SGO MS TFET reduces the off-state GIDL current ($I_{\mathrm{off}}$) from $4.6\times {10}^{-7}$ A to $2.6\times {10}^{-11}$ A, achieving a maximum improvement of 4.22 orders of magnitude in the on-state-to-off-state current ratio ($I_{\mathrm{on}}/I_{\mathrm{off}}$) and a 28% reduction in subthreshold swing (SS). Furthermore, compared to lightly doped drain (LDD) MS TFETs, the SGO MS TFET achieves a 32% reduction in total gate capacitance and a 23% enhancement in carrier mobility at the channel/drain interface. This study demonstrates that SGO provides an effective solution for GIDL suppression. Full article

We systematically study the transport properties of arsenene nanoribbon tunneling field-effect transistors (TFETs) along the armchair directions using first-principles calculations based on density functional theory combined with the non-equilibrium Green’s function approach. The pristine nanoribbon TFET devices with and without underlap (UL) exhibit poor performance. Introducing a H defect in the left UL region between the source and channel can drastically enhance the ON-state currents and reduce the SS to below 60 mV/decade. When the H defect is positioned far from the gate and/or at the center sites, the ON-state currents are substantially enhanced, meeting the International Technology Roadmap for Semiconductors requirements for high-performance and low-power devices with 5 nm channel length. The gate-all-around (GAA) structure can further improve the performance of the devices with H defects. Particularly for the devices with H defects near the edge, the GAA structure significantly reduces the SS values as low as 35 mV/decade. Our study demonstrates that GAA structure can greatly enhance the performance of the arsenene nanoribbon TFET devices with H defects, providing theoretical guidance for improving TFET performance based on two-dimensional material nanoribbons through the combination of defect engineering and GAA gate structures. Full article

In this article, we propose a dual-gate dielectric face tunnel field-effect transistor (DGDFTFET) that can exhibit three different output voltage states. Meanwhile, according to the requirements of the ternary operation in the ternary inverter, four related indicators representing the performance of the DGDFTFET are proposed, and we explain the impact of these indicators on the inverter and confirm that better indicators can be obtained by choosing appropriate design parameters for the device. Then, the ternary inverter implemented with this device can exhibit voltage transfer characteristics (VTCs) with three stable output voltage levels and bigger static noise margins (SNMs). In addition, by comparing the indicators of the DGDFTFET and a face tunnel field-effect transistor (FTFET), as well as the SNM of inverters, it is demonstrated that the performance of the DGDFTFET far surpasses the FTFET. Full article

This paper investigates the performance of vacuum gate dielectric doping-free carbon nanotube/nanoribbon field-effect transistors (VGD-DL CNT/GNRFETs) via computational analysis employing a quantum simulation approach. The methodology integrates the self-consistent solution of the Poisson solver with the mode space non-equilibrium Green’s function (NEGF) in the ballistic limit. Adopting the vacuum gate dielectric (VGD) paradigm ensures radiation-hardened functionality while avoiding radiation-induced trapped charge mechanisms, while the doping-free paradigm facilitates fabrication flexibility by avoiding the realization of a sharp doping gradient in the nanoscale regime. Electrostatic doping of the nanodevices is achieved via source and drain doping gates. The simulations encompass MOSFET and tunnel FET (TFET) modes. The numerical investigation comprehensively examines potential distribution, transfer characteristics, subthreshold swing, leakage current, on-state current, current ratio, and scaling capability. Results demonstrate the robustness of vacuum nanodevices for high-performance, radiation-hardened switching applications. Furthermore, a proposal for extrinsic enhancement via doping gate voltage adjustment to optimize band diagrams and improve switching performance at ultra-scaled regimes is successfully presented. These findings underscore the potential of vacuum gate dielectric carbon-based nanotransistors for ultrascaled, high-performance, energy-efficient, and radiation-immune nanoelectronics. Full article

After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures. Full article

In this paper, a new junctionless graphene nanoribbon tunnel field-effect transistor (JLGNR TFET) is proposed as a multi-gas nanosensor. The nanosensor has been computationally assessed using a quantum simulation based on the self-consistent solutions of the mode space non-equilibrium Green’s function (NEGF) formalism coupled with the Poisson’s equation considering ballistic transport conditions. The proposed multi-gas nanosensor is endowed with two top gates ensuring both reservoirs’ doping and multi-gas sensing. The investigations have included the I_DS-V_GS transfer characteristics, the gas-induced electrostatic modulations, subthreshold swing, and sensitivity. The order of change in drain current has been considered as a sensitivity metric. The underlying physics of the proposed JLGNR TFET-based multi-gas nanosensor has also been studied through the analysis of the band diagrams behavior and the energy-position-resolved current spectrum. It has been found that the gas-induced work function modulation of the source (drain) gate affects the n-type (p-type) conduction branch by modulating the band-to-band tunneling (BTBT) while the p-type (n-type) conduction branch still unaffected forming a kind of high selectivity from operating regime point of view. The high sensitivity has been recorded in subthermionic subthreshold swing (SS < 60 mV/dec) regime considering small gas-induced gate work function modulation. In addition, advanced simulations have been performed for the detection of two different types of gases separately and simultaneously, where high-performance has been recorded in terms of sensitivity, selectivity, and electrical behavior. The proposed detection approach, which is viable, innovative, simple, and efficient, can be applied using other types of junctionless tunneling field-effect transistors with emerging channel nanomaterials such as the transition metal dichalcogenides materials. The proposed JLGNRTFET-based multi-gas nanosensor is not limited to two specific gases but can also detect other gases by employing appropriate gate materials in terms of selectivity. Full article

In this study, a frequency doubler that consists of a tunnel field-effect transistor (TFET) with dual pocket doping is proposed, and its operation is verified using technology computer-aided design (TCAD) simulations. The frequency-doubling operation is important to having symmetrical current characteristics, which eliminate odd harmonics and the need for extra filter circuitry. The proposed TFET has intrinsically bidirectional and controllable currents that can be implemented by pocket doping, which is located at the junction between the source/drain (S/D) and the channel region, to modify tunneling probabilities. The source-to-channel (I_SC) and channel-to-drain currents (I_CD) can be independently changed by managing each pocket doping concentration on the source and drain sides (N_S,POC and N_D,POC). After that, the current matching process was investigated through N_S,POC and N_D,POC splits, respectively. However, it was found that the optimized doping condition achieved at the device level (namely, a transistor evaluation) is not suitable for a frequency doubler operation because the voltage drop generated by a load resistor in the frequency doubler circuit configuration causes the currents to be unbalanced between I_SC and I_CD. Therefore, after symmetrical current matching was performed by optimizing N_S,POC and N_D,POC at the circuit level, it was clearly seen that the output frequency was doubled in comparison to the input sinusoidal signal. In addition, the effects of the S/D and pocket doping variations that can occur during process integration were investigated to determine how much frequency multiplications are affected, and these variations have the immunity of S/D doping and pocket doping length changes. Furthermore, the impact of device scaling with gate length (L_G) variations was evaluated. Based on these findings, the proposed frequency doubler is anticipated to offer benefits for circuit design and low-power applications compared to the conventional one. Full article

A new structure for PNPN tunnel field-effect transistors (TFETs) has been designed and simulated in this work. The proposed structure incorporates the polarity bias concept and the gate work function engineering to improve the DC and analog/RF figures of merit. The proposed device consists of a control gate (CG) and a polarity gate (PG), where the PG uses a dual-material gate (DMG) structure and is biased at −0.7 V to induce a P⁺ region in the source. The PNPN structure introduces a local minimum on the conduction band edge curve at the tunneling junction, which dramatically reduces the tunneling width. Furthermore, we show that incorporating the DMG architecture further enhances the drive current and improves the subthreshold slope (SS) characteristics by introducing an additional electric field peak. The numerical simulation reveals that the electrically doped PNPN TFET using DMG improves the DC and analog/RF performances in comparison to a conventional single-material gate (SMG) device. Full article

This study discusses the use of a triple material gate (TMG) junctionless tunnel field-effect transistor (JLTFET) as a biosensor to identify different protein molecules. Among the plethora of existing types of biosensors, FET/TFET-based devices are fully compatible with conventional integrated circuits. JLTFETs are preferred over TFETs and JLFETs because of their ease of fabrication and superior biosensing performance. Biomolecules are trapped by cavities etched across the gates. An analytical mathematical model of a TMG asymmetrical hetero-dielectric JLTFET biosensor is derived here for the first time. The TCAD simulator is used to examine the performance of a dielectrically modulated label-free biosensor. The voltage and current sensitivity of the device and the effects of the cavity size, bioanalyte electric charge, fill factor, and location on the performance of the biosensor are also investigated. The relative current sensitivity of the biosensor is found to be about 10¹³. Besides showing an enhanced sensitivity compared with other FET- and TFET-based biosensors, the device proves itself convenient for low-power applications, thus opening up numerous directions for future research and applications. Full article

Biosensors based on tunnel FET for label-free detection in which a nanogap is introduced under gate electrode to electrically sense the characteristics of biomolecules, have been studied widely in recent years. In this paper, a new type of heterostructure junctionless tunnel FET biosensor with an embedded nanogap is proposed, in which the control gate consists of two parts, namely the tunnel gate and auxiliary gate, with different work functions; and the detection sensitivity of different biomolecules can be controlled and adjusted by the two gates. Further, a polar gate is introduced above the source region, and a P+ source is formed by the charge plasma concept by selecting appropriate work functions for the polar gate. The variation of sensitivity with different control gate and polar gate work functions is explored. Neutral and charged biomolecules are considered to simulate device-level gate effects, and the influence of different dielectric constants on sensitivity is also researched. The simulation results show that the switch ratio of the proposed biosensor can reach 10⁹, the maximum current sensitivity is 6.91 × 10², and the maximum sensitivity of the average subthreshold swing (SS) is 0.62. Full article

In this paper, a novel ferroelectric-based electrostatic doping (Fe-ED) nanosheet tunneling field-effect transistor (TFET) is proposed and analyzed using technology computer-aided design (TCAD) Sentaurus simulation software. By inserting a ferroelectric film into the polarity gate, the electrons and holes are induced in an intrinsic silicon film to create the p-source and the n-drain regions, respectively. Device performance is largely independent of the chemical doping profile, potentially freeing it from issues related to abrupt junctions, dopant variability, and solid solubility. An improved ON-state current and I_ON/I_OFF ratio have been demonstrated in a 3D-calibrated simulation, and the Fe-ED NSTFET’s on-state current has increased significantly. According to our study, Fe-ED can be used in versatile reconfigurable nanoscale transistors as well as highly integrated circuits as an effective doping strategy. Full article

Tunnel Field-Effect Transistors (TFETs) have been considered one of the most promising technologies to complement or replace CMOS for ultra-low-power applications, thanks to their subthreshold slope below the well-known limit of 60 mV/dec at room temperature holding for the MOSFET technologies. Nevertheless, TFET technology still suffers of ambipolar conduction, limiting its applicability in digital systems. In this work, we analyze through SPICE simulations, the impact of the symmetric and asymmetric ambipolarity in failure and power consumption for TFET-based complementary logic circuits. Our results clarify the circuit-level effects induced by the ambipolarity feature, demonstrating that it affects the correct functioning of logic gates and strongly impacts power consumption. We believe that our outcomes motivate further research towards technological solutions for ambipolarity suppression in TFET technology for near-future ultra-low-power applications. Full article

Two-dimensional (2D) transition-metal dichalcogenides (TMDCs) have attracted attention as promising next-generation electronic devices and sensors. In this study, we fabricated a novel nanoelectronic device based on a black-phosphorus-gated WSe₂/SnSe₂ van der Waals (vdW) tunnel field-effect transistor (TFET), where hexagonal boron nitride (h-BN) was used as the gate insulator. We performed morphological, electrical, and optoelectronic characterizations. The p-WSe₂/n-SnSe₂ heterostructure-based TFET exhibited p-type behavior with a good dependence on the gate voltage. The TFET device showed a trend toward negative differential resistance (NDR) originating from band-to-band tunneling, which can be tuned by applying a gate voltage. The optoelectronic performance of the TFET device was low, with a maximum photoresponsivity of 11 mA W⁻¹, owing to the large device length. The results obtained herein promote the integration of black phosphorus into low-energy-consumption 2D vdW TFETs. Full article

In this paper, an L-shaped tunneling field effect transistor (LTFET) with ferroelectric gate oxide layer (Si: HfO₂) is proposed. The electric characteristic of NC-LTFET is analyzed using Synopsys Sentaurus TCAD. Compared with the conventional LTFET, a steeper subthreshold swing (SS = 18.4 mV/dec) of NC-LTFET is obtained by the mechanism of line tunneling at low gate voltage instead of diagonal tunneling, which is caused by the non-uniform voltage across the gate oxide layer. In addition, we report the polarization gradient effect in a negative capacitance TFET for the first time. It is noted that the polarization gradient effect should not be ignored in TFET. When the polarization gradient parameter g grows larger, the dominant tunneling mechanism that affects the SS is the diagonal tunneling. The on-state current (I_on) and SS of NC-LTFET become worse. Full article