Journal of Low Power Electronics and Applications

Research

13 pages, 1777 KiB

Open AccessArticle

A Time-Mode PWM 1st Order Low-Pass Filter

by Konstantinos P. Pagkalos, Orfeas Panetas-Felouris and Spyridon Vlassis

J. Low Power Electron. Appl. 2023, 13(2), 32; https://doi.org/10.3390/jlpea13020032 - 6 May 2023

Cited by 3 | Viewed by 2865

In this work, a first-order low-pass filter is proposed as suitable for time-mode PWM signal processing. In time-mode PWM signal processing, the pulse width of a rectangular pulse is the processing variable. The filter is constructed using basic time-mode building blocks such as [...] Read more.

In this work, a first-order low-pass filter is proposed as suitable for time-mode PWM signal processing. In time-mode PWM signal processing, the pulse width of a rectangular pulse is the processing variable. The filter is constructed using basic time-mode building blocks such as time registers and time adders and so it is characterized by low complexity which can lead to the modular and versatile design of higher-order filters. All the building blocks of the filter were designed and verified in a TSMC 65 nm technology process. The sampling frequency was 5 MHz, the gain of the filter at low frequencies was at −0.016 dB, the cut-off frequency was 1.2323 MHz, and the power consumption was around 59.1 μW. Full article

(This article belongs to the Special Issue Recent Advances on Design of Analog/Digital Circuits for Contemporary Applications)

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18 pages, 8732 KiB

Open AccessArticle

Buck-Boost Charge Pump Based DC-DC Converter

by Evi Keramida, George Souliotis, Spyridon Vlassis and Fotis Plessas

J. Low Power Electron. Appl. 2023, 13(2), 27; https://doi.org/10.3390/jlpea13020027 - 21 Apr 2023

Cited by 4 | Viewed by 4200

Abstract

This paper presents a novel inductorless dual-mode buck-boost charge pump (CP) based DC-DC converter. The proposed architecture allows the same circuit to accomplish two modes of operation, buck and boost, for degrading or elevating the output voltage, respectively, compared to the input. To [...] Read more.

This paper presents a novel inductorless dual-mode buck-boost charge pump (CP) based DC-DC converter. The proposed architecture allows the same circuit to accomplish two modes of operation, buck and boost, for degrading or elevating the output voltage, respectively, compared to the input. To achieve each mode, only a switching of the input–output connections is needed without any other modification in the design of the DC-DC converter. The dual-mode configuration aims to merge two different functions into one circuit, minimizing the design time and the area the DC-DC converter occupies on the die. The proposed buck-boost CP has been designed using TSMC 65 nm complementary metal–oxide–semiconductor (CMOS) technology. The functional input voltage range of the CP in boost mode is 1.2 V to 1.8 V and the typical output voltage is 1.8 V. For the buck mode, the input voltage range is 3.2 V to 3.6 V and the output is 1.5 V. For both modes, the output can be easily modified to new values by changing the comparator configuration. Efficiency results are also provided for the two modes. Full article

(This article belongs to the Special Issue Recent Advances on Design of Analog/Digital Circuits for Contemporary Applications)

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19 pages, 10651 KiB

Open AccessArticle

A Ka-Band SiGe BiCMOS Quasi-F⁻¹ Power Amplifier Using a Parasitic Capacitance Cancellation Technique †

by Vasileios Manouras and Ioannis Papananos

J. Low Power Electron. Appl. 2023, 13(2), 23; https://doi.org/10.3390/jlpea13020023 - 24 Mar 2023

Viewed by 2319

Abstract

This paper deals with the design, analysis, and implementation of a Ka-band, single-stage, quasi-inverse class F power amplifier (PA). A detailed methodology for the evaluation of the active device’s output capacitance is described, enabling the designing of a second-harmonically tuned load and resulting [...] Read more.

This paper deals with the design, analysis, and implementation of a Ka-band, single-stage, quasi-inverse class F power amplifier (PA). A detailed methodology for the evaluation of the active device’s output capacitance is described, enabling the designing of a second-harmonically tuned load and resulting in enhanced performance. A simplified model for the extraction of time-domain intrinsic voltage and current waveforms at the output of the main active core is introduced, enforcing the implementation process of the proposed quasi-inverse class F technique. The PA is fabricated in a 130 nm SiGe BiCMOS technology with

f_{T} / f_{m a x} = 250 / 370 GHz

and it is suitable for 5G applications. It achieves

33 %

peak power-added efficiency (

P A E

),

18.8 dBm

saturation output power

P_{s a t}

, and

14.7 dB

maximum large-signal power gain

G

at the operating frequency of

38 GHz

. The PA’s response is also tested under a modulated-signal excitation and simulation results are denoted in this paper. The chip size is

0.605 \times 0.712 {mm}^{2}

including all pads. Full article

(This article belongs to the Special Issue Recent Advances on Design of Analog/Digital Circuits for Contemporary Applications)

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13 pages, 1158 KiB

Open AccessArticle

Decoding Algorithms and HW Strategies to Mitigate Uncertainties in a PCM-Based Analog Encoder for Compressed Sensing

by Carmine Paolino, Alessio Antolini, Francesco Zavalloni, Andrea Lico, Eleonora Franchi Scarselli, Mauro Mangia, Alex Marchioni, Fabio Pareschi, Gianluca Setti, Riccardo Rovatti, Mattia Luigi Torres, Marcella Carissimi and Marco Pasotti

J. Low Power Electron. Appl. 2023, 13(1), 17; https://doi.org/10.3390/jlpea13010017 - 13 Feb 2023

Viewed by 2568

Abstract

Analog In-Memory computing (AIMC) is a novel paradigm looking for solutions to prevent the unnecessary transfer of data by distributing computation within memory elements. One such operation is matrix-vector multiplication (MVM), a workhorse of many fields ranging from linear regression to Deep Learning. [...] Read more.

Analog In-Memory computing (AIMC) is a novel paradigm looking for solutions to prevent the unnecessary transfer of data by distributing computation within memory elements. One such operation is matrix-vector multiplication (MVM), a workhorse of many fields ranging from linear regression to Deep Learning. The same concept can be readily applied to the encoding stage in Compressed Sensing (CS) systems, where an MVM operation maps input signals into compressed measurements. With a focus on an encoder built on top of a Phase-Change Memory (PCM) AIMC platform, the effects of device non-idealities, namely programming spread and drift over time, are observed in terms of the reconstruction quality obtained for synthetic signals, sparse in the Discrete Cosine Transform (DCT) domain. PCM devices are simulated using statistical models summarizing the properties experimentally observed in an AIMC prototype, designed in a 90 nm STMicroelectronics technology. Different families of decoders are tested, and tradeoffs in terms of encoding energy are analyzed. Furthermore, the benefits of a hardware drift compensation strategy are also observed, highlighting its necessity to prevent the need for a complete reprogramming of the entire analog array. The results show >30 dB average reconstruction quality for mid-range conductances and a suitably selected decoder right after programming. Additionally, the hardware drift compensation strategy enables robust performance even when different drift conditions are tested. Full article

(This article belongs to the Special Issue Recent Advances on Design of Analog/Digital Circuits for Contemporary Applications)

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16 pages, 1105 KiB

Open AccessArticle

Minimum Active Component Count Design of a PI^λD^μ Controller and Its Application in a Cardiac Pacemaker System

by Julia Nako, Costas Psychalinos and Ahmed S. Elwakil

J. Low Power Electron. Appl. 2023, 13(1), 13; https://doi.org/10.3390/jlpea13010013 - 2 Feb 2023

Cited by 9 | Viewed by 2863

Abstract

A generalized structure for implementing fractional-order controllers is introduced in this paper. This is achieved thanks to the consideration of the controller transfer function as a ratio of integer and non-integer impedances. The non-integer order impedance is implemented using RC networks, such as [...] Read more.

A generalized structure for implementing fractional-order controllers is introduced in this paper. This is achieved thanks to the consideration of the controller transfer function as a ratio of integer and non-integer impedances. The non-integer order impedance is implemented using RC networks, such as the Foster and Cauer networks. The main offered benefit, with regards to the corresponding convectional implementations, is the reduced active and, also, passive component count. To demonstrate the versatility of the proposed concept, a controller suitable for implementing a cardiac pacemaker control system is designed. The evaluation of the performance of the system is performed through circuit simulation results, using a second-generation voltage conveyor as the active element. Full article

(This article belongs to the Special Issue Recent Advances on Design of Analog/Digital Circuits for Contemporary Applications)

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24 pages, 1884 KiB

Open AccessArticle

A Power-Efficient Neuromorphic Digital Implementation of Neural–Glial Interactions

by Angeliki Bicaku, Maria Sapounaki, Athanasios Kakarountas and Sotiris K. Tasoulis

J. Low Power Electron. Appl. 2023, 13(1), 10; https://doi.org/10.3390/jlpea13010010 - 18 Jan 2023

Cited by 4 | Viewed by 2746

Abstract

Throughout the last decades, neuromorphic circuits have incited the interest of scientists, as they are potentially a powerful tool for the treatment of neurological diseases. To this end, it is essential to consider the biological principles of the CNS and develop the appropriate [...] Read more.

Throughout the last decades, neuromorphic circuits have incited the interest of scientists, as they are potentially a powerful tool for the treatment of neurological diseases. To this end, it is essential to consider the biological principles of the CNS and develop the appropriate area- and power-efficient circuits. Motivated by studies that outline the indispensable role of astrocytes in the dynamic regulation of synaptic transmission and their active contribution to neural information processing in the CNS, in this work we propose a digital implementation of neuron–astrocyte bidirectional interactions. In order to describe the neuronal dynamics and the astrocytes’ calcium dynamics, a modified version of the original Izhikevich neuron model was combined with a linear approximation of the Postnov functional neural–glial interaction model. For the implementation of the neural–glial computation core, only three pipeline stages and a 10.10 fixed point representation were utilized. Regarding the results obtained from the FPGA implementation and the comparisons to other works, the proposed neural–glial circuit reported significant savings in area requirements (from 22.53% up to 164.20%) along with considerable savings in total power consumption of 28.07% without sacrificing output computation accuracy. Finally, an RMSE analysis was conducted, confirming that this particular implementation produces more accurate results compared to previous studies. Full article

(This article belongs to the Special Issue Recent Advances on Design of Analog/Digital Circuits for Contemporary Applications)

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24 pages, 36314 KiB

Open AccessArticle

FPGA-Based Decision Support System for ECG Analysis

by Agostino Giorgio, Cataldo Guaragnella and Maria Rizzi

J. Low Power Electron. Appl. 2023, 13(1), 6; https://doi.org/10.3390/jlpea13010006 - 7 Jan 2023

Cited by 11 | Viewed by 4525

Abstract

The high mortality rate associated with cardiac abnormalities highlights the need of accurately detecting heart disorders in the early stage so to avoid severe health consequence for patients. Health trackers have become popular in the form of wearable devices. They are aimed to [...] Read more.

The high mortality rate associated with cardiac abnormalities highlights the need of accurately detecting heart disorders in the early stage so to avoid severe health consequence for patients. Health trackers have become popular in the form of wearable devices. They are aimed to perform cardiac monitoring outside of medical clinics during peoples’ daily lives. Our paper proposes a new diagnostic algorithm and its implementation adopting a FPGA-based design. The conceived system automatically detects the most common arrhythmias and is also able to evaluate QT-segment lengthening and pulmonary embolism risk often caused by myocarditis. Debug and simulations have been carried out firstly in Matlab environment and then in Quartus IDE by Intel. The hardware implementation of the embedded system and the test for the functional accuracy verification have been performed adopting the DE1_SoC development board by Terasic, which is equipped with the Cyclone V 5CSEMA5F31C6 FPGA by Intel. Properly modified real ECG signals corrupted by a mixture of muscle noise, electrode movement artifacts, and baseline wander are used as a test bench. A value of 99.20% accuracy is achieved by taking into account 0.02 mV for the root mean square value of noise voltage. The implemented low-power circuit is suitable as a wearable decision support device. Full article

(This article belongs to the Special Issue Recent Advances on Design of Analog/Digital Circuits for Contemporary Applications)

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10 pages, 5491 KiB

Open AccessArticle

Simple Technique to Improve Essentially the Performance of One-Stage Op-Amps in Deep Submicrometer CMOS Technologies

by Jaime Ramirez-Angulo, Alejandra Diaz-Armendariz, Jesus E. Molinar-Solis, Alejandro Diaz-Sanchez and Jesus Huerta-Chua

J. Low Power Electron. Appl. 2023, 13(1), 4; https://doi.org/10.3390/jlpea13010004 - 4 Jan 2023

Cited by 4 | Viewed by 2807

Abstract

A comparative study of one-stage-amp performance improvement based on simulations in 22 nm, 45 nm, 90 nm, and 180 nm in deep submicrometer CMOS technologies is discussed. Generic SPICE models were used to simulate the circuits. It is shown that in all cases [...] Read more.

A comparative study of one-stage-amp performance improvement based on simulations in 22 nm, 45 nm, 90 nm, and 180 nm in deep submicrometer CMOS technologies is discussed. Generic SPICE models were used to simulate the circuits. It is shown that in all cases a simple modification using resistive local common mode feedback increases open-loop gain and gain-bandwidth product, peak output currents, and slew rate by close to an order of magnitude. It is shown that this modification is especially appropriate for its utilization in current CMOS technologies since large factor improvements were not available in previous technologies. The OTAs with resistive local common mode feedback require simple phase lead compensation with a very small additional silicon area and keep supply requirements and static power dissipation unchanged. Full article

(This article belongs to the Special Issue Recent Advances on Design of Analog/Digital Circuits for Contemporary Applications)

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18 pages, 3918 KiB

Open AccessArticle

Tunnel Field-Effect Transistor: Impact of the Asymmetric and Symmetric Ambipolarity on Fault and Performance in Digital Circuits

by Chiara Elfi Spano, Fabrizio Mo, Roberta Antonina Claudino, Yuri Ardesi, Massimo Ruo Roch, Gianluca Piccinini and Marco Vacca

J. Low Power Electron. Appl. 2022, 12(4), 58; https://doi.org/10.3390/jlpea12040058 - 31 Oct 2022

Cited by 1 | Viewed by 2796

Abstract

Tunnel Field-Effect Transistors (TFETs) have been considered one of the most promising technologies to complement or replace CMOS for ultra-low-power applications, thanks to their subthreshold slope below the well-known limit of 60 mV/dec at room temperature holding for the MOSFET technologies. Nevertheless, TFET [...] Read more.

Tunnel Field-Effect Transistors (TFETs) have been considered one of the most promising technologies to complement or replace CMOS for ultra-low-power applications, thanks to their subthreshold slope below the well-known limit of 60 mV/dec at room temperature holding for the MOSFET technologies. Nevertheless, TFET technology still suffers of ambipolar conduction, limiting its applicability in digital systems. In this work, we analyze through SPICE simulations, the impact of the symmetric and asymmetric ambipolarity in failure and power consumption for TFET-based complementary logic circuits. Our results clarify the circuit-level effects induced by the ambipolarity feature, demonstrating that it affects the correct functioning of logic gates and strongly impacts power consumption. We believe that our outcomes motivate further research towards technological solutions for ambipolarity suppression in TFET technology for near-future ultra-low-power applications. Full article

(This article belongs to the Special Issue Recent Advances on Design of Analog/Digital Circuits for Contemporary Applications)

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