Search Results (21)

Researching cosmic dust requires terrestrial facilities for accelerating analogues of different sizes and masses. To address the area of very lightweight particles, electrostatic accelerators like Van de Graaf accelerators or Linear Accelerators (LINACs) have proven adequate. This article describes the components, dimensions, working principle and attributes of a variable frequency switched 6-stage LINAC of 120 kilovolts (kV) potential based at the Institute of Space Systems, University of Stuttgart. It utilizes negative voltages, no storage capacitors, isometric drift tubes, one semiconductor-based high-voltage switch per stage and there is no voltage drop during acceleration. The particle rate can reach up to 33 particles per second. By setting a target speed window, it autonomously chooses the right number of acceleration stages to meet that requirement, if possible. Micron-sized iron particles were accelerated successfully, achieving speed increase rates of up to three times the pre-LINAC speed and a total speed of up to 1300 m per second (m/s). This platform provides a new tool for dust sensor calibration, impact physics and material surface processing due to its ability to bring particles of different charge-to-mass ratios to a defined target speed. Full article

Capacitive-coupling non-contact voltage sensors face a key challenge: their probe-conductor coupling capacitance varies, making it hard to accurately determine the division ratio. This capacitance is influenced by factors like the conductor’s insulation material, radius, and relative position. To address this challenge, this paper proposes a sensor gain self-calibration method based on switching capacitors. This method obtains multiple sets of real-time measurement outputs by connecting and switching different standard capacitors in parallel with the sensor’s structural capacitance, and then simultaneously solves for the coupling capacitance and the voltage under test, thereby achieving on-site autonomous calibration of the sensor gain. To effectively suppress interference from stray electric fields in the surrounding space, a shielded coaxial probe structure and corresponding back-end processing circuitry were designed, significantly enhancing the system’s anti-interference capability. Finally, an experimental platform incorporating insulated conductors of various diameters was built to validate the method’s effectiveness. Within the 100–300 V power-frequency range, the reconstructed voltage amplitude shows a maximum relative error of 1.06% and a maximum phase error of 0.76°, and harmonics are measurable up to the 50th order. Under inter-phase electric field interference, the maximum relative error of the reconstructed voltage amplitude is 1.34%, demonstrating significant shielding effectiveness. For conductors with diameters ranging from 6 mm² to 35 mm², the measurement error is controlled within 1.57%. These results confirm the method’s strong environmental adaptability and broad applicability across different conductor diameters. Full article

Embedded differential temperature sensors can be utilized to monitor the power consumption of circuits, taking advantage of the inherent on-chip electrothermal coupling. Potential applications range from hardware security to linearity, gain/bandwidth calibration, defect-oriented testing, and compensation for circuit aging effects. This paper introduces the use of on-chip differential temperature sensors as part of a wireless Internet of Things system. A new low-power differential temperature sensor circuit with chopped cascode transistors and switched-capacitor integration is described. This design approach leverages chopper stabilization in combination with a switched-capacitor integrator that acts as a low-pass filter such that the circuit provides offset and low-frequency noise mitigation. Simulation results of the proposed differential temperature sensor in a 65 nm complementary metal-oxide-semiconductor (CMOS) process show a sensitivity of $33.18\mathrm{V}{/}^{°}\mathrm{C}$ within a linear range of $\pm 36.5{\mathrm{m}}^{°}\mathrm{C}$ and an integrated output noise of $0.862{\mathrm{mV}}_{\mathrm{rms}}$ (from 1 to 441.7 Hz) with an overall power consumption of $0.187\mathrm{mW}$. Considering a figure of merit that involves sensitivity, linear range, noise, and power, the new temperature sensor topology demonstrates a significant improvement compared to state-of-the-art differential temperature sensors for on-chip monitoring of power dissipation. Full article

This paper presents an implementation of a 14-bit 2.5 MS/s differential Successive-Approximation-Register (SAR) analog-to-digital converter (ADC) to be used for sensing multiple analog input signals. A differential binary-weighted with split capacitance charge-redistribution capacitive digital-to-analog converter (CDAC) utilizing the conventional switching technique is designed, without using any calibration mechanism for fast power-on operation. The CDAC capacitor unit has been optimized for improved linearity without calibration technique. The SAR ADC has a differential input range 3.6 V_pp, with a SNDR of 80.45 dB, ENOB of 13.07, SFDR of 87.16 dB and dissipates an average power of 0.8 mW, while operating at 2.5 V/1 V for analog/digital power supply. The INL and DNL is +0.22/−0.34 LSB and +0.42/−0.3 LSB, respectively. A prototype ADC has been fabricated in a conventional CMOS 65 nm technology process. Full article

This study proposes self-calibration of capacitor mismatch errors for high-resolution pipeline analog-to-digital converters (ADCs). The proposed calibration circuit recursively amplifies the capacitor mismatch error by re-utilizing a multiplying digital-to-analog converter in a pipeline stage without increasing the circuit complexity, and the amplified error voltage is converted into digital code by utilizing the remaining pipeline stages. Error correction is performed by subtracting the digital code from the ADC output during normal operation. A prototype of a 12-bit pipeline ADC is fabricated in a 0.18 µm standard CMOS process. The ADC comprises eight 1.5-bit stages, followed by a 4-bit flash ADC as the final stage; the capacitor mismatch errors in the first two pipeline stages are corrected by utilizing the proposed self-calibration technique. Although the calibration method is employed in a 1.5-bit stage architecture, which uses a gain-of-two switched-capacitor amplifier, it is applicable to different bit-per-stage architectures. The ADC linearity significantly improves after calibration, and this is verified through simulations and measurements. Full article

This paper presents a 52-to-57 GHz CMOS quadrature voltage-controlled oscillator (QVCO) with a novel I/Q phase tuning technique based on a body bias control method. The QVCO employs an in-phase injection-coupling (IPIC) network comprising four diode-connected FETs for the quadrature phase generation. The I/Q phase error is calibrated by controlling the body bias voltage offset of the QVCO’s four core FETs. This technique effectively covers a wide range of I/Q phase error between −13.4° and +10.7°. It also minimally induces the unwanted variations in the phase noise, current dissipation, and oscillation frequency, which were found to be only 0.4 dB, 0.07%, and 36 MHz, respectively. After the IPIC-QVCO, a phase-tunable two-stage LO buffer employing a 3-bit switched-capacitor bank was added for additional phase tuning, leading to the extension of the phase tuning range up to −22.7–+20.0°. The proposed QVCO is implemented in a 40 nm RF CMOS process. The measured results show that the QVCO covers a frequency band from 52.4 to 57.6 GHz while consuming 26.2 mW. The phase noise and the figure-of-merit of the QVCO are −91.8 dBc/Hz at 1 MHz offset and −172.4 dBc/Hz, respectively. We also realized a fully integrated 55 GHz quadrature RF transmitter employing the phase-tunable QVCO and LO generator. The effectiveness of the proposed phase-tunable LO generator was confirmed by verifying the image rejection ratio (IRR) calibration at the RF output. Full article

This paper proposes a one-dimensional (1D) maximum power point tracking (MPPT) design which only requires measurement of one parameter (the input voltage of a switched-capacitor charge pump) for calibrating a power converter including the charge pump and thermoelectric generator. The frequency of the clock to drive the charge pump is designed to minimize the circuit area of the entire charge pump circuit for generating a target output current at a specific output voltage. The ratio of the capacitance value of each boosting capacitor (C) to the size of the switching MOSFET can be determined to maximize the transferring current at the same time. When a thermoelectric generator (TEG) is given, its output impedance is determined. Its open-circuit voltage varies with the temperature difference between two plates of the TEG. MPPT maximizes the output power of the charge pump even when the temperature difference varies. It was indicated that the number of stages of charge pump (N) needs to increase when the temperature difference lowers, whereas C needs to decrease inversely proportional to N, meaning that the C–N product should be kept unchanged for MPPT. Demonstration of the circuit design was conducted in 65 nm CMOS, and the measured results validated the concept of the 1D MPPT. Full article

In a routine optical remote sensor, there is a contradiction between the two requirements of high radiation sensitivity and high dynamic range. Such a problem can be solved by adopting pixel-level adaptive-gain technology, which is carried out by integrating multilevel integrating capacitors into photodetector pixels and multiple nondestructive read-outs of the target charge with a single exposure. There are four gains for any one pixel: high gain (HG), medium gain (MG), low gain (LG), and ultralow gain (ULG). This study analyzes the requirements for laboratory radiometric calibration, and we designed a laboratory calibration scheme for the distinctive imaging method of pixel-level adaptive gain. We obtained calibration coefficients for general application using one gain output, and the switching points of dynamic range and the proportional conversion relationship between adjacent gains as the adaptive-gain output. With these results, on-orbit quantification applications of spectrometers adopting pixel-level automatic gain adaptation technology are guaranteed. Full article

Drift-time ion mobility spectrometer (DT-IMS) is a promising technology for gas detection and analysis in the form of miniaturized instrument. Analytes may exist in the form of positively or negatively charged ions according to their chemical composition and ionization condition, and therefore require both polarity of electric field for the detection. In this work the polarity switching of a drift-time ion mobility spectrometer based on a direct current (DC) corona discharge ionization source was investigated, with novel solutions for both the control of ion shutter and the stabilization of aperture grid. The drift field is established by employing a switchable high voltage power supply and a serial of voltage regulator diode, with optocouplers to drive the ion shutter when the polarity is switched. The potential of aperture grid is stabilized during the polarity switching by the use of four diodes to avoid unnecessary charging cycle of the aperture grid capacitor. Based on the proposed techniques, the developed DT-IMS with 50 mm drift path is able to switch its polarity in 10 ms and acquire mobility spectrum after 10 ms of stabilization. Coupled with a thermal desorption sampler, limit of detection (LoD) of 0.1 ng was achieved for ketamine and TNT. Extra benefits include single calibration substance for both polarities and largely simplified pneumatic design, together with the reduction of second drift tube and its accessories. This work paved the way towards further miniaturization of DT-IMS without compromise of performance. Full article

This paper presents a 12-b successive approximation register (SAR) analog-to-digital converter (ADC) for biopotential sensing applications. To reduce the digital-to-analog converter (DAC) switching energy of the high-resolution ADC, we combine merged-capacitor-switching (MCS) and detect-and-skip (DAS) methods, successfully embedded in the subranging structure. The proposed method saves 96.7% of switching energy compared to the conventional method. Without an extra burden on the realization of the calibration circuit, we achieve mismatch calibration by reusing the on-chip DAC. The mismatch data are processed in the digital domain to compensate for the nonlinearity caused by the DAC mismatch. The ADC is realized using a 0.18 μm CMOS process with a core area of 0.7 mm². At the sampling rate f_S = 9 kS/s, the ADC achieves a signal-to-noise ratio and distortion (SINAD) of 67.4 dB. The proposed calibration technique improves the spurious-free dynamic range (SFDR) by 7.2 dB, resulting in 73.5 dB. At an increased f_S = 200 kS/s, the ADC achieves a SINAD of 65.9 dB and an SFDR of 68.8 dB with a figure-of-merit (FoM) of 13.2 fJ/conversion-step. Full article

This paper presents a flash frequency tuning technique for switched-capacitor-based, voltage-controlled oscillators operating at mm wave frequencies. The proposed strategy exploits a capacitor array and a small varactor for coarse and fine tuning, respectively, which are simultaneously operated thanks to a flash A/D-based control circuit. This avoids additional delay in the frequency calibration, thus enabling very fast-frequency locking operation. The VCO was fabricated in a 28 nm FD-SOI CMOS technology and provides an oscillation frequency around 39 GHz with an overall tuning range of 3.3 GHz. The circuit dissipates 8.4 mW from a power supply as low as 0.7 V, while occupying a silicon area of 210 µm × 150 µm. Full article

This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm${}^2$. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step. Full article

This paper presents a switched capacitive reference driver (SCRD) with a low-energy switching scheme. In order to reduce the performance degradation resulting from a signal-dependent voltage drop in a capacitive reference driver (CRD) without increasing the capacitance (C_REF) of a CRD, the proposed SCRD utilizes the CRD for LSB conversion cycles. In MSB conversion cycles, a supply voltage is used as a reference voltage to save on area and power consumption. As such, the proposed SCRD significantly relaxes the required C_REF, and does not necessitate bit weight calibration or compensation requiring an auxiliary capacitor-based digital-to-analog converter (CDAC). To evaluate the proposed SCRD, a prototype 12-bit 40-MS/s SAR ADC is fabricated in a 65 nm CMOS process. With near Nyquist frequency, the measured spurious-free dynamic range (SFDR) of the SAR ADC with the SCRD is 80.6 dB, which is about a 16 dB improvement from the SFDR of a SAR ADC with a CRD only. Full article

This paper proposed a digital background calibration algorithm with positive and negative symmetry error tolerance to remedy the capacitor mismatch for successive approximation register analog-to-digital converters (SAR ADCs). Compensate for the errors caused by capacitor mismatches and improve the ADC performance. Combination with a tri-level switching scheme based on the common-mode voltage V_cm to achieve capacitor reduction and high switching energy efficiency. The proposed calibration algorithm significantly improves capacitor mismatch without resorting to extensive computation or dedicated circuits. The active area is 0.046 mm² in 40 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The post-simulation results show the effective number of bits (ENOB) improves from 8.23 bits to 11.36 bits, signal-to-noise-and distortion ratio (SNDR) improves from 51.33 dB to 70.15 dB, respectively, before and after calibration. This improves the spurious-free dynamic range (SFDR) by 24.13 dB, from 61.50 dB up to 85.63 dB. The whole ADC’s power consumption is only 0.3564 mW at sampling rate f_s =2 MS/s and Nyquist input frequency, with a figure-of-merit (FOM) 67.8 fJ/conv.-step. Full article

A low-power column-parallel gain-adaptive single-slope analog-to-digital converter (ADC) for CMOS image sensors is proposed. The gain-adaptive function is realized with the proposed switched-capacitor based gain control structure in which only minor changes from the traditional single-slope ADC are required. A switched-capacitor controlled dynamic bias comparator and a flip-reduced up/down double-data-rate (DDR) counter are proposed to reduce the power consumption of the column circuits. A 12-bit current steering digital-to-analog converter (DAC) with a two-dimensional gradient error tolerant switching scheme is adopted in the ramp generator to improve the linearity of the ADC. The proposed techniques were experimentally verified in a prototype chip fabricated in the TSMC 180 nm CMOS process. A single-column ADC consumes a total power of 63.2 $\mathsf{\mu }$ W and occupies an area of 4.48 $\mathsf{\mu }$ m × 310 $\mathsf{\mu }$ m. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the ADC are −0.43/+0.46 least significant bit (LSB) and −0.84/+1.95 LSB. A 13-bit linear output is acquired in nonlinearity within 0.08% of the full scale after calibration. Full article