A 12-b Subranging SAR ADC Using Detect-and-Skip Switching and Mismatch Calibration for Biopotential Sensing Applications

This paper presents a 12-b successive approximation register (SAR) analog-to-digital converter (ADC) for biopotential sensing applications. To reduce the digital-to-analog converter (DAC) switching energy of the high-resolution ADC, we combine merged-capacitor-switching (MCS) and detect-and-skip (DAS) methods, successfully embedded in the subranging structure. The proposed method saves 96.7% of switching energy compared to the conventional method. Without an extra burden on the realization of the calibration circuit, we achieve mismatch calibration by reusing the on-chip DAC. The mismatch data are processed in the digital domain to compensate for the nonlinearity caused by the DAC mismatch. The ADC is realized using a 0.18 μm CMOS process with a core area of 0.7 mm2. At the sampling rate fS = 9 kS/s, the ADC achieves a signal-to-noise ratio and distortion (SINAD) of 67.4 dB. The proposed calibration technique improves the spurious-free dynamic range (SFDR) by 7.2 dB, resulting in 73.5 dB. At an increased fS = 200 kS/s, the ADC achieves a SINAD of 65.9 dB and an SFDR of 68.8 dB with a figure-of-merit (FoM) of 13.2 fJ/conversion-step.


Introduction
Portable biomedical sensing applications demand low-power consumption for long battery operation. The human biopotentials have low-frequency bandwidth, up to a few kHz [1]. The amplitude of an electrocardiogram (ECG) is around 1 mV. An electroencephalogram (EEG) has an amplitude from 10 to 100 µV over a frequency band from 0.5 Hz to 150 Hz. The local field potential (LFP) has a typical amplitude of 1 mV over 1 Hz to 200 Hz. The biopotentials are low-amplitude signals, which must be amplified before signal processing. The next important block for signal processing will be the analog-to-digital converter (ADC). Thus, the performance of the amplifier and ADC determines the quality of the measured biopotentials. For digitizing the amplified signal, successive approximation register (SAR) ADC is suitable, with its energy-efficient structure for medium resolution. Moreover, the scaling-friendly structure of the SAR ADC has drawn continued research interest [2]. The basic building blocks of the SAR ADC include a comparator, a digitalto-analog converter (DAC), and SAR logic. The power consumption of the SAR logic, which is mostly digital, can be reduced by lowering the supply voltage. The comparator power can be reduced using a dynamic structure. Thus, researchers have investigated various energy-efficient DAC switching methods-for example, split-DAC [3], monotonic switching [4], set and down [5], and energy saving [6]. The work in [7] introduces a merged-capacitor-switching (MCS) method. In this approach, DAC capacitors are switched from the common-mode (CM) voltage V CM to ground or reference voltage V REF . This method not only saves switching energy but also effectively handles the issues related to Figure 1a shows the proposed subranging ADC. It includes a 7-bit coarse SAR ADC, a 12-bit fine SAR ADC, a DAS controller, a calibration (CAL) logic, and an output buffer. The coarse ADC includes the DAC consisting of seven binary-weighted capacitors C Ck (k = 1 to 7). The fine ADC includes the DAC designed with twelve binary-weighted capacitors. For mismatch calibration, we divide the DAC into a 7-bit MSB segment of capacitors C i (i = 6 to 12) and a 5-bit LSB segment of capacitor C j (j = 1 to 5). MCS is used for coarse and fine ADCs to save DAC switching energy. The analog input is sampled into the two ADCs at the same time. Top-plate sampling is performed using a bootstrapped switch operating with 1.8 V [9]. After sampling the input, the coarse ADC sequentially generates 7-bit output D OUT,C [12:6]. Then, the DAS controller and fine ADC are enabled by the signal CDONE (coarse done). The DAS controller decodes D OUT,C [12:6], and sets the switches for C i (i = 6 to 12) of the fine ADC. This operation generates the residue in the fine DAC. Then, the SAR logic of the fine ADC sequentially determines the switch states of the remaining C j (j = 1 to 5) to generate D OUT,F [5:1]. The D OUT,C [12:6] and D OUT,F [5:1] are combined in the output buffer to generate the ADC output D OUT [12:1] with the end-of-conversion (EOC) signal. Figure 1b shows the timing sequence for the subranging ADC, which consists of calibration and conversion modes. The calibration mode includes three steps: reset, mismatch measurement, and data loading. When the reset signal becomes high, calibration mode starts with the calibration-enabled signal CAL. In this mode, the DAC inputs are disconnected from the analog input. During this time, the calibration code D CAL [6:1] for C i (i = 6 to 12) is generated and loaded two times (positive and negative DAC). Two bootstrap switches are used to set the bottom plate of the DAC capacitor to V CM . These switches are controlled by the output CAL p,n of the CAL logic at the beginning of each calibration cycle. The data loading occurs at the falling edge of EOC_CAL (end of calibration), which captures D CAL [6:1]. After finishing the calibration, the ADC enters conversion mode. Figure 2 shows the timing sequence of the ADC in conversion mode. It shows the internal DAC control signals, V C [k] (k = 1 to 7) for the coarse ADC, V F [i] (i = 6 to 12) for the MSB segment of the fine ADC, and V F [j] (j = 1 to 5, 6ex) for the LSB segment of the fine ADC. V F [6ex] is the control signal for C 6ex , which is an additional capacitor for mismatch calibration. The input signal is sampled into the coarse and fine ADCs by the sampling clock CLKS. All  The input CM voltage is constant during MCS. In the previous work [4,9], the comparator is implemented with a PMOS differential pair because this comparator is designed for monotonic switching. When the previous comparator is used for MCS, it can result in a relatively large offset at the input of the comparator. In this work, we use a comparator having complementary input stages, which allows rail-to-rail range and reduces the kickback noise [14]. Figure 3a shows an example waveform of the DAC when D OUT [9:6] = 0101 is generated using MCS. Figure 3b shows the waveform when MCS and DAS are combined. The two methods generate the same residue for V DAC,p and V DAC,n ; however, MCS can waste energy by performing unnecessary switching. By combining MCS and DAS, unnecessary switching can be avoided. The DAS controller decides which capacitor can be skipped for switching. Using D OUT,C [12:6] from the coarse ADC, the DAS operation can be summarized as follows: Where MSB = 12 and k is the binary capacitor index of the coarse ADC. We note that the MCS and DAS method is more effective for a relatively smaller input since most switching can be skipped. Because the mismatch effect of the skipped capacitors is also removed, DAS can provide the additional benefit of improved linearity. Figure 4 shows the schematic of the DAS controller. When CDONE is enabled, the output D OUT,C [12:6] is input to the DAS control switch through the logic gates. In the beginning,

Merged Capacitor Switching with Detect and Skip
To evaluate the effectiveness of various switching methods, we compare the switching energy of a 12-bit ADC. The switching energy E Mono (i) of the ith capacitor in the monotonic switching can be expressed as where index i is from 1 to N = 12, C T is the total capacitance of each DAC branch, and b m is the binary bit value. The switching energy E MCS (i) of the ith capacitor in the MCS can be expressed as [15] E MCS (i) A detailed derivation of Equations (1) and (2) can be found in the Appendices A and B, respectively. In the subranging ADC, switching energy can be divided into MSB and LSB segments of the DAC. The switching energy of the MSB segment can be expressed as where C SW is the sum of switched capacitors. The switching energy of the LSB segment is calculated using 6-bit MCS. The total switching energy is obtained using Figure 5 compares the switching energy of a 12-bit ADC normalized using V REF and the unit capacitor C 1 . The split capacitor scheme saves 37.5% of energy on average compared with the conventional method [1]. The monotonic switching saves up to 81%. The energy is further reduced using the MCS to 87.5%. Finally, the average switching energy saved is up to 96.7% when combining MCS and DAS in the subranging ADC, which is 9.2% lower than the previous state-of-the-art [7]. This result neglects the energy of the 7-bit coarse ADC, which is relatively small compared to the energy of the 12-bit fine ADC. We note that the switching energy is a normalized value using V REF and C 1 , independent of the technology node. Relatively low power can still be achieved using the conventional method-for example, 0.084 µW for a 10-bit ADC [8] and 0.38 µW for a 12-bit ADC [16]. Because the SAR ADC is realized using mostly digital logic, except for the comparator, low power can be achieved using scaled-down CMOS technology; the works [8] and [16] are realized using 40 nm and 65 nm CMOS processes, respectively.  Figure 6a shows one example of a DAC configuration for reading out the mismatch of C i (i = 6 to 12), one of the 7-bit MSB segments of the DAC. The proposed calibration method reuses the 6-bit DAC to measure the weight error of C i . The 6-bit DAC consists of 5-bit LSB capacitors (C 1 to C 5 ) and one extra capacitor C 6ex . Assuming that the 6-bit DAC has sufficient intrinsic linearity, the mismatch of each C i is sequentially measured. The digital representation D CAL [6:1] of the mismatch is generated from the CAL logic. The positive DAC branch is evaluated first, and the negative DAC branch is calibrated next. During the positive DAC calibration, V DAC,n (negative input of the comparator) is connected to V CM .  Here, V C [i] is the control signal connected to the bottom plate of the DAC capacitor. In the sampling phase, V C [i] of all capacitors are connected to V CM . In the next cycle, the bottom plate of the upper group capacitors (C 12 to C i + 1 ) is connected to V CM , while the bottom plate of the lower group capacitors (C i−1 to C 6 ) is connected to the ground. The switching results in V DAC,p are

DAC Capacitor Mismatch Calibration
where w * i is the weight of C i with mismatch error. Without mismatch, V DAC,p will be equal to V CM . The mismatch causes V DAC,p to deviate from V CM , which is measured by the 6-bit DAC. The bit weight difference between C i and the sum of lower group capacitors (C i-1 to C 6 ), which is quantized by the 6-bit DAC, can be expressed as where w j is the ideal weight, b j is the binary value, and q j is the quantization error. The values of the LSB segment capacitors (C 6ex , C 5 , . . . , C 1 ) are assumed to be linear with w * j = w j (j = 1, . . . , 6). The C 6ex is added to provide sufficient coverage for weight extraction. The value of C 6ex is 16C U , which is small compared to the total capacitance C T = 2048C U of each DAC, where C U = C 1 is the unit capacitor of the DAC. To simplify the SAR logic, C 6ex can be activated only during the calibration mode while connected to V CM in the conversion mode; however, the addition of C 6ex causes the actual weight of each capacitor to deviate from the ideal binary weight. The DAC mismatch calibration is based on the idea that the addition of C 6ex does not significantly change the weight of each capacitor. To preserve the correct weight of each capacitor, we handle the issue using an alternative approach: (1) C 6ex is used in both calibration and conversion mode; in the conversion mode, C 6ex serves as a redundant capacitor to improve the ADC linearity; (2) mismatch calibration is designed by including the weight of C 6ex ; then, the total weight of the 12-bit DAC is increased from 2048 to 2064 (see Table 1).

Mismatch Error of DAC Capacitor
The V DAC,p and V DAC,n at the inputs of the comparator can be expressed as where V IN,p and V IN,n are the sampled input voltages at the positive and negative DAC, respectively. The b i is the binary value of the DAC capacitor in the MSB segment (C 12 , . . . , C 6 ), and b j is the value of capacitors in the LSB segment (C 6ex , C 5 , . . . , C 1 ). The Ω is the group of switched capacitors by the DAS controller. The w i is the ideal weight of ith capacitor in the MSB segment of the DAC, which is the ratio between C i and C T . The w j is the ideal weight of the jth capacitor in the LSB segment. The ∆w pi and ∆w ni are the weight errors of the ith capacitor in the positive and negative branches of the fine DAC, respectively. Table 1 shows the ideal weight of each capacitor. The second term of (7) and (8) is the amount of change caused by the mismatch of the MSB capacitors. The third term represents the change caused by the mismatch of the LSB capacitors. At the end of conversion, both V DAC,p and V DAC,n approach V CM as By multiplying 2 11 on both sides of (10), we obtain where W i = 2 12 w i , ∆W i = (∆W pi + ∆W ni )/2 is the average error of the positive and negative branch, ∆W pi = 2 12 (∆w pi ), W ni = 2 12 (∆w ni ), and W 0 = 2 11 (127/129) = 2016.248. At this moment, the weight error ∆W i is unknown, and the method of calculating ∆W i is presented in the next subsection.

Weight Error Extraction
We assume that the overall mismatch of the DAC is averaged out and normalize the full scale to one [17]. Then, the sum of weight for C 12 can be expressed as The calibration code d 12 for C 12 can be expressed as When we substitute (13) into (12), we obtain where w j is the weight of the capacitors in the 6-bit DAC. We note that ∆ 12 = (w 12 − w * 12 )∆ 12 = (w 12 -w * 12 ) is the weight error of C 12 and w 12 = (64/129) is the ideal weight of C 12 . Then, we obtain Similarly, the sum of weight for C 11 can be expressed as Using the calibration code d 11 for C 11 , we obtain Noting that ∆ 11 = (w 11 -w * 11 ) ∆ 11 = (w 11 − w * 11 ) is the weight error of C 11 , where w 11 = (32/129) is the ideal weight, we obtain Similarly, we obtain the remaining weights. For example, the weight error ∆ 6 of C 6 can be expressed as The digital representation of sampled input V IN,p can be expressed as D IN,p = 2 12 (V IN,p /V REF ). Then, the result (10) can be rearranged as The first two terms of (20) represent the contribution of the MSB segment of the DAC, which can be positive or negative. The third term is the contribution of the LSB segment. The last term is the average output value. A similar definition can be proposed for D IN,n = 2 12 Figure 8 shows the floor plan of the coarse DAC. We use a common-centroid layout to reduce the capacitor mismatch. Because capacitors need to be connected to the outside of the DAC, the metal route increases the coupling with neighboring capacitors. The effect of additional coupling is usually more sensitive to small capacitors. We reduce the effect by placing the capacitors of the LSB segment close to the edge of the DAC. Dummy capacitors are added around the DAC periphery to reduce the mismatch caused by the edge effect. A similar technique is used for the fine DAC. We use a behavioral model to investigate the ADC performance depending on the mismatch. Monte Carlo simulations with 1000 samples are performed using the DAC capacitor mismatch rate of 1.0%, 1.5%, 2.0%, and 2.5%. Figure 9 compares the effective number of bits (ENOB) probability distribution before and after calibration. Before calibration, the average ENOB decreases from 11.1 bits to 10.2 bits when the mismatch increases from 0.5% to 2%. In the case of a 1% mismatch, the average ENOB increases from 10.8 bits to 11.2 bits after calibration. The standard deviation is reduced from 0.44 bit to 0.15 bit. In the case of a 1.5% mismatch, the average ENOB improves from 10.5 bits to 11.3 bits. The result shows that calibration effectively handles ENOB degradation with the mismatch rate. The minimum capacitor value allowed by the process is 21.2 fF (4 × 4 µm 2 ). Based on the process datasheet, the unit capacitor in the coarse DAC is designed to be larger than the minimum value to achieve a 1% mismatch rate, which is 54 fF (6.72 × 6.72 µm 2 ). Figure 10 shows the power breakdown of the ADC. Overall power including output buffer is 5.08 µW at f S = 200 kS/s. The breakdown shows that the SAR logic of fine ADC, the DAS controller, and the SAR logic of coarse ADC consume 39.5%, 18.9%, and 16.7% of the overall power, respectively.   Figure 11 shows a microphotograph of the ADC fabricated in a 0.18 µm CMOS process. The core area is 0.7 mm 2 . The coarse ADC occupies 8.5% of the overall area. The IC is mounted on a test board using the chip-on-board (COB) technique. Biopotentials typically exhibit signal frequencies less than 1 kHz. In this measurement, we choose an input frequency f IN = 1.12k kHz.  Figure 12 shows the comparison of the measured output spectra of the ADC before and after calibration. A differential sinusoidal signal with 0.9 V amplitude is applied for dynamic performance testing. The measured data are obtained from the fast Fourier transform (FFT) spectrum with 32768 points. After calibration, SINAD and SFDR are improved by 5.04 dB and 7.21 dB, respectively, resulting in an ENOB of 10.9 bits. The third harmonic located at 3f IN , which is related to the nonlinearity of the ADC, is reduced from −66.3 dB to −77.2 dB. Figure 13 shows the output spectrum using a near-Nyquist input frequency and the sampling rate f S = 9 kS/s. The SINAD and SFDR are improved by 5.44 dB and 2.94 dB, respectively, resulting in an ENOB of 10.5 bits.   Figure 15 shows the measured SFDR and SINAD as a function of f IN . The effective resolution bandwidth (ERBW) is the input frequency where the SINAD drops by 3 dB (1/2 LSB or 0.5 bit) from its value for low-frequency input. The result shows that ERBW is around 100 kHz, approximately half of the sampling frequency (Nyquist frequency).     Table 2 shows the comparison with the previous works. The work in [8] presents a subranging SAR ADC using the DAS method. They use split capacitor switching, which consumes more energy than MCS. A similar observation can be made for the work in [16], which uses the swap-to-reset DAC switching method. The low power consumption can be attributed to the scaled-down technology, 65 nm CMOS [16] and 40 nm CMOS [8,18]. When we compare the ADC realized using a similar CMOS process [2,19], our work achieves a better Walden's figure-of-merit (FOM W ) of 13.2 fJ/conv.-step and Schreier's figure-of-merit (FOM S ) of 170.4 dB. The work in [11] presents a 13-bit SAR ADC with on-chip calibration realized in a relatively large area (0.9 mm 2 ) using a 0.13 µm CMOS process. Our work realizes the subranging ADC, consisting of coarse and fine ADC, in 0.7 mm 2 using a 0.18 µm CMOS process. The work in [20] presents good dynamic performance; however, it consumes relatively high power, leading to an FoM S of 114.5 dB. The footnote shows the relationship between ENOB and SINAD. This equation does not explicitly consider the process gain related to the FFT. We can estimate the process gain using G FFT = 10·log(N F /2), where N F is the number of points processed in the FFT. Each nth FFT bin can be considered as the output from a narrow bandpass filter with a center frequency at (nf S /N F ). A large number of samples improves the frequency resolution and decreases the amount of noise in the bin's passband. For an N F -point FFT, the average value of the noise contained in each frequency bin is reduced by G FFT below the root-mean-square (rms) value of the quantization noise.

Conclusions
We investigate a 12-bit subranging SAR ADC for low-power biopotential sensing applications. A new DAC switching method is proposed by combining the MCS and DAS methods, successfully embedded in the subranging structure. Analysis of the DAC switching energy shows that the proposed method saves 96.7% of switching energy compared to the conventional method. To handle the DAC mismatch, we implement digital domain calibration without the extra burden of an on-chip calibration circuit. A simple method of extracting the weight error is presented by reusing the 6-bit DAC. The mismatch data are successfully processed in the digital domain to compensate for the nonlinearity caused by the DAC mismatch. The proposed ADC fabricated in 0.18 µm CMOS demonstrates successful operation and performance improvement using the proposed calibration technique. At a sampling rate of 200 kS/s, the ADC achieves SINAD of 65.9 dB and SFDR of 68.8 dB, with an FoM of 13.2 fJ/conversion-step. The contributions of this paper can be summarized as follows: (1) this work proposes an energy-efficient DAC switching method by combining MCS and DAS, (2) the proposed switching method is successfully implemented in a 12-bit subranging ADC, and (3) this work proposes a digital domain calibration using a normalized full-scale weight method. The result will be useful for realizing a low-power ADC for battery-powered, portable biomedical sensing applications.

Acknowledgments:
The chip fabrication and CAD tools were supported by the IDEC (IC Design Education Center).

Conflicts of Interest:
The authors declare no conflict of interest. Figure A1 shows the monotonic switching diagram for a 3-bit example (N = 3). After the sampling switches are turned off, the comparator directly performs the first comparison without switching any capacitor.

Appendix A. Monotonic Switching
where C N = 2C, C T = 4C is the total capacitance of each DAC branch, and C is the unit capacitance.
We can express the four cases using a single equation that describes the total capacitance connected to V REF as is the XOR of the current bit (b N ) and the previous bit (b N−1 ) value. The switching energy that V REF supplies to the DAC at the second cycle (φ 2 ) can be expressed as (3) After the third comparison, b N−2 is determined. The bottom plate of capacitor C N−2 is switched to the ground. The comparator input is reduced by an amount of (C N−2 /C T )V REF . There are eight switching cases, and we can express the cases using a single equation that describes the total capacitance connected to V REF as The switching energy that V REF supplies to the DAC at the third cycle (φ 3 ) can be expressed as By generalizing the above result for an N-bit ADC, we obtain Equation (1) of the main text. Figure A2 shows the merged capacitor switching diagram for a 3-bit example. After the sampling switches are turned off, the comparator directly performs the first comparison without switching any capacitor. Switching energy calculation is similar to monotonic switching, except that switching is performed from V CM rather than V REF .

Appendix B. Merged Capacitor Switching
(1) After the first comparison, the MSB bit b N is determined. The bottom plate of capacitor C N (positive DAC branch if b N = 1 or negative DAC branch if b N = 0) is switched from V CM to V REF . Then, one comparator input (V DAC,p if b N = 1 or V DAC,n if b N = 0) is increased by the amount of (C N /C T )(V REF /2). The opposite comparator input is reduced by the amount of (C N /C T )(V REF /2). The total capacitance connected to V REF is C N . The switching energy that V REF supplies to the DAC at the first cycle (φ 1 ) can be expressed as Similar equations can be derived for the remaining three cases. Then, we can express the four cases using a single equation, and the switching energy at φ 2 can be expressed as where the ± sign is replaced with (−1) b N−1 ⊕b N . Figure A2. Merged capacitor switching diagram for a 3-bit ADC.
(3) After the third comparison, b N−2 is determined. There are eight cases, and we can express the cases using a single equation. Then, the switching energy at φ 3 can be expressed as where the first ± sign in the second term is replaced with (−1) b N−2 ⊕b N , and the second ± sign is replaced with (−1) b N−2 ⊕b N−1 . By generalizing the above result, we obtain Equation (2) of the main text.