# Low Power SAR ADC Design with Digital Background Calibration Algorithm

^{*}

## Abstract

**:**

_{cm}to achieve capacitor reduction and high switching energy efficiency. The proposed calibration algorithm significantly improves capacitor mismatch without resorting to extensive computation or dedicated circuits. The active area is 0.046 mm

^{2}in 40 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The post-simulation results show the effective number of bits (ENOB) improves from 8.23 bits to 11.36 bits, signal-to-noise-and distortion ratio (SNDR) improves from 51.33 dB to 70.15 dB, respectively, before and after calibration. This improves the spurious-free dynamic range (SFDR) by 24.13 dB, from 61.50 dB up to 85.63 dB. The whole ADC’s power consumption is only 0.3564 mW at sampling rate f

_{s}=2 MS/s and Nyquist input frequency, with a figure-of-merit (FOM) 67.8 fJ/conv.-step.

## 1. Introduction

_{cm}with a tri-level switching method. Compare with the traditional structure, it only uses half of the unit capacitors. It can save a large proportion of switching energy consumption, the most significant bit (MSB) conversion without drawing any energy, and tri-level switch changing from common-mode voltage V

_{cm}to the reference voltage V

_{ref}or physical ground GND in every bit of the decision subsequently. Adopt a digital background calibration with redundancy capacitor array to minimize capacitor mismatch. Improve the ADC’s static performance, such as differential nonlinearity (DNL) and integral nonlinearity (INL). The digital calibration method can make sure it is high speed and does not impact original circuits, and it is compatible with device scaling.

_{cm}with the tri-level switching method. Section 3 shows the digital calibration theory and implementation method. Section 4 displays the simulation results of ADC performance. Finally, a brief conclusion is presented in Section 5.

## 2. ADC Architecture

_{Rd}(C

_{Rd}= C

_{u}) adds to the capacitor arrays for signal sampling completeness. The unit capacitor C

_{Rd}participates in the sampling process and does not participate in the quantization process. The total number of unit capacitors of the full differential N-bit charge redistribution SAR ADC is 2

^{N}*C

_{u}; Figure 1 depicts the structure of binary-weighted error compensation SAR ADC where it inserts three compensative capacitors array C

_{2C}, C

_{5C}, and C

_{8C}, and the weight equal with C

_{2}, C

_{5}, and C

_{8}, respectively. The digital error correction logic circuit is generated by the design compiler to execute the error compensation. The DAC switching method saves a large proportion of switching energy and half of the capacitors than the conventional structure. When the ADC system starts to work, the two capacitor arrays’ bottom plates start sampling the input signal. Then, the full differential dynamic comparator starts the first comparison.

#### 2.1. Switching Method

_{cm}to reference voltage V

_{ref}or physical ground GND in every bit of conversion. Moreover, the most significant bit (MSB) can determine without any switching energy consumption; V

_{cm}based tri-level switching method example, as shown in Figure 2 with 3 bits conversion. The stepping size is directly proportional to the capacitor array’s sizing during the binary search with this method. The input signal compares with (±2/4) V

_{ref}according to the first comparison, switch turning up or down, connect with the reference voltage V

_{ref}or physical ground GND in the DAC. For 12-bit SAR ADC, V

_{cm}based tri-level switch structure produces switching energy consumption of 681.83 CV

^{2}

_{ref}, saving 87.51% of changing energy consumption than the traditional DAC switch structure.

#### 2.2. SAR Control Logic

_{cm}architecture with a tri-level switching method; Besides, since the shift register ring counter and SAR control logic is iterative, it is easily extended to higher resolutions by just extending the shift registers, using this similar method, assign different clock period to an individual bit decision step is possibly and easily. Figure 3 shows the schematic of the SAR control logic and its timing diagram. CLK14 to CLK0 load the digital output codes from the comparator to the output register. After that, the digital output code feedback as control signals for the tri-level switches of lower capacitor array to accomplish the switching procedure. The digital calibration circuit performs 15b redundancy code to 12 b digital output code conversion simultaneously.

## 3. Calibration Implementation

#### 3.1. Capacitor Mismatch

#### 3.2. Calibration Theory

_{i}’s and B

_{ic}’s) and the actual decision values (D

_{out}’s) are a function of actual capacitor values as given in Equation (1). The swing of input signal shrink with a factor of ɑ due to the redundancy capacitors, α can calculate with Equation (2), in this design, α is equal to 0.876, so the peak-to-peak of the input signal equal to reference voltage multiply the factor α, which is approximate 1.05 V. Overflow occurs when the signal swing is over the range, the digital output codes will be a settlement to the value from 0 to 4095 to keep the function normal and prevent data from spilling up or down. Figure 5 shows an example of the digital background calibration process.

_{cm}based tri-level switching method, as shown in Figure 2. In the binary-weighted search method, the stepping size is equal to the corresponding capacitor array proportion in the overall capacitor array. Around each decision level, the stepping sizes and the error-tolerance windows are symmetric. Combine the redundant capacitors array digital background calibration algorithm with the tri-level switching method. The complexity of circuit design is reduced, but also achieves symmetric error tolerance windows with ±292 LSB.

## 4. Simulation Results

^{2}. The whole test chip micrograph, as shown in Figure 12.

## 5. Conclusions

_{cm}based switching method and redundancy capacitors to correct the decision errors due to incomplete setting and capacitor arrays mismatch. Applied to a 12-bit full differential SAR ADC, the test chip implemented in standard 40 nm CMOS technology, at Nyquist full-scale sine wave input and 2 MSPs sampling rate reached SNDR 70.15 dB, SFDR up to 85.63 dB, ENOB is 11.36 bits. DNL and INL are +0.7/−0.6 LSB and +1.2/−1.1 LSB, respectively.

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

## References

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**Figure 1.**The architecture of 12-bit full differential successive approximation register analog-to-digital converters (SAR ADC).

Specifications | Ref. [2] | Ref. [3] | Ref. [4] | This Work |
---|---|---|---|---|

Architecture | SAR | SAR | SAR | SAR |

Technology(nm) | 28 | 40 | 28 | 40 |

Supply(V) | 1.8 | 1.0 | 1.2/1.5 | 1.2 |

Sampling Rate(MS/s) | 4 | 40 | 600 | 2 |

Resolution(bit) | 12 | 12 | 12 | 12 |

SNDR(dB) | 70.1 | 63.46 | 60.7 | 70.15 |

SFDR(dB) | 84.3 | 73.72 | — | 85.63 |

ENOB(bit) | 11.35 | 10.25 | 9.79 | 11.36 |

DNL(LSB) | +0.2/−0.2 | +0.51/−0.49 | — | +0.7/−0.6 |

INL(LSB) | +0.6/−0.6 | +1.95/−1.44 | — | +1.1/−1.0 |

Power(mW) | 1.73 | 1.25 | 26.5 | 0.3564 |

FOM(fJ/conv.-step) | 165.5 | 25.7 | 68 | 67.80 |

Active Area(mm^{2}) | 0.13 | 0.04 | 0.076 | 0.046 |

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**MDPI and ACS Style**

Li, S.; Chen, J.; Liang, B.; Guo, Y.
Low Power SAR ADC Design with Digital Background Calibration Algorithm. *Symmetry* **2020**, *12*, 1757.
https://doi.org/10.3390/sym12111757

**AMA Style**

Li S, Chen J, Liang B, Guo Y.
Low Power SAR ADC Design with Digital Background Calibration Algorithm. *Symmetry*. 2020; 12(11):1757.
https://doi.org/10.3390/sym12111757

**Chicago/Turabian Style**

Li, Shouping, Jianjun Chen, Bin Liang, and Yang Guo.
2020. "Low Power SAR ADC Design with Digital Background Calibration Algorithm" *Symmetry* 12, no. 11: 1757.
https://doi.org/10.3390/sym12111757