Search Results (79)

Memristor-based configuration memory offers an alternative solution to the volatility and large area overhead of conventional Static Random Access Memory (SRAM)-based FPGA configuration memory. Their non-volatile nature and the possibility of stacking them on top of the logic layer in a process called Back-End-Of-Line (BEOL) manufacturing help not only dramatically reduce area consumption but also significantly reduce startup time. However, due to the comparatively high defect probability caused by manufacturing defects, traditional approaches for defect tolerance are not fit to address these defects. This work introduces an approach to defect-aware and tolerant synthesis. Based on this, an investigation into the defect tolerance of different architecture choices regarding the size of LUTs and the fracturability of LUTs is presented. We can show that smaller, non-fracturable LUTs exhibit a higher defect tolerance. Moreover, multiple strategies to improve the mapping result based on the properties of the logic functions are introduced. Notably, reducing the mapping complexity of logic clusters during the packing stage significantly improves the mapping success rate. Full article

As the process node is scaled down, the spin-transfer-torque magnetic random-access memory (STT-MRAM) exhibits higher memory density than the static random-access memory (SRAM), making it one of the more promising successors of the low-level on-chip cache memory. However, the low read margin (RM) of the magnetic tunnel junction (MTJ) in STT-MRAM can limit the achievable read accuracy. We implemented 2-bit channel quantization for error-correcting code (ECC) schemes and explored the trade-offs between improved read accuracy and factors such as circuit area, power consumption, and latency. The proposed quantization scheme consists of a sensing amplifier-based 2-bit quantizer and MTJ resistor-based soft-decision thresholds. Compared to 1-bit channel quantization using the Bose–Chaudhuri–Hocquenghem (BCH) code, the proposed 2-bit quantization architecture achieves a fourfold reduction in frame error rate (FER) from $8.0\times {10}^{-4}$ to $2.0\times {10}^{-4}$ when paired with polar codes and successive cancellation (SC) decoding. Additionally, this approach results in decoding complexity that is only 1/13th of that required for BCH at a 0.7 code rate. Full article

This paper proposes a high-speed static random access memory (SRAM) architecture that integrates a self-refresh mechanism with a novel single error and adjacent-bit errors correction (SEABEC) scheme to enhance resilience against single-event upsets (SEUs) in radiation-prone environments. By leveraging extended Hamming coding and dynamic circuits, the design achieves a 29.1% RW speed improvement, reduces SEU cross-section by one order of magnitude, and incurs a 29.8% area overhead and a 95.2% dynamic power increase of the ECC module, leading to an overall chip area increase of ~14.2% compared to static logic-based RH SEC-DED SRAM. Radiation experiments validate superior tolerance across a LET range of 1.63–21.8 MeV·cm²/mg, demonstrating nearly doubled SEU resilience compared to conventional SEC-DED-based designs. This work balances error correction capabilities with system efficiency, making it suitable for high-reliability applications in space electronics and advanced processors. Full article

Wireless sensor systems can collect and share a large amount of data for different kinds of applications, but are also vulnerable to cyberattacks. The impact of cyberattacks on systems’ confidentiality, integrity, and availability can be mitigated by using authentication procedures and cryptographic algorithms. Authentication passwords and cryptographic keys may be stored in a non-volatile memory, which may be easily tampered with. Alternately, Physical Unclonable Functions (PUFs) can be adopted. They generate a chip’s unique fingerprint, by exploiting the randomness of process parameters’ variations occurring during chip fabrication, thus constituting a more secure alternative to the adoption of non-volatile memories for password storage. PUF reliability is of primary concern to guarantee a system’s availability. In this paper, the reliability of a Static Random Access Memory (SRAM)-based PUF implemented by a standard 32 nm CMOS technology is investigated, as a function of different operating conditions, such as noise, power supply voltage, and temperature, and considering different values of transistor conduction threshold voltages. The achieved results will show that transistor threshold voltage and noise are the operating conditions mostly affecting PUF reliability, while the impact of temperature variations is lower, and that of power supply variations is negligible. Full article

Resource-constrained sensor nodes in Internet-of-Things (IoT) and embedded sensing applications frequently rely on low-cost microcontrollers, where even basic algorithmic choices directly impact latency, energy consumption, and memory footprint. This study evaluates six sorting algorithms—Bubble Sort, Insertion Sort, Selection Sort, Merge Sort, Quick Sort, and Heap Sort—in the restricted environment that microcontrollers provide. Three Arduino boards were used: Arduino Uno, Arduino Leonardo, and Arduino Mega 2560. Each algorithm was implemented in its unoptimized form and tested on datasets of increasing size, emulating buffered time-series sensor readings in random, ascending, and descending order. Execution time, number of write operations, and memory usage were measured. The tests show clear distinctions between the slower $O\left(n^2\right)$ algorithms and the more efficient $O(nlogn)$ algorithms. For random inputs of $n=1000$ elements, Bubble Sort required 1,958,193.75 $\mathsf{\mu }$son average, whereas Quick Sort completed it in 54,260.50 $\mathsf{\mu }$s and Heap Sort in 92,429.00 $\mathsf{\mu }$s, i.e., speedups of more than one order of magnitude compared to the quadratic baseline. These gains, however, come with very different memory footprints. Merge Sort kept the runtime below 100,000 $\mathsf{\mu }$s at $n=1000$ but required approximately 2023 bytes of additional static random-access memory (SRAM), effectively exhausting the 2 kB SRAM of the Arduino Uno. QuickSort used approximately 311 bytes of extra SRAM and failed to process larger ascending and descending datasets on the more constrained boards due to its recursive pattern and stack usage. Heap Sort offered the best overall trade-off: it successfully executed all tested sizes up to the SRAM limit of each board while using only about 12–13 bytes of additional SRAM and keeping the runtime below 100,000 $\mathsf{\mu }$s for $n=1000$. The results provide practical guidelines for selecting sorting algorithms on 8-bit AVR Arduino-class microcontrollers, which are widely used as simple sensing and prototyping nodes operating under strict RAM, program-memory, and energy constraints. Full article

Artificial intelligence (AI) has made significant strides, with computing-in-memory (CIM) emerging as a key enabler for energy-efficient AI acceleration. Resistive random-access memory (RRAM)-based analog CIM offers better energy efficiency and storage density compared to static random-access memory (SRAM)-based digital CIM. Building on this, three-dimensional (3D) RRAM further improves storage density through vertical stacking. However, 3D-RRAM-CIM is susceptible to variation, which degrades accuracy and poses a significant challenge for system-level deployment in edge computing. Furthermore, the constrained capacity of CIM limits the multitasking performance. In this work, low-rank adaptation is applied to the Hybrid CIM system (Hybrid-CIM) for the first time, which leverages high-density 3D RRAM and high-precision SRAM, to address these challenges. Simulation results illustrate the feasibility of our approach, reducing accuracy degradation by 86% and achieving an 8.5× reduction in area with less than 2% weight overhead. In ResNet-18, with the backbone stored in 3D-RRAM kept fixed, the proposed low-rank adaptation branch (LoBranch) approach achieves an accuracy of 94.0% on CIFAR-10, which is only 0.4% lower than the noise-free digital baseline. This work strikes a favorable balance between accuracy and area, thereby facilitating reliable and efficient 3D-RRAM-based edge computing. Full article

Optimizing static random-access memory (SRAM) cells requires considering parasitic effects, as their impact on circuits in advanced nodes becomes increasingly complex. In this paper, Convolutional Neural Network-Informed Non-dominated Sorting Genetic Algorithms-II (CNN-Informed NSGA-II) was proposed to optimize 7 nm FinFET 6T-SRAM cells taking into account parasitic resistance. CNN-Informed NSGA-II uses a trained CNN model integrated into the conventional NSGA-II, thereby reducing its computational complexity. This approach provides a generally applicable solution that significantly improves the efficiency of circuits while balancing competitive performance metrics. Compared to the ideal (parasitic-free) 6T-SRAM cell design, the optimized 6T-SRAM cell design (considering parasitic effects) achieves a reduction of 81.60% in Write Dynamic Power and 64.65% in Write Time; HSNM and RSNM are improved by 11.92% and 6.42%, respectively. The optimized 7 nm FinFET 6T-SRAM cell structure in this paper outperforms the parasitic-free structure in terms of the performance parameters above, even when taking into account parasitic effects. Full article

This work introduces an innovative approach for estimating the Single-Event Upset (SEU) cross-sections in Static Random-Access Memory (SRAM) devices, addressing challenges related to limited technological information and the complexity of Technology Computer-Aided Design (TCAD) simulations. The proposed methodology is designed to be accessible even to users without in-depth TCAD expertise, enabling a streamlined yet accurate SEU cross-section estimation. Using simplified mixed-modeling (TCAD-based 2D modeling with circuit-level SPICE simulations), this approach significantly reduces computational efforts while maintaining good correlation with experimental data. Furthermore, this study identifies key parameters that influence TCAD modeling accuracy and proposes strategies for approximating unknown parameters, enhancing the reliability of SEU cross-section predictions. Full article

The proliferation of Internet of Things (IoT) swarms—comprising billions of low-end interconnected embedded devices—has transformed industrial automation, smart homes, and agriculture. However, these swarms are highly susceptible to firmware anomalies that can propagate across nodes, posing serious security threats. To address this, we propose a novel Remote Attestation (RA) framework for real-time firmware verification, leveraging Relational Graph Neural Networks (RGNNs) to model the graph-like structure of IoT swarms and capture complex inter-node dependencies. Unlike conventional Graph Neural Networks (GNNs), RGNNs incorporate edge types (e.g., Prompt, Sensor Data, Processed Signal), enabling finer-grained detection of propagation dynamics. The proposed method uses runtime Static Random Access Memory (SRAM) data to detect malicious firmware and its effects without requiring access to firmware binaries. Experimental results demonstrate that the framework achieves 99.94% accuracy and a 99.85% anomaly detection rate in a 4-node swarm (Swarm-1), and 100.00% accuracy with complete anomaly detection in a 6-node swarm (Swarm-2). Moreover, the method proves resilient against noise, dropped responses, and trace replay attacks, offering a robust and scalable solution for securing IoT swarms. Full article

Electronic equipment in space is constantly exposed to high-energy particles, which can induce Single Event Upsets (SEUs) in memory components, threatening system reliability. To address this critical challenge, we propose RHLP-18T, a radiation-hardened 18-transistor (18T) Static Random-Access Memory (SRAM) cell designed to enhance robustness against radiation-induced faults. The proposed cell integrates circuit-level Radiation-Hardened-by-Design (RHBD) techniques to mitigate both SEUs and multi-node upsets. Comprehensive simulations were conducted using 90 nm CMOS technology, benchmarking RHLP-18T against nine existing RHBD cells (RHBD14T, HPHS12T, NRHC14T, QCCS12T, RHMC12T, RHWC12T, SEA14T, SIMR-18T, and SERSC16T). Simulation results demonstrate that the proposed RHLP-18T cell exhibits superior SEU tolerance, achieving a Read Static Noise Margin (RSNM) over three times higher than the next best design. Moreover, the proposed cell achieves the lowest hold power consumption among all evaluated cells. These improvements result in the highest Figure of Merit (FOM), indicating that RHLP-18T provides an optimal trade-off between robustness and overall performance for operation in radiation-exposed environments. Full article

As a critical component of computer systems, static random access memory (SRAM) plays a significant role in the fields of high-performance computing, artificial intelligence, and the Internet of Things. However, the conventional silicon-based SRAM is facing problems such as high power consumption, integration limitations, and the need for performance improvement. For the power consumption challenge of SRAM, a novel read/write-decoupled SRAM cell is proposed in this paper. When SRAM is in a standby state, utilization of this cell can effectively reduce the leakage current, thereby reducing the static power consumption. In addition, a novel carbon–silicon heterogeneous-integrated SRAM technology is proposed in this paper. The carbon–silicon heterogeneous-integrated SRAM technology combines the high mobility, low power consumption, and low temperature process compatibility of carbon nanotubes (CNTs) with mature silicon-based fabrication processes, enabling significant optimization of access time and power consumption. The SRAM was implemented by a silicon-based 55 nm process and a carbon-based 500 nm process. The simulation results showed that when the power supply was 1.2 V, the access time of SRAM with the silicon 55 nm process was 886 ps. The static and dynamic power consumption was 91.51 nW and 1.48 mW, respectively. The SRAM with carbon–silicon heterogeneous-integrated technology achieved an access time of 872 ps, a static power consumption of 62.54 nW, and a dynamic power consumption of 1.07 mW, representing reductions of 1.58%, 31.66%, and 27.70%, respectively. Full article

As CMOS technology has advanced, the transistor integration density of static random-access memory (SRAM) cells has increased. This has led to a reduction in the critical charge of sensitive nodes, making the SRAM cells more susceptible to soft errors. When high-energy particles in space strike the sensitive nodes of an SRAM cell, a single-event upset (SEU) can occur, altering the stored data. Additionally, the charge-sharing effect between transistors can cause single-event multi-node upsets (SEMNUs). To address these challenges, this paper proposes a radiation-hardened 16T SRAM cell optimized for stability and power, referred to as RHSP16T. The performance of the proposed RHSP16T cell was compared with other radiation-hardened SRAM cells, including QUC-CE12T, WE-QUATRO, RHBD10T, RHD12T, and RSP14T. Simulation results indicate that the proposed RHSP16T cell exhibits higher read and write stability, along with lower-leakage power consumption. compared with all other cells. This demonstrates that RHSP16T ensures high reliability for stored data. Furthermore, EQM results show that the RHSP16T cell outperformed the compared designs in overall SRAM cell performance. The proposed integrated circuit was implemented in a 90 nm CMOS process and operated on 1 V supply voltage. Full article

The performance of Static Nanomaterials Random-Access Memories (SRAMs) is often degraded in the sub-threshold region as it is susceptible to increased access energy and leakage power. However, the low-power operation of SRAM is very much essential for efficient device functioning. Accordingly, designing robust SRAM cells that maintain stability and minimize power consumption is a key challenge. In this regard, with this ongoing work, the authors present novel designs of SRAMs using memristor technology by mitigating the shortcomings discussed above. This paper proposes a novel SRAM architecture of four transistors and five memristors, by integrating memristor technology to achieve drastic improvement in performance at subthreshold regions. Further, it performs an analysis of the metrics of static noise margin and power consumption to comprehensively evaluate the proposed SRAM designs. Simulation using Cadence Virtuoso for 65 nm technology demonstrates that power consumption for a 4T5M cell is about two and a half times lower than for 4T4M and 1.2 times lower than for 4T3M, hence proving that it will be promising for extremely low-power applications. Full article

The exposure of spaceborne devices to high-energy charged particles in space results in the occurrence of both a total ionizing dose (TID) and the single-event effect (SEE). These phenomena present significant challenges for the reliable operation of spacecraft and satellites. The rapid advancement of semiconductor fabrication processes and the continuous reduction in device feature size have led to an increase in the significance of the synergistic effects of TID and SEE in static random access memory (SRAM). In order to elucidate the involved physical mechanisms, the synergistic effects of TID and single-event upset (SEU) in a new kind of 130 nm 7T silicon-on-insulator (SOI) SRAM were investigated by means of cobalt-60 gamma-ray and heavy ion irradiation experiments. The findings demonstrate that 7T SOI SRAM is capable of maintaining normal reading and writing functionality when subjected to TID irradiation at a total dose of up to 750 krad(Si). In general, the TID was observed to reduce the SEU cross-section of the 7T SOI SRAM. However, the extent of this reduction was influenced by the heavy ion LET value and the specific writing data pattern employed. Based on the available evidence, it can be proposed that TID preirradiation represents a promising avenue for enhancing the resilience of 7T SOI SRAMs to SEU. Full article

As the feature size of integrated circuit decreases, the critical charge of single-event effect decreases as well, making nano-scale devices more susceptible to the high-energy charged particles during their application in space. Here, we study the electron-induced single-event effect in 28 nm static random-access memory (SRAM)-based field programmable gate array (FPGA) utilizing high-energy electrons with energy of 1 MeV~5 MeV. The experimental results demonstrate that the 3 MeV electrons can cause single-event functional interrupts (SEFIs) in FPGA, while the electrons with other energies cannot. To further explore the mechanism of electron-induced SEFIs in this nanoscale FPGA, we combined Monte Carlo, Technology Computer-Aided Design (TCAD), and Simulation Program with Integrated Circuit Emphasis (SPICE) simulations. It is revealed that the SEFI was mainly caused by the direct ionization effect of high-energy electrons, and the SEFI was related to the interactions between multiple sensitive nodes. Full article