Optimization of 6T-SRAM Cell Based on CNN-Informed NSGA-II with Consideration of Parasitic Resistance

Abstract

Optimizing static random-access memory (SRAM) cells requires considering parasitic effects, as their impact on circuits in advanced nodes becomes increasingly complex. In this paper, Convolutional Neural Network-Informed Non-dominated Sorting Genetic Algorithms-II (CNN-Informed NSGA-II) was proposed to optimize 7 nm FinFET 6T-SRAM cells taking into account parasitic resistance. CNN-Informed NSGA-II uses a trained CNN model integrated into the conventional NSGA-II, thereby reducing its computational complexity. This approach provides a generally applicable solution that significantly improves the efficiency of circuits while balancing competitive performance metrics. Compared to the ideal (parasitic-free) 6T-SRAM cell design, the optimized 6T-SRAM cell design (considering parasitic effects) achieves a reduction of 81.60% in Write Dynamic Power and 64.65% in Write Time; HSNM and RSNM are improved by 11.92% and 6.42%, respectively. The optimized 7 nm FinFET 6T-SRAM cell structure in this paper outperforms the parasitic-free structure in terms of the performance parameters above, even when taking into account parasitic effects.

1. Introduction

SRAM is widely used in memory caches due to its high read/write speed [1]. With a reduction in circuit size and an increase in device density, the impact of parasitic effects becomes increasingly apparent and even causes read and write faults in SRAM cells [2]. Maddela et al. [3] conducted detailed studies on different kinds of faults caused by parasitic effects on SRAM at different technology nodes. Ajay et al. [4] analyzed the topology of 22 nm 6T FinFET SRAM and explored the effect of parasitic capacitance on its performance, proving that symmetric gate-workfunction 6T FinFET SRAMs have better dynamic write-ability and DC metrics. Thus, parasitic effects need to be considered when modeling SRAM at advanced nodes. Gupta et al. [5] studied the effects of different device structures on parasitic resistance and capacitance by introducing a novel device called the complementary field-effect transistor at the 7 nm node. Due to the three-dimensional structure, 7 nm FinFETs have gate capacitance, parasitic capacitance, and resistance. Therefore, parasitic effects need to be analyzed in device and circuit design for advanced nodes using FinFET [6]. To address parasitic effects in the post-layout simulation process, Luo et al. [7,8] considered parasitic capacitance and parasitic resistance in the pre-layout simulation stage. This measure helps to analyze the impact of parasitic parameter values on the performance of SRAM cells, thus optimizing the layout accordingly. However, some parasitic parameters have competitive relationships with a specific performance metric. To quickly balance the various performance metrics of SRAM cells, a faster method is required to analyze multiple parasitic parameters.

The application of low-cost machine learning (ML) models can realize the fast prediction of circuit parameters. Jeon et al. [9] focused on parasitic parameters and accelerated the extraction of SRAM’s RC netlist through Bayesian optimization. Both Bouhlila et al. [10] and Sudharsan et al. [11] applied ML models for the rapid analysis and optimization of SRAM cell performance metrics. Particularly, in a recent study, Shen et al. [12] used Graph Neural Network (GNN) classifiers and Multi-Layer Perceptron (MLP) regressors to perform parasitic extraction on SRAM in the pre-layout simulation stage, accelerating the parasitic extraction process. However, performance metrics such as the power consumption and read/Write Time of SRAM cells often exhibit a competitive relationship [13]. For example, designs with larger cell areas have higher static noise margins (SNMs) but result in higher power consumption and larger latency. Genetic algorithms, which mimic natural evolution, have been proposed to obtain the optimal solutions for multi-objective optimization problems [14]. Zhang et al. [15] applied a genetic algorithm to optimize various wearout-related parameters of SRAM cells. Some parasitic resistance of SRAM cells has a competitive impact on performance metrics [7]. So far, no work has balanced parasitic-related performance metrics through genetic algorithms. This paper focuses on parasitic resistance and uses the improved genetic algorithm to optimize the performance of SRAM cells.

This paper improves the algorithm by combining NSGA-II with a trained CNN model and proposes CNN-Informed NSGA-II for higher efficiency. The algorithm achieves high computational efficiency even under large population sizes and strict constraints. The parasitic resistances between key nodes and the transistor ports of 7 nm FinFET 6T-SRAM were analyzed in this paper. Despite considering parasitic effects, the optimized SRAM cell’s performance was still superior to that of the parasitic-free state 7 nm FinFET 6T-SRAM. CNN-informed NSGA-II significantly enhances the efficiency of multi-objective optimization for SRAM cells.

2. Methodology

This paper proposes a method for the rapid analysis and optimization of the parasitic resistance of SRAM cells. Figure 1 outlines our methodology: Firstly, in Section 2.1, we use HSPICE simulation and analyze the impact of parasitic parameters between key nodes and the transistor ports of 7 nm FinFET 6T-SRAM on its performance to determine the resistance that needs to be optimized. Afterward, multiple HSPICE simulations are conducted based on these resistances to generate a dataset. In Section 2.2, these datasets are employed to train various neural network models, among which the one-dimensional CNN model performs the best. In Section 2.3, the best-trained CNN model is integrated into the conventional NSGA-II to obtain the Pareto fronts with different configurations of resistances. CNN-informed NSGA-II is used to find the appropriate resistance configuration based on the performance metrics of the 6T-SRAM cell. The selected Pareto-optimal solution is used to design 6T-SRAM.

2.1. Analysis of Parasitic Resistances in 6T-SRAM and Generation of Dataset

Usually, parasitic effects are considered during post-layout simulation, after which the circuit layout can be optimized. This process, however, is expensive and time-consuming. Analyzing parasitic effects during pre-layout circuit simulation and designing layouts based on optimization goals for specific parasitic parameters can balance various performance parameters of SRAM cells. Several studies have investigated the parasitic extraction of 6T-SRAM cell circuits; parasitic capacitance has been proven to have a negative impact on all performance parameters of SRAM cells [7,8]. The effect of parasitic resistance on the performance of SRAM is competitive, so this paper mainly analyzes and balances parasitic resistance. The parasitic resistance networks are shown in Figure 2, which illustrate the parasitic resistances between the key nodes (storage nodes O1/O2, power supply (VDD), ground (VSS), bit line and bit line bar (BL/BLB), and write line (WL)) of 6T-SRAM and the transistor ports, while

Table 1. Parasitic resistances between key nodes and the transistor ports of 6T-SRAM cells [7].

Res.	Key Nodes	Transistor Ports
Rbax	BL/BLB	AX_D
Roax	O1/O2	AX_S
Ropu	O1/O2	PU_D
Ropd	O1/O2	PD_D
Ropug	O1/O2	PU_G
Ropdg	O1/O2	PD_G
Rwax	WL	AX_G
Rpds	GND	PD_S
Rpud	VDD	PU_S

shows the classification of these parasitic resistances.

A 7 nm FinFET 6T-SRAM circuit schematic was developed using Cadence Virtuoso (6.1.8) based on the ASAP7 PDK library [16]. The ratio of PU:PD:AX was set to 1:5:2 in this paper, to obtain SRAM cells with high stability [17] and high read/write speed [18]. The supply voltage (VDD) was set to 0.7 V [19]. Subsequently, transient and DC simulations of the 6T-SRAM cell in the hold, read, and write states were conducted using HSPICE. In the relevant experiments, parasitic resistances between key nodes of 6T-SRAM were extracted [7]. To align with the actual scenario and enable NSGA-II to search for optimal parameters in sufficient detail, the value of each type was uniformly varied from 0 to 25 K$\Omega$. The value of each type of parasitic resistance is shown in Table 1, which is used to investigate the impact of significant parasitic effects on the performance metrics of 6T-SRAM cells.

The simulation results, as shown in Figure 3, demonstrate the variations in eight performance metrics of the 6T-SRAM cell when each parasitic resistance is individually varied from 0 to 25 K$\Omega$. The performance metrics are Write Dynamic Power (average power in transient simulation, when the operating frequency of the SRAM cell is 250 kHz), Write Time (time from the 50% rising edge of WL to the 90% falling edge), Write/Read Peak-to-Peak Power (the difference between the maximum and minimum values of the power curve during DC simulation), Write/Read Average Power (the average value of the power curve during DC simulation), and Hold/Read Static Noise Margin (H/RSNM, where the SNM is defined as the diagonal length of the largest inner square in the butterfly curve). Notably, in the hold state, the voltage of WL is 0, and the access transistors are in the cutoff state, so the relevant parasitic resistance is not considered. There are some counterintuitive conclusions in the simulation results of Figure 3, and several types of parasitic resistance (Rbax, Roax, and Ropd) increase, which can lead to a decrease in power. These phenomena are caused by multiple physical reasons. For example, an increase in parasitic resistance prolongs the charging and discharging times of the storage nodes, which in turn leads to a decrease in the average power within one period. Alternatively, an increase in parasitic resistance can alter the current distribution in the circuit, leading to a significant reduction in the current of high-energy-consuming branches and potentially lowering the overall power consumption of the circuit.

The analysis of similar phenomena typically requires a significant amount of professional knowledge and multiple simulations to balance the power consumption and other performance metrics (SNM and delay) of SRAM cells. Thus, this paper combines machine learning with genetic algorithms to quickly find suitable parameters, providing a series of guiding ideas for the layout of SRAM cells. The optimization guidance for each type of resistance is recorded in

Table 2. Based on the impact of various parasitic resistances on 6T-SRAM performance metrics, an analysis is conducted to determine the optimization guidance for each type of parasitic resistance.

Performance Metrics	Optimization Guidance
	Decrease	Increase
Write Dynamic Power	-	Roax, Ropd, Rbax, Rpds, Rwax
Write Time	Rbax, Roax	-
Write Peak-to-Peak Power	-	Roax, Ropd, Rbax, Rpds
Write Average Power	-	Roax, Ropd, Rbax, Rpds
Read Average Power	-	Roax, Ropd, Rbax, Rpds
Read Peak-to-Peak Power	Rpds, Rpud	Rbax, Roax
RSNM	Rpds	Roax, Rbax
HSNM	Rpds, Ropd, Ropu, Rpud	-

. According to the information in Table 2, to balance the performance metrics of the read and write states, Rbax, Roax, and Rpds were selected; a detailed analysis of these three types of resistance will be conducted in the following sections.

During the dataset generation process, PVT (Process, Voltage, Temperature) represents the standard process corner, with a voltage of 0.7 V and a temperature of 27 °C. The values of the three types of parasitic resistances (Rbax, Roax, and Rpds) were varied from 0 to 25 K$\Omega$ through HSPICE simulations. Removing samples that failed to write “0” (caused by parasitic effects) resulted in 5604 samples. These 5604 samples are used as the dataset to train the neural network model. When only considering the read and write state, each sample’s input features include the values of Rbax, Roax, and Rpds, while the output features comprise the values of Write Peak-to-Peak Power, Write Average Power, Write Dynamic Power, Write Time, Read Peak-to-Peak Power, Read Average Power, and RSNM—seven performance metrics in total.

2.2. The Training of the Neural Networks

In this section, a one-dimensional convolutional neural network (1D-CNN) was trained to predict performance metrics based on the parasitic resistances. Among the 5604 samples in the dataset, 5% were allocated for validation. The remaining data was split into 75% for training and 25% for testing. In the preprocessing stage, MinMaxScaler was applied to the inputs and outputs. The hyperparameters for each neural network model were determined through experimentation and tuning. The cuDNN library of PyTorch (2.3.0) [20] was used for the three neural network models in this paper, and the Adam optimizer [21] was employed with a learning rate of 0.001. The loss function was defined as a combination of the mean squared error (MSE) and L2 regularization loss, which can accelerate model convergence.

$$Loss={\displaystyle \frac{1}{n}}{\sum }_{i=1}^n{(y_i-\widehat{y_i})}^2+\lambda {\sum }_{p\in parameters}{p}^2$$

(1)

where $\lambda$ is the regularization strength parameter, set to 0.00001, and $parameters$ represents the weights and biases of the model. The CNN model was trained for 50 epochs to prevent overfitting.

The 1D-CNN model is a filter (convolutional kernel) that slides along the input data [22]. Before performing the convolution operation, the unsqueeze and expand operations are used to expand each sample with three channels, thereby obtaining a data shape suitable for 1D-CNN. During the convolution operation, the filter performs dot product operation with the local area of the input data.

$$y\left[n\right]=b+{\sum }_{i=1}^{C_{in}}(x\left[n\right]·w_i)\left[n\right]$$

(2)

where $y\left[n\right]$ is the output of the convolution layer, $C_{in}$ is the number of channels, and b is the bias. $w_i$ is the i th filter, and $x\left[n\right]$ is the input sequence. Figure 4c shows the structure of the CNN model as 3-cnn1 (filters: 32; kernel size: 3; padding: 1; stride: 1)-maxpool (kernel size: 2; stride: 2)-cnn2 (filters: 64; kernel size: 3; padding: 1; stride: 1)-cnn3 (filters: 128; kernel size: 3; padding: 1; stride: 1)-cnn4 (filters: 256; kernel size: 3; padding: 1; stride: 1)-flatten-fc256-7. It has four convolutional layers, with a max-pooling layer following the first convolutional layer, a flatten layer, and a fully connected layer following the fourth convolutional layer. The activation function for the four convolutional layers is ReLU. In the designed multi-channel 1D-CNN, each filter is used to obtain different feature maps, and this measure can comprehensively extract features and improve the performance of 1D-CNN [23].

We also trained other neural network models, the Multi-Layer Perceptron (MLP) and Long Short-Term Memory (LSTM). The MLP model exhibits good performance in nonlinear problems [24]. Figure 4a shows the structure of the MLP model as 3-fc64-fc128-fc128-fc64-7, with four fully linked layers and their activation functions being rectifier linear units (ReLUs) [25]. The LSTM model is a special case of recurrent neural networks that alleviates gradient vanishing through gating [26]. Figure 4b displays the structure of the LSTM model, which is 3-LSTM (hidden size: 128)-fc128-7, and the activation function is sigmoid.

After training, the performance of the neural network models was evaluated using an additional 5% of the dataset. The MSE and the R-squared (R²) values for the three models are presented in

Table 3. The performance evaluation metrics for the MLP, CNN, and LSTM, including the mean squared error (MSE) and the R-squared (R²) value.

Model	MSE	R2
MLP	5.94 $\times {10}^{-7}$	0.9204
CNN	2.11 $\times {10}^{-7}$	0.9690
LSTM	2.04 $\times {10}^{-7}$	0.9109

.

$$MSE={\displaystyle \frac{1}{n}}{\sum }_{i=1}^n{(y_i-\widehat{y_i})}^2$$

(3)

$$R^2=1-{\displaystyle \frac{S{S}_{res}}{S{S}_{tot}}}$$

(4)

where $S{S}_{res}$ is the Sum of Squares due to Error, representing the sum of squares of the difference between the actual value and the model’s predicted value. $S{S}_{tot}$ is the Sum of Squares due to Total, which represents the sum of squares of the difference between the actual value and the average value of the dataset. All three models have a very small MSE, but the CNN model performs the best from the R² perspective.

2.3. CNN-Informed NSGA-II to Obtain Pareto Front

CNN-Informed NSGA-II is introduced in this section to optimize the performance metrics and identify the optimal configuration of the parasitic resistance values. Figure 5a shows a flowchart of NSGA-II, and this algorithm encodes the decision variables in binary or real number format and then applies crossover and mutation operations. In each iteration, the non-dominated sorting, crowding-distance assignment, and elite strategy are used to explore the parameter space [27]. Non-dominated sorting is a key component of NSGA-II. The following is the mathematical principle of non-dominated sorting: $P=\{x_1,x_2,\dots ,x_N\}$ is the population containing N individuals; for each individual $x_i$, $n_i$ is the domination count, and $S_i=\{x_j\in P|x_i\prec x_j\}$ is the set of individuals dominated by the individual $x_i$. For $i=1,2,\dots ,N$, we iterate through all pairs of individuals $(x_i,x_j)(j=1,2,\dots ,N\mathrm{and}j\ne i)$. If $x_i\prec x_j$, $S_i\leftarrow S_i\cup \left\{x_j\right\}$ and if $x_j\prec x_i$, then $S_i\leftarrow S_i\cup \left\{x_j\right\}$. Subsequently, based on the dominance count $n_i$, individuals in $S_i$ are assigned to different fronts. Among them, the set of individuals with the smallest $n_i$ constitutes the Pareto front.

However, NSGA-II has limitations; exploring the entire parameter space can yield unrealistic solutions for solving practical problems. The quality of the solutions obtained by NSGA-II largely depends on the setting of constraints and stopping conditions. Strict constraints and stopping conditions may require a large number of expensive iterations to satisfy, and NSGA-II may also fail to obtain Pareto-optimal solutions due to convergence to local minima. This section proposes a generally applicable approach to address these limitations of NSGA-II.

Figure 5b shows a flowchart of CNN-informed NSGA-II. The following are the improvements over the traditional NSGA-II:

• First, 4000 samples are randomly selected from the simulation data as the initial population. This avoids the slow convergence associated with randomly generated problems.
• The non-dominated sorting part was replaced by a trained CNN model. During each iteration, the CNN model directly takes decision variables (resistances) as input and outputs the objective function values (performance metrics). Constraints are set based on practical requirements for screening individuals whose constraints are retained, and the remaining individuals proceed to crossover and mutation.
• Population diversity is preserved, and algorithms are prevented from converging to local minima. In each iteration, the crowding-distance of the individuals is calculated and used as a “Diversity Threshold”. When the threshold is no less than 0.1, 100 randomly selected samples from the simulation data are combined to serve as parents for the next iteration. The Diversity Threshold is defined as follows:

  $$DiversityThreshold={\displaystyle \frac{2}{n(n-1)}}{\sum }_{i=1}^{n-1}{\sum }_{j=i+1}^n{d}_{ij}$$

  (5)

  where n is the population size, and $d_{ij}$ is the Euclidean distance between solution i and solution j. The improvements described above were implemented based on the NSGA-II provided by the Platypus library [28]. The algorithm was iterated 100 times to minimize Write Peak-to-Peak Power, Write Average Power, Write Dynamic Power, Write Time, Read Peak-to-Peak Power, and Read Average Power while maximizing RSNM.

3. Results and Discussion

The learning curve of the CNN model during the training process is shown in Figure 6a. After training, the performance of the CNN was evaluated using the 5% validation set. A comparison of the prediction results from the trained CNN model with the actual simulation results is shown in Figure 6b–h. The MSE and R-squared values of the trained CNN model are 2.11 $\times {10}^{-7}$ and 0.9690, respectively. The CNN model can accurately predict the performance metrics of the 6T-SRAM cell based on the values of the parasitic resistances Rbax, Roax, and Rpds.

The Pareto-optimal solutions obtained from CNN-informed NSGA-II are presented in

Table 4. The Pareto front (with 13 solutions) obtained from CNN-informed NSGA-II (unit: $\Omega$).

Pareto Front	Rbax	Roax	Rpds
1	124.60	20,884.71	20,504.20
2	1895.09	18,443.30	24,354.19
3	980.50	17,337.85	23,617.78
4	514.25	18,785.59	24,215.14
5	435.39	19,451.52	23,007.56
6	1123.00	20,741.90	24,631.09
7	123.39	19,868.92	20,355.95
8	1019.97	18,991.99	24,109.28
9	189.61	20,791.24	24,642.21
10	1158.71	21,208.81	21,186.57
11	899.72	20,332.68	23,186.61
12	433.42	22,114.40	20,551.84
13	370.29	15,871.56	24,628.51

. Simulations were conducted to validate the effectiveness of the proposed method, and a comparison was made with the parasitic-free 7 nm FinFET 6T-SRAM cell. Additionally, optimization strategies were provided for the parasitic resistances.

HSPICE was employed for transient and DC simulations for the 13 Pareto-optimal solutions. As a result, the performance metrics were obtained, including Write Peak-to-Peak Power, Write Average Power, Write Dynamic Power, Write Time, Read Peak-to-Peak Power, Read Average Power, and RSNM, for each solution, as shown in Figure 7.

The 13th solution, which yielded the lowest Write Time, was selected for further simulation. This solution was compared to the ideal (parasitic-free) 7 nm FinFET 6T-SRAM cell [29] in terms of Write Dynamic Power, Write Time, HSNM, and RSNM, with the results displayed in

Table 5. A comparison of Write Dynamic Power, Write Time, HSNM, and RSNM for the 13th solution with the ideal (parasitic-free) 7 nm FinFET 6T-SRAM design [29], at a supply voltage (VDD) of 0.5 V.

	Write Dynamic Power	Write Time	HSNM	RSNM
This work	12.49 uW	33.33 ps	0.3099 V	0.1658 V
Ref. [29]	67.87 uW	94.28 ps	0.2769 V	0.1558 V

. Despite including parasitic effects, CNN-informed NSGA-II’s Pareto-optimal solution demonstrates better performance. Specifically, Write Dynamic Power and Write Time were reduced by 81.60% and 64.65%, respectively, while HSNM and RSNM increased by 11.92% and 6.42% compared to the ideal SRAM [29]. The 6T-SRAM cell designed in this study is mainly intended for applications that require frequent read and write operations. Compared with RRAM/PCM [30,31], the 6T-SRAM cell designed in this paper features fast read/write speeds, low power consumption fluctuations, and a high noise margin. Consequently, the designed SRAM holds broad application prospects in high-precision In-Memory Computing (IMC) scenarios, such as control logic storage and temporary computing data caching.

The proposed method analyzes parasitic effects during pre-layout simulation and provides optimization strategies. A detailed analysis was conducted on the impact of the parasitic resistances (Rbax, Roax, and Rpds) on the performance metrics of 6T-SRAM, and optimal configurations for these parasitic resistances were obtained. According to Table 4, optimization efforts should focus on Rbax, while Roax and Rpds may, in some cases, even contribute positively to performance. Rbax represents the resistance between BL/BLB and the drain of access transistors. The following are suggested optimization strategies for Rbax:

• Optimize the interconnects. Use a wider BL/BLB or arrange interconnects in different metal layers to reduce parasitic resistance.
• Use the buried power rail structure [32] to reduce interconnect parasitic resistance.
• Improve the manufacturing process. Use Ruthenium instead of copper for interconnects to reduce resistance [33].

In addition, the proposed CNN-informed NSGA-II for multi-objective optimization can be generalized to other practical problems that require a large population size and strict constraints. In this approach, regarding the computationally intensive part, non-dominated sorting is replaced by a trained CNN model. For NSGA-II, the algorithmic complexity per iteration is $O\left(M{N}^2\right)$, where the complexity of non-dominated sorting is $O\left(M{\left(2N\right)}^2\right)$, M is the number of objective functions, and N is the population size [27]. In contrast, the CNN model’s computational complexity for predicting N samples is $O(N\times 131,680).$ Given an initial population size of 4000, NSGA-II’s complexity of non-dominated sorting is $O\left(M{\left(2N\right)}^2\right)$ per iteration. In contrast, for CNN-informed NSGA-II, many individuals will be filtered out by setting constraints. Except for the first iteration, the number of samples involved in each iteration is far less than 4000. This results in the computational complexity of CNN-informed NSGA-II being much lower than that of the traditional NSGA-II during the iterative process, especially when dealing with a large population size.

Table 6. A comparison of the runtime between the proposed CNN-informed NSGA-II framework and the MOIL framework [34] for optimizing SRAM cells. The number of samples used in this work for simulation and NN training is 5604; for the genetic algorithm, it is 4000; and the number of samples for the MOIL framework is 800.

Unit: s	This Work	Ref. [34]
Simulation time	17,498.8	3276.0
NN training time	70.8	504.0
Genetic algorithm time	11.3	3312.0
Total time	17,580.9	7092.0

provides a comparison of the runtime between the CNN-informed NSGA-II framework and the MOIL framework (which uses an ANN surrogate model and the NSGA-II algorithm) [34] for optimizing SRAM cells. The MOIL framework employs the traditional NSGA-II in the genetic algorithm part, while this work adopts CNN-informed NSGA-II. In Table 6, the runtime of the genetic algorithm in this work is much shorter than that of the MOIL framework, indicating that the algorithm complexity of CNN-informed NSGA-II is indeed reduced. In addition, when using Bayesian optimization with a sample size of 800, the runtime is 26.7 h [34], which is significantly longer than that of CNN-informed NSGA-II.

CNN-informed NSGA-II is also advantageous under strict constraint conditions. In traditional NSGA-II, strict constraints and stopping conditions mean high-quality Pareto-optimal solutions for practical problems. However, this can require excessive iterations for NSGA-II, potentially risking convergence to local minima and failure to obtain the Pareto-optimal solutions. In contrast, CNN-informed NSGA-II avoids these problems by introducing a simulation data-driven CNN predictive model, resulting in high computational efficiency even under strict constraint conditions.

4. Conclusions

This paper presents a comprehensive analysis of the parasitic effects resulting from parasitic resistance between the key nodes and transistor ports in 7 nm FinFET 6T-SRAM cells. Specific parasitic resistances were observed to have competitive relationships with the SRAM cell’s performance metrics. By implementing predictive neural networks and CNN-informed NSGA-II, a trade-off was achieved among seven performance metrics for the 6T-SRAM cell (Write Peak-to-Peak Power, Write Average Power, Write Dynamic Power, Write Time, Read Peak-to-Peak Power, Read Average Power, and RSNM). This resulted in 13 Pareto-optimal solutions, including configurations for the parasitic resistances Rbax, Roax, and Rpds. A detailed simulation was conducted for one of the Pareto-optimal solutions, considering the significant parasitic effects of Rbax, Roax, and Rpds. The results showed that the performance metrics for the 6T-SRAM design achieved a reduction of 81.60% and 64.65% in Write Dynamic Power and Write Time and an increase of 11.92% and 6.42% in HSNM and RSNM, respectively, compared to those of the ideal (parasitic-free) 7 nm FinFET 6T-SRAM cell design. This method considers parasitic effects during pre-layout simulation and accelerates this process using CNN-informed NSGA-II. This approach significantly speeds up the chip design process compared to the traditional workflow. Additionally, the approach proposed in this paper also provides a framework for analyzing parasitic effects at advanced technology nodes.

The CNN-informed NSGA-II proposed in this paper is a generally applicable approach with high computational efficiency when dealing with practical problems with large populations and strict constraints. The method efficiently manages trade-offs among parameters with competitive relationships and achieves multi-objective optimization, showing broad application potential in circuit design. In this work, the PVT conditions were set to the standard process corner, specifically at 0.7 V and 27 °C. To further enhance PVT robustness verification and meet the requirements of practical chip applications in future work, we will expand to a multi-PVT dataset, retrain the CNN to enable PVT-generalizable performance prediction, and implement PVT-aware multi-objective optimization. These steps will significantly improve the application value of our framework in the practical design of 7 nm FinFET SRAM.