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Search Results (773)

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11 pages, 2306 KiB  
Article
Optical Path Design of an Integrated Cavity Optomechanical Accelerometer with Strip Waveguides
by Chengwei Xian, Pengju Kuang, Zhe Li, Yi Zhang, Changsong Wang, Rudi Zhou, Guangjun Wen, Yongjun Huang and Boyu Fan
Photonics 2025, 12(8), 785; https://doi.org/10.3390/photonics12080785 (registering DOI) - 4 Aug 2025
Abstract
To improve the efficiency and stability of the system, this paper proposes a monolithic integrated optical path design for a cavity optomechanical accelerometer based on a 250 nm top silicon thickness silicon-on-insulator (SOI) wafer instead of readout through U-shape fiber coupling. Finite Element [...] Read more.
To improve the efficiency and stability of the system, this paper proposes a monolithic integrated optical path design for a cavity optomechanical accelerometer based on a 250 nm top silicon thickness silicon-on-insulator (SOI) wafer instead of readout through U-shape fiber coupling. Finite Element Analysis (FEA) and Finite-Difference Time-Domain (FDTD) methods are employed to systematically investigate the performance of key optical structures, including the resonant modes and bandgap characteristics of photonic crystal (PhC) microcavities, transmission loss of strip waveguides, coupling efficiency of tapered-lensed fiber-to-waveguide end-faces, coupling characteristics between strip waveguides and PhC waveguides, and the coupling mechanism between PhC waveguides and microcavities. Simulation results demonstrate that the designed PhC microcavity achieves a quality factor (Q-factor) of 2.26 × 105 at a 1550 nm wavelength while the optimized strip waveguide exhibits a low loss of merely 0.2 dB over a 5000 μm transmission length. The strip waveguide to PhC waveguide coupling achieves 92% transmittance at the resonant frequency, corresponding to a loss below 0.4 dB. The optimized edge coupling structure exhibits a transmittance of 75.8% (loss < 1.2 dB), with a 30 μm coupling length scheme (60% transmittance, ~2.2 dB loss) ultimately selected based on process feasibility trade-offs. The total optical path system loss (input to output) is 5.4 dB. The paper confirms that the PhC waveguide–microcavity evanescent coupling method can effectively excite the target cavity mode, ensuring optomechanical coupling efficiency for the accelerometer. This research provides theoretical foundations and design guidelines for the fabrication of high-precision monolithic integrated cavity optomechanical accelerometers. Full article
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15 pages, 5631 KiB  
Article
Design and Evaluation of a Capacitive Micromachined Ultrasonic Transducer(CMUT) Linear Array System for Thickness Measurement of Marine Structures Under Varying Environmental Conditions
by Changde He, Mengke Luo, Hanchi Chai, Hongliang Wang, Guojun Zhang, Renxin Wang, Jiangong Cui, Yuhua Yang, Wendong Zhang and Licheng Jia
Micromachines 2025, 16(8), 898; https://doi.org/10.3390/mi16080898 (registering DOI) - 31 Jul 2025
Viewed by 137
Abstract
This paper presents the design, fabrication, and experimental evaluation of a capacitive micromachined ultrasonic transducer (CMUT) linear array for non-contact thickness measurement of marine engineering structures. A 16-element CMUT array was fabricated using a silicon–silicon wafer bonding process, and encapsulated in polyurethane to [...] Read more.
This paper presents the design, fabrication, and experimental evaluation of a capacitive micromachined ultrasonic transducer (CMUT) linear array for non-contact thickness measurement of marine engineering structures. A 16-element CMUT array was fabricated using a silicon–silicon wafer bonding process, and encapsulated in polyurethane to ensure acoustic impedance matching and environmental protection in underwater conditions. The acoustic performance of the encapsulated CMUT was characterized using standard piezoelectric transducers as reference. The array achieved a transmitting sensitivity of 146.82 dB and a receiving sensitivity of −229.55 dB at 1 MHz. A complete thickness detection system was developed by integrating the CMUT array with a custom transceiver circuit and implementing a time-of-flight (ToF) measurement algorithm. To evaluate environmental robustness, systematic experiments were conducted under varying water temperatures and salinity levels. The results demonstrate that the absolute thickness measurement error remains within ±0.1 mm under all tested conditions, satisfying the accuracy requirements for marine structural health monitoring. The results validate the feasibility of CMUT-based systems for precise and stable thickness measurement in underwater environments, and support their application in non-destructive evaluation of marine infrastructure. Full article
(This article belongs to the Special Issue MEMS/NEMS Devices and Applications, 3rd Edition)
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19 pages, 1761 KiB  
Article
Prediction of China’s Silicon Wafer Price: A GA-PSO-BP Model
by Jining Wang, Hui Chen and Lei Wang
Mathematics 2025, 13(15), 2453; https://doi.org/10.3390/math13152453 - 30 Jul 2025
Viewed by 165
Abstract
The BP (Back-Propagation) neural network model (hereafter referred to as the BP model) often gets stuck in local optima when predicting China’s silicon wafer price, which hurts the accuracy of the forecasts. This study addresses the issue by enhancing the BP model. It [...] Read more.
The BP (Back-Propagation) neural network model (hereafter referred to as the BP model) often gets stuck in local optima when predicting China’s silicon wafer price, which hurts the accuracy of the forecasts. This study addresses the issue by enhancing the BP model. It integrates the principles of genetic algorithm (GA) with particle swarm optimization (PSO) to develop a new model called the GA-PSO-BP. This study also considers the material price from both the supply and demand sides of the photovoltaic industry. These prices are important factors in China’s silicon wafer price prediction. This research indicates that improving the BP model by integrating GA allows for a broader exploration of potential solution spaces. This approach helps to prevent local minima and identify the optimal solution. The BP model converges more quickly by using PSO for weight initialization. Additionally, the method by which particles share information decreases the probability of being confined to local optima. The upgraded GA-PSO-BP model demonstrates improved generalization capabilities and makes more accurate predictions. The MAE (Mean Absolute Error) value of the GA-PSO-BP model is 31.01% lower than those of the standalone BP model and also falls by 19.36% and 16.28% relative to the GA-BP and PSO-BP models, respectively. The smaller the value, the closer the prediction result of the model is to the actual value. This model has proven effective and superior in China’s silicon wafer price prediction. This capability makes it an essential resource for market analysis and decision-making within the silicon wafer industry. Full article
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11 pages, 1461 KiB  
Article
Global–Local Cooperative Optimization in Photonic Inverse Design Algorithms
by Mingzhe Li, Tong Wang, Yi Zhang, Yulin Shen, Jie Yang, Ke Zhang, Dehui Pan and Ming Xin
Photonics 2025, 12(7), 725; https://doi.org/10.3390/photonics12070725 - 17 Jul 2025
Viewed by 306
Abstract
We developed the Global–Local Integrated Topology inverse design algorithm (denoted as the GLINT algorithm), which employs a trajectory-based optimization strategy with waveguide–substrate material-flipping structural modifications, enabling the direct optimization of discrete waveguide–substrate binary structures. Compared to the conventional Direct Binary Search (DBS), the [...] Read more.
We developed the Global–Local Integrated Topology inverse design algorithm (denoted as the GLINT algorithm), which employs a trajectory-based optimization strategy with waveguide–substrate material-flipping structural modifications, enabling the direct optimization of discrete waveguide–substrate binary structures. Compared to the conventional Direct Binary Search (DBS), the GLINT algorithm not only significantly enhances computational efficiency through its global search–local refinement framework but also achieves a superior 20 nm × 20 nm optimization resolution while maintaining its optimization speed—substantially advancing the design capability. Utilizing this algorithm, we designed and experimentally demonstrated a 3.5 µm × 3.5 µm dual-port wavelength division multiplexer (WDM), achieving a minimum crosstalk of −11.3 dB and a 2 µm × 2 µm 90-degree bending waveguide exhibiting a 0.31–0.52 dB insertion loss over the 1528–1600 nm wavelength range, both fabricated on silicon-on-insulator (SOI) wafers. Additionally, a 4.5 µm × 4.5 µm three-port WDM structure was also designed and simulated, demonstrating crosstalk as low as −36.5 dB. Full article
(This article belongs to the Special Issue Recent Progress in Integrated Photonics)
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14 pages, 3338 KiB  
Article
Monolithically Integrated GaAs Nanoislands on CMOS-Compatible Si Nanotips Using GS-MBE
by Adriana Rodrigues, Anagha Kamath, Hannah-Sophie Illner, Navid Kafi, Oliver Skibitzki, Martin Schmidbauer and Fariba Hatami
Nanomaterials 2025, 15(14), 1083; https://doi.org/10.3390/nano15141083 - 12 Jul 2025
Viewed by 282
Abstract
The monolithic integration of III-V semiconductors with silicon (Si) is a critical step toward advancing optoelectronic and photonic devices. In this work, we present GaAs nanoheteroepitaxy (NHE) on Si nanotips using gas-source molecular beam epitaxy (GS-MBE). We discuss the selective growth of fully [...] Read more.
The monolithic integration of III-V semiconductors with silicon (Si) is a critical step toward advancing optoelectronic and photonic devices. In this work, we present GaAs nanoheteroepitaxy (NHE) on Si nanotips using gas-source molecular beam epitaxy (GS-MBE). We discuss the selective growth of fully relaxed GaAs nanoislands on complementary metal oxide semiconductor (CMOS)-compatible Si(001) nanotip wafers. Nanotip wafers were fabricated using a state-of-the-art 0.13 μm SiGe Bipolar CMOS pilot line on 200 mm wafers. Our investigation focuses on understanding the influence of the growth conditions on the morphology, crystalline structure, and defect formation of the GaAs islands. The morphological, structural, and optical properties of the GaAs islands were characterized using scanning electron microscopy, high-resolution X-ray diffraction, and photoluminescence spectroscopy. For samples with less deposition, the GaAs islands exhibit a monomodal size distribution, with an average effective diameter ranging between 100 and 280 nm. These islands display four distinct facet orientations corresponding to the {001} planes. As the deposition increases, larger islands with multiple crystallographic facets emerge, accompanied by a transition from a monomodal to a bimodal growth mode. Single twinning is observed in all samples. However, with increasing deposition, not only a bimodal size distribution occurs, but also the volume fraction of the twinned material increases significantly. These findings shed light on the growth dynamics of nanoheteroepitaxial GaAs and contribute to ongoing efforts toward CMOS-compatible Si-based nanophotonic technologies. Full article
(This article belongs to the Section Nanofabrication and Nanomanufacturing)
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16 pages, 5752 KiB  
Article
Hybrid-Integrated Multi-Lines Optical-Phased-Array Chip
by Shengmin Zhou, Mingjin Wang, Jingxuan Chen, Zhaozheng Yi, Jiahao Si and Wanhua Zheng
Photonics 2025, 12(7), 699; https://doi.org/10.3390/photonics12070699 - 10 Jul 2025
Viewed by 321
Abstract
We propose a hybrid-integrated III–V-silicon optical-phased-array (OPA) based on passive alignment flip–chip bonding technology and provide new solutions for LiDAR. To achieve a large range of vertical beam steering in a hybrid-integrated OPA, a multi-lines OPA in a single chip is introduced. The [...] Read more.
We propose a hybrid-integrated III–V-silicon optical-phased-array (OPA) based on passive alignment flip–chip bonding technology and provide new solutions for LiDAR. To achieve a large range of vertical beam steering in a hybrid-integrated OPA, a multi-lines OPA in a single chip is introduced. The system allows parallel hybrid integration of multiple dies onto a single wafer, achieving a multi-fold improvement in tuning efficiency. In order to increase the range of horizontal beam steering, we propose a half-wavelength pitch waveguide emitter with non-uniform width to reduce the crosstalk, which can remove the higher-order grating lobes in free space. In this work, we simulate OPA individually for four-lines and eight-lines. As a result, we simultaneously achieved a beam steering with nearly ±90° (horizontal) × 17.2° (vertical, when four-line OPA) or 39.6° (vertical, when eight-line OPA) field of view (FOV) and a high tuning efficiency with 1.13°/nm (when eight-line OPA). Full article
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17 pages, 4643 KiB  
Article
Semiconductor Wafer Flatness and Thickness Measurement Using Frequency Scanning Interferometry Technology
by Weisheng Cheng, Zexiao Li, Xuanzong Wu, Shuangxiong Yin, Bo Zhang and Xiaodong Zhang
Photonics 2025, 12(7), 663; https://doi.org/10.3390/photonics12070663 - 30 Jun 2025
Viewed by 425
Abstract
Silicon (Si) and silicon carbide (SiC) are second- and third-generation semiconductor materials with excellent properties that are particularly suitable for applications in scenarios such as high temperature, high voltage, and high frequency. Si/SiC wafers face warpage and bending problems during production, which can [...] Read more.
Silicon (Si) and silicon carbide (SiC) are second- and third-generation semiconductor materials with excellent properties that are particularly suitable for applications in scenarios such as high temperature, high voltage, and high frequency. Si/SiC wafers face warpage and bending problems during production, which can seriously affect subsequent processing. Fast, accurate, and comprehensive detection of thickness, thickness variation, and flatness (including bow and warpage) of SiC and Si wafers is an industry-recognized challenge. Frequency scanning interferometry (FSI) can synchronize the upper and lower surfaces and thickness information of transparent parallel thin wafers, but it is still affected by multiple interfacial harmonic reflections, reflectivity asymmetry, and phase modulation uncertainty when measuring SiC thin wafers, which leads to thickness calculation errors and face reconstruction deviations. To this end, this paper proposes a high-precision facet reconstruction method for SiC/Si structures, which combines harmonic spectral domain decomposition, refractive index gradient constraints, and partitioning optimization strategy, and introduces interferometric signal “oversampling” and weighted fusion of multiple sets of data to effectively suppress higher-order harmonic interferences, and to enhance the accuracy of phase resolution. The multi-layer iterative optimization model further enhances the measurement accuracy and robustness of the system. The flatness measurement system constructed based on this method can realize the simultaneous acquisition of three-dimensional top and bottom surfaces on 6-inch Si/SiC wafers, and accurately reconstruct the key parameters, such as flatness, warpage, and thickness variation (TTV). A comparison with the Corning Tropel FlatMaster commercial system shows that this method has high consistency and good applicability. Full article
(This article belongs to the Special Issue Emerging Topics in Freeform Optics)
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23 pages, 4929 KiB  
Article
Low Phase Noise, Dual-Frequency Pierce MEMS Oscillators with Direct Print Additively Manufactured Amplifier Circuits
by Liguan Li, Di Lan, Xu Han, Tinghung Liu, Julio Dewdney, Adnan Zaman, Ugur Guneroglu, Carlos Molina Martinez and Jing Wang
Micromachines 2025, 16(7), 755; https://doi.org/10.3390/mi16070755 (registering DOI) - 26 Jun 2025
Cited by 1 | Viewed by 402
Abstract
This paper presents the first demonstration and comparison of two identical oscillator circuits employing piezoelectric zinc oxide (ZnO) microelectromechanical systems (MEMS) resonators, implemented on conventional printed-circuit-board (PCB) and three-dimensional (3D)-printed acrylonitrile butadiene styrene (ABS) substrates. Both oscillators operate simultaneously at dual frequencies (260 [...] Read more.
This paper presents the first demonstration and comparison of two identical oscillator circuits employing piezoelectric zinc oxide (ZnO) microelectromechanical systems (MEMS) resonators, implemented on conventional printed-circuit-board (PCB) and three-dimensional (3D)-printed acrylonitrile butadiene styrene (ABS) substrates. Both oscillators operate simultaneously at dual frequencies (260 MHz and 437 MHz) without the need for additional circuitry. The MEMS resonators, fabricated on silicon-on-insulator (SOI) wafers, exhibit high-quality factors (Q), ensuring superior phase noise performance. Experimental results indicate that the oscillator packaged using 3D-printed chip-carrier assembly achieves a 2–3 dB improvement in phase noise compared to the PCB-based oscillator, attributed to the ABS substrate’s lower dielectric loss and reduced parasitic effects at radio frequency (RF). Specifically, phase noise values between −84 and −77 dBc/Hz at 1 kHz offset and a noise floor of −163 dBc/Hz at far-from-carrier offset were achieved. Additionally, the 3D-printed ABS-based oscillator delivers notably higher output power (4.575 dBm at 260 MHz and 0.147 dBm at 437 MHz). To facilitate modular characterization, advanced packaging techniques leveraging precise 3D-printed encapsulation with sub-100 μm lateral interconnects were employed. These ensured robust packaging integrity without compromising oscillator performance. Furthermore, a comparison between two transistor technologies—a silicon germanium (SiGe) heterojunction bipolar transistor (HBT) and an enhancement-mode pseudomorphic high-electron-mobility transistor (E-pHEMT)—demonstrated that SiGe HBT transistors provide superior phase noise characteristics at close-to-carrier offset frequencies, with a significant 11 dB improvement observed at 1 kHz offset. These results highlight the promising potential of 3D-printed chip-carrier packaging techniques in high-performance MEMS oscillator applications. Full article
(This article belongs to the Section E:Engineering and Technology)
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11 pages, 3502 KiB  
Technical Note
Defect Detection and Error Source Tracing in Laser Marking of Silicon Wafers with Machine Learning
by Hsiao-Chung Wang, Teng-To Yu and Wen-Fei Peng
Appl. Sci. 2025, 15(13), 7020; https://doi.org/10.3390/app15137020 - 22 Jun 2025
Viewed by 728
Abstract
Laser marking on wafers can introduce various defects such as inconsistent mark quality; under- or over-etching, and misalignment. Excessive laser power and inadequate cooling can cause burning or warping. These defects were inspected using machine vision, confocal microscopy, optical and scanning electron microscopy, [...] Read more.
Laser marking on wafers can introduce various defects such as inconsistent mark quality; under- or over-etching, and misalignment. Excessive laser power and inadequate cooling can cause burning or warping. These defects were inspected using machine vision, confocal microscopy, optical and scanning electron microscopy, acoustic/ultrasonic methods, and inline monitoring and coaxial vision. Machine learning has been successfully applied to improve the classification accuracy, and we propose a random forest algorithm with a training database to not only detect the defect but also trace its cause. Four causes have been identified as follows: unstable laser power, a dirty laser head, platform shaking, and voltage fluctuation of the electrical power. The object-matching technique ensures that a visible image can be utilized without a precise location. All inspected images were compared to the standard (qualified) product image pixel-by-pixel, and then the 2D matrix pattern for each type of defect was gathered. There were 10 photos for each type of defect included in the training to build the model with various labels, and the synthetic testing images altered by the defect cause model for laser marking defect inspection had accuracies of 97.0% and 91.6% in sorting the error cause, respectively Full article
(This article belongs to the Section Computing and Artificial Intelligence)
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15 pages, 7383 KiB  
Article
Numerical Simulation-Based Study of Controlled Particle Deposition Technology for Wafer Surfaces
by Ziheng Zhang, Jun Ren, Yue Liu and Junjie Liu
Appl. Sci. 2025, 15(13), 6970; https://doi.org/10.3390/app15136970 - 20 Jun 2025
Viewed by 267
Abstract
Scanning surface inspection systems (SSISs) require standard wafers (SWs) with traceable particle characteristics for accurate calibration. Achieving controlled particle deposition on wafer surfaces is essential for the fabrication of such SWs. In this study, numerical simulations were conducted using Fluent to systematically investigate [...] Read more.
Scanning surface inspection systems (SSISs) require standard wafers (SWs) with traceable particle characteristics for accurate calibration. Achieving controlled particle deposition on wafer surfaces is essential for the fabrication of such SWs. In this study, numerical simulations were conducted using Fluent to systematically investigate the effects of key deposition parameters—including nozzle diameter, nozzle-to-wafer distance, chamber volume, rotation speed, and particle size—on deposition efficiency and uniformity. Based on the simulation results, a generation–deposition system was developed, incorporating a differential mobility classifier (DMC) to produce monodisperse aerosols. The particles used in the experiments were polystyrene latex (PSL) particles with diameters of 70 nm, 100 nm, 140 nm, and 200 nm; the wafers used were 50 mm silicon wafers. Experimental validation was carried out using scanning electron microscopy (SEM) and SSISs. The optimal deposition conditions were identified as a nozzle diameter of 4 mm, nozzle-to-wafer distance of 15 mm, chamber volume greater than 657 cm3, and a rotation speed of 0.314 rad/s. Under these unified parameters, particles with diameters ≥100 nm could be effectively deposited, while smaller particles required additional adjustments. The developed system enables the preparation of SW with traceable particle sizes and uniform deposition, fulfilling the fundamental requirements for SSIS calibration. Full article
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17 pages, 1669 KiB  
Article
Setting the Emissivity of an Imaging Bolometer in the Surface Temperature Profile Measurement of SiC-Based MEMS Heaters
by Reinoud Wolffenbuttel, David Bilby and Jaco Visser
Metrology 2025, 5(2), 36; https://doi.org/10.3390/metrology5020036 - 17 Jun 2025
Viewed by 237
Abstract
The proper usage of a bandwidth-limited imaging bolometer for the measurement of the lateral temperature profile of microstructures in Silicon-Carbide (SiC) is analyzed. The SiC spectral emissivity, ϵSiC(λ), has a dip at λ12μ [...] Read more.
The proper usage of a bandwidth-limited imaging bolometer for the measurement of the lateral temperature profile of microstructures in Silicon-Carbide (SiC) is analyzed. The SiC spectral emissivity, ϵSiC(λ), has a dip at λ12μm, which is in the band of a typical commercially available instrument and complicates the selection of the value of the equivalent emissivity, ϵeq,SiC, in the instrument settings. The impact is analyzed by deduction using simulation, and by experimental validation. Membranes of 3C-SiC of 1000 μm diameter and 3 μm thickness have been fabricated on Si wafers, with integrated poly-SiC resistors for both membrane heating and on-membrane temperature measurement for calibration purposes. The optimum setting was found as ϵeq,SiC = 0.705 ± 0.025 by deduction and as ϵeq,SiC = 0.66 ± 0.06 by experimental validation in the temperature range 120 °C to 400 °C. The apparent temperature coefficient of emissivity, TCE< 2 × 10−4 °C−1 is due to the shift of the Wien peak wavelength relative to the instrument’s sensitivity band. Full article
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14 pages, 3967 KiB  
Article
Influence of Homoepitaxial Layer Thickness on Flatness and Chemical Mechanical Planarization Induced Scratches of 4H-Silicon Carbide Epi-Wafers
by Chi-Hsiang Hsieh, Chiao-Yang Cheng, Yi-Kai Hsiao, Zi-Hao Wang, Chang-Ching Tu, Chao-Chang Arthur Chen, Po-Tsung Lee and Hao-Chung Kuo
Micromachines 2025, 16(6), 710; https://doi.org/10.3390/mi16060710 - 13 Jun 2025
Viewed by 474
Abstract
The integration of thick homoepitaxial layers on silicon carbide (SiC) substrates is critical for enabling high-voltage power devices, yet it remains challenged by substrate surface quality and wafer geometry evolution. This study investigates the relationship between substrate preparation—particularly chemical mechanical planarization (CMP)—and the [...] Read more.
The integration of thick homoepitaxial layers on silicon carbide (SiC) substrates is critical for enabling high-voltage power devices, yet it remains challenged by substrate surface quality and wafer geometry evolution. This study investigates the relationship between substrate preparation—particularly chemical mechanical planarization (CMP)—and the impact on wafer bow, total thickness variation (TTV), local thickness variation (LTV), and defect propagation during epitaxial growth. Seven 150 mm, 4° off-axis, prime-grade 4H-SiC substrates from a single ingot were processed under high-volume manufacturing (HVM) conditions and grown with epitaxial layers ranging from 12 μm to 100 μm. Metrology revealed a strong correlation between increasing epitaxial thickness and geometric deformation, especially beyond 31 μm. Despite initial surface scratches from CMP, hydrogen etching and buffer layer deposition significantly mitigated scratch propagation, as confirmed through defect mapping and SEM/FIB analysis. These findings provide a deeper understanding of the substrate-to-epitaxy integration process and offer pathways to improve manufacturability and yield in thick-epilayer SiC device fabrication. Full article
(This article belongs to the Section D:Materials and Processing)
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22 pages, 8548 KiB  
Article
Study on the Motion Trajectory of Abrasives and Surface Improvement Mechanism in Ultrasonic-Assisted Diamond Wire Sawing Monocrystalline Silicon
by Honghao Li, Yufei Gao, Shengtan Hu and Zhipu Huo
Micromachines 2025, 16(6), 708; https://doi.org/10.3390/mi16060708 - 13 Jun 2025
Viewed by 413
Abstract
The surface quality of diamond wire sawing (DWS) wafers directly affects the efficiency and yield of subsequent processing steps. This paper investigates the motion trajectory of abrasives in ultrasonic-assisted diamond wire sawing (UADWS) and its mechanism for improving surface quality. The influence of [...] Read more.
The surface quality of diamond wire sawing (DWS) wafers directly affects the efficiency and yield of subsequent processing steps. This paper investigates the motion trajectory of abrasives in ultrasonic-assisted diamond wire sawing (UADWS) and its mechanism for improving surface quality. The influence of ultrasonic vibration on the cutting arc length, cutting depth, and interference of multi-abrasive trajectories was analyzed through the establishment of an abrasive motion trajectory model. The ultrasonic vibration transforms the abrasive trajectory from linear to sinusoidal, thereby increasing the cutting arc length while reducing the cutting depth. A lower wire speed was found to be more conducive to exploiting the advantages of ultrasonic vibration. Furthermore, the intersecting interference of multi-abrasive trajectories contributes to enhanced surface quality. Experimental studies were conducted on monocrystalline silicon (mono-Si) to verify the effectiveness of ultrasonic vibration in improving surface morphology and reducing wire marks during the sawing process. The experimental results demonstrate that, compared with DWS, UADWS achieves a significantly lower surface roughness Ra and generates micro-pits. The ultrasonic vibration induces a micro-grinding effect on both peaks and valleys of wire marks, effectively reducing their peak–valley (PV) height. This study provides a theoretical basis for optimizing UADWS process parameters and holds significant implications for improving surface quality in mono-Si wafer slicing. Full article
(This article belongs to the Section D:Materials and Processing)
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12 pages, 2301 KiB  
Article
Unveiling the Hydrogen Diffusion During Degradation of Silicon Solar Cells
by MyeongSeob Sim, Yejin Gu, Donghwan Kim and Yoonmook Kang
Energies 2025, 18(12), 3090; https://doi.org/10.3390/en18123090 - 12 Jun 2025
Viewed by 394
Abstract
We investigated monocrystalline passivated emitter rear contact cells for light- and elevated-temperature-induced degradation. Among the cell performance factors, a short current density results in a significant decrease in the short term. The quantum efficiency is also affected by carrier recombination-active defects, especially in [...] Read more.
We investigated monocrystalline passivated emitter rear contact cells for light- and elevated-temperature-induced degradation. Among the cell performance factors, a short current density results in a significant decrease in the short term. The quantum efficiency is also affected by carrier recombination-active defects, especially in the case of the reference cell, which has a decreased quantum efficiency across the wavelength, unlike the commercial cell. The front side of the cell has a diffuse hydrogen distribution, and it is related to LeTID. We observe how the hydrogen changes during each process and the changes in the profile during the degradation. The hydrogen appears to redistribute within the silicon wafer and saturate at a certain equilibrium state. The hydrogen distribution is correlated with the changes in the lifetime and, finally, short current density. Regeneration occurs depending on the hydrogen concentration within the emitter, and the closer the concentration is to saturation, the less degradation occurs. Full article
(This article belongs to the Special Issue Solar Energy and Resource Utilization—2nd Edition)
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41 pages, 6794 KiB  
Article
Effectiveness of Electrode Design Methodologies for Fast EDM Slotting of Thick Silicon Wafers
by Mahmud Anjir Karim and Muhammad Pervej Jahan
Appl. Sci. 2025, 15(11), 6374; https://doi.org/10.3390/app15116374 - 5 Jun 2025
Viewed by 457
Abstract
Silicon is the most commonly used material in the electronic industries due to its unique properties, which also make it very difficult to machine using conventional machining. Electrical discharge machining (EDM) is a non-traditional process that is gaining popularity for machining silicon, although [...] Read more.
Silicon is the most commonly used material in the electronic industries due to its unique properties, which also make it very difficult to machine using conventional machining. Electrical discharge machining (EDM) is a non-traditional process that is gaining popularity for machining silicon, although a slower machining rate is one of its limitations. This study investigates two electrode design strategies to enhance the efficiency of EDM by improving the material removal rates, reducing tool wear, and refining the quality of machined features. The first approach involves using graphite electrodes in various array configurations (1 × 4 to 6 × 4) and leg heights (0.2″ and 0.3″). The second approach employs hollow electrodes with differing wall thicknesses (0.04″, 0.08″, and 0.12″). The effects of these variables on performance were evaluated by maintaining constant EDM parameters. The results indicate that increasing the number of electrode legs improves the flushing conditions, resulting in shorter machining times. Meanwhile, the shorter electrode height outperforms the taller electrode, providing a higher machining speed. The thinnest wall thickness for hollow electrodes yielded the best performance due to the increased energy distribution. Both electrode design methodologies can be used for the mass fabrication of features with targeted profiles on silicon using the die-sinking EDM process. Full article
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