Search Results (154)

Silicon carbide (SiC) MOSFETs, as one of the representative power electronic devices, have faced reliability challenges due to threshold voltage (V_th) instability under dynamic gate stress. To explore the underlying mechanisms, this work investigates 4H-SiC MOS structures (P-MOS and N-MOS) under AC bias temperature instability (AC BTI) stress, utilizing a laser to generate minority carriers and simulate realistic switching conditions. Through combined capacitance–voltage (C-V) and gate current–voltage (J_g-V_g) characterizations on P-MOS and N-MOS devices before and after degradation at different temperatures, we reveal a critical temperature dependence in defect interactions. At room temperature, degradation is dominated by electron trapping in shallow interface states and near-interface traps (NITs). In contrast, high-temperature stress activates charge exchange with deep-level, slow states. Notably, a positive V_FB shift is consistently observed in both N-MOS and P-MOS devices under AC stress, confirming that electron trapping is the dominant cause of the commonly observed positive V_th shift in SiC MOSFETs. These findings clarify the distinct defect-mediated mechanisms governing dynamic V_th instability in SiC devices, providing fundamental insights for interface engineering and reliability assessment. Full article

Silicon carbide (SiC) power converters are increasingly used in automotive, renewable energy, and industrial applications. While reliability assessments are typically performed at either the device or system level, an integrative approach that simultaneously evaluates both levels remains underexplored. This article presents a novel system-level simulation method with two strategies to evaluate the reliability of power devices and a resonant converter under varying temperatures and total ionizing doses (TIDs). Temperature-sensitive electrical parameters (TSEPs), such as on-state resistance ($R_{\mathrm{ON}}$) and threshold voltage shift ($\Delta V_{\mathrm{TH}}$), are calibrated and analyzed using a B1505A curve tracer. These parameters are incorporated into the system-level simulation of a 300 W resonant converter with a boosting cell. Both Silicon (Si) and SiC-based power resonant converters are assessed for power application in space engineering and harsh environments. Additionally, gate-oxide degradation and $\Delta V_{\mathrm{TH}}$-related issues are discussed based on the simulation results. The thermal-strategy results indicate that SiC MOSFETs maintain a more stable conduction loss at elevated temperatures, exhibiting higher reliability due to their high thermal conductivity. Conversely, increased TIDs result in a negative shift in conduction losses across all SiC devices under the radiation strategy, affecting the long-term reliability of the power converter. Full article

Power semiconductor devices are fundamental components in modern electronic power conversion. In applications demanding high power density and efficiency, the choice between silicon (Si) IGBTs and Silicon Carbide (SiC) MOSFETs is critical. SiC MOSFETs, owing to their high critical electric field, superior thermal conductivity, wide band gap, and low power loss, realize significant performance improvements and compact design. This work presents a comprehensive, simulation-driven comparative investigation under identical setups, evaluating both technologies across various parameters. The effects of temperature variations on gate-source threshold voltage drift, current slew rate, device stress, and energy dissipation during switching transitions are evaluated. Furthermore, the characteristic switching behavior when the DC-bus voltage, gate resistance, and load current are varied is investigated. This study addresses a current scarcity of systematic investigation by presenting a comprehensive comparative evaluation of switching losses and efficiency across varied operating conditions, providing validated conclusions for the design of advanced WBG converters. The results demonstrate that SiC exhibits lower losses and faster switching speeds than Si IGBTs, with minimal temperature-dependent loss variations, unlike Si devices, whose losses rise significantly with temperature. Si shows distinct tail currents during turn-off, absent in SiC devices. A conclusive comparative evaluation of switching energy losses under varied operating conditions demonstrates that SiC devices can effectively retrofit Si counterparts for fast, low-loss, high-efficiency applications. Full article

The choice of a suitable isolated and bidirectional DC/DC converter (IBDC) topology is an important step in the design of a bidirectional electric vehicle (EV) charging system. In this context, six 10 kW rated silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET)-based dual-active bridge (DAB) converter topologies, supplied by a +750/0/−750 V bipolar DC link, are analyzed and compared in this article. The evaluation criteria include the required volt-ampere semiconductor ratings, loss distribution, efficiency, and thermal considerations of the considered converter configurations. The IBDC topologies are compared based on the observations and results obtained from theoretical analysis, electro-thermal simulations, and experiments, considering the same voltage and power conditions. The advantages and disadvantages of the topologies, in terms of the considered evaluation criteria, are discussed. It is shown that the series-resonant (SR) input-series output-parallel (ISOP) full-bridge (FB) DAB converter configuration is the most suitable design choice for the considered EV charging application based on the chosen operating conditions and evaluation criteria. Full article

In this article, a dedicated testing system is developed to realize low-delay threshold voltage (V_TH) characteristic testing of silicon carbide (SiC) MOSFET devices after an avalanche stress. The developed low-delay testing system enables V_TH detection within milliseconds after the avalanche, facilitating the study of V_TH drift behavior under different gate-source turn-off voltages (V_GS-OFF) and repeated avalanche events. Experimental results of 1200 V commercial devices indicate that after a single avalanche stress, V_TH drifts positively by about 0.11 V when V_GS-OFF is 0 V. However, if the avalanche stress is monitored at a negative bias of V_GS-OFF, V_TH exhibits a negative drift. The drift increases as a more negative gate bias is applied. When V_GS-OFF reaches 6 V, the V_TH drift saturates at approximately −0.226 V. After repeated avalanche cycles, the threshold drift does not saturate until V_GS-OFF is −10 V. Furthermore, verification shows that the V_TH drift is minimized when V_GS-OFF is −3 V. The absolute value of V_TH drift shows a non-monotonic variation with avalanche cycles: it starts to increase with the number of avalanche cycles, reaching a peak at approximately 1000 cycles, and further increasing the avalanche cycles. The magnitude of the drift gradually decreases after reaching a peak. TCAD simulations reveal that this phenomenon could be attributed to the ionization of donor/acceptor traps at the SiC/SiO₂ interface and the consequent modulation of channel hole concentration. After excitation by electric fields of varying intensities, the ionization of acceptor and donor traps undergoes differential changes, consequently leading to a non-monotonic drift in threshold voltage. Full article

Accurately assessing the remaining useful life (RUL) is a significant challenge to the reliability of Silicon Carbide (SiC) MOSFETs and is crucial for their safe operation. Consequently, this paper proposes a novel data-driven prediction method that integrates Successive Variational Mode Decomposition (SVMD), the Sparrow Search Algorithm (SSA), and the Transformer model. The threshold voltage V_th is selected as the degradation parameter for prediction. Firstly, SVMD is utilized to decompose the original V_th data into a degradation trend component and several fluctuation components with different central frequencies, thereby providing a more precise feature for prediction models. Subsequently, based on the Transformer model, trend predictions are conducted on each intrinsic mode function (IMF) derived from SVMD, and these results are aggregated as the final predicted value of V_th. The hyperparameters of the Transformer are optimized using SSA to enhance prediction accuracy. Ultimately, a power cycling platform is constructed to acquire the dataset of the device, where the device is subjected to rated current and 80 °C junction temperature fluctuation stress during testing. Building upon this, the difference between the number of cycles when V_th reaches its upper limit and the current number of cycles is determined as the predicted RUL value. Results demonstrate that compared to both a single Transformer model and the SVMD-Transformer model, the proposed method achieves a higher coefficient of determination (R²) and a lower root mean square error (RMSE), indicating superior prediction performance. Full article

Discrete Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors (SiC MOSFETs) are characterized by their lower parasitic parameters and single-chip design, enabling them to achieve even faster switching speeds. However, the rapid rate of change in voltage (dv/dt) and current (di/dt) can lead to overshoot and oscillation in both voltage and current, ultimately limiting the performance of high-frequency operations. To address this issue, this paper presents a high-switching-frequency motor controller that utilizes discrete SiC MOSFETs. To achieve a high switching frequency for the controller while minimizing current oscillation and voltage overshoot, a novel electronic system architecture is proposed. Additionally, a passive driving circuit is designed to suppress gate oscillation without the need for additional control circuits. A new printed circuit board (PCB) laminate stack featuring low parasitic inductance, high current conduction capacity, and efficient heat dissipation is also developed using advanced wiring technology and a specialized heat dissipation structure. Compared to traditional methods, the proposed circuit and bus design features a simpler structure, a higher power density, and achieves a 13% reduction in current overshoot, along with a 15.7% decrease in switching loss. The silicon carbide (SiC) controller developed from this research has successfully undergone double-pulse and power testing. The results indicate that the designed controller can operate reliably over extended periods at a switching frequency of 50 kHz, achieving a maximum efficiency of 98.2% and a power density of 9 kW/kg (10 kW/L). The switching frequency and quality density achieved by the controller have not been observed in previous studies. This controller is suitable for use in the development of new energy electrical systems. Full article

Silicon carbide (SiC) MOSFETs with voltage ratings above 3.3 kV are emerging as key enablers for next-generation medium-voltage (MV) power conversion systems, offering superior blocking capabilities, faster switching speeds, and an improved thermal performance compared to conventional silicon IGBTs. However, the practical deployment of 10 kV SiC devices remains constrained by the immaturity of high-voltage chip and packaging technologies. Current development is often limited to engineering samples provided by a few suppliers and custom packaging solutions evaluated only in laboratory settings. To advance the commercialization of 10 kV SiC power modules, this paper presents the design and characterization of a 10 kV, 60 A half-bridge module employing the XHP housing and newly developed SiC MOSFET chips from China Electronics Technology Group Corporation (CETC). Electro-thermal simulations based on a finite element analysis were conducted to extract key performance parameters, with a measured parasitic inductance of 24 nH and a thermal resistance of 0.0948 K/W. To further validate the packaging concept, a double-pulse test platform was implemented. The dynamic switching behavior of the module was experimentally verified under a 6 kV DC-link voltage, demonstrating the feasibility competitiveness of this approach and paving the way for the industrial adoption of 10 kV SiC technology in MV applications. Full article

The junction temperature (T_j) is a key parameter reflecting the thermal behavior of Silicon carbide (SiC) MOSFETs and is essential for condition monitoring and reliability assessment in power electronic systems. However, the limited temperature sensitivity of switching characteristics makes it difficult for traditional single temperature-sensitive electrical parameters (TSEPs) to achieve accurate estimation. To address this challenge and enable practical thermal sensing applications, this study proposes an accurate, application-oriented T_j estimation method based on multivariate linear regression (MLR) using turn-off current fall time (t_fi) and fall loss (E_fi) as complementary TSEPs. First, the feasibility of using current fall time and current fall energy loss as TSEPs is demonstrated. Then, a coupled junction temperature prediction model is developed based on multivariate linear regression using t_fi and E_fi. The proposed method is experimentally validated through comparative analysis. Experimental results demonstrate that the proposed method achieves high prediction accuracy, highlighting its effectiveness and superiority in MLR approach based on the current fall phase characteristics of SiC MOSFETs. This method offers promising prospects for enhancing the condition monitoring, reliability assessment, and intelligent sensing capabilities of power electronics systems. Full article

This paper presents the design and implementation of a high-efficiency, full silicon carbide (SiC)-based center-tapped phase-shifted full-bridge (PSFB) converter for NiCd battery charging applications in railway systems. The converter utilizes SiC MOSFET modules on the primary side and SiC diodes on the secondary side, resulting in significant efficiency improvements due to the superior switching characteristics and high-temperature tolerance inherent in SiC devices. A nanocrystalline-cored center-tapped transformer is optimized to minimize voltage stress on the rectifier diodes. Additionally, the use of a nanocrystalline core provides high saturation flux density, low core loss, and excellent permeability, particularly at high frequencies, which significantly enhances system efficiency. The converter also compensates for temperature fluctuations during operation, enabling a wide and adjustable output voltage range according to the temperature differences. A prototype of the 10-kW, 50-kHz PSFB converter, operating with an input voltage range of 700–750 V and output voltage of 77–138 V, was developed and tested both through simulations and experimentally. The converter achieved a maximum efficiency of 97% and demonstrated a high power density of 2.23 kW/L, thereby validating the effectiveness of the proposed design for railway battery charging applications. Full article

This article presents a method for detecting the temperature distribution of two parallelized Silicon Carbide (SiC) MOSFETs. Two thermally sensitive electrical parameters (TSEPs), namely the on-state resistance ($R_{dson}$) and the threshold voltage ($V_{th}$), are introduced. A comparison of the temperatures interpolated by $V_{th}$ and $R_{dson}$ shows disparity, enabling the detection of individual junction temperatures. $V_{th}$ instability and its measurement are discussed for SiC devices. Experimental results show that, depending on the instability of the $V_{th}$ and the sensitivity of the two TSEPs at certain temperatures, a combination of different TSEPs could be a solution for extracting the maximum junction temperature of parallelized devices. Full article

The transient overvoltage caused by coupling of loop inductance during rapid turn off of a silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) can easily induce avalanche breakdown. Meanwhile, the instantaneous high-density heat flux generated by energy dissipation can create significant electrothermal coupling stress, potentially leading to device failure under severe conditions. To address the issue that the multi-chip parallel structure of power modules cannot linearly enhance avalanche withstand capability, an innovative device screening method based on parameter matching is proposed in this paper. The effectiveness of the proposed solution is verified through experiments, with the total current limit of dual-tube parallel devices and three-tube parallel devices achieving 1.9 times and 2.4 times that of single-tube devices, respectively. This research is of great significance for improving safe and reliable operation of the system. Full article

In this study, a novel silicon carbide (SiC) double-trench MOSFET (DT-MOS) combined Schottky barrier diode (SBD) and MOS-channel diode (MCD) is proposed and investigated using TCAD simulations. The integrated MCD helps inactivate the parasitic body diode when the device is utilized as a freewheeling diode, eliminating bipolar degradation. The adjustment of SBD position provides an alternative path for reverse conduction and mitigates the electric field distribution near the bottom source trench region. As a result of the Schottky contact adjustment, the reverse conduction characteristics are less influenced by the source oxide thickness, and the breakdown voltage (BV) is largely improved from 800 V to 1069 V. The gate-to-drain capacitance is much lower due to the removal of the bottom oxide, bringing an improvement to the turn-on switching rise time from 2.58 ns to 0.68 ns. These optimized performances indicate the proposed structure with both SBD and MCD has advantages in switching and breakdown characteristics. Full article

In situ estimations of gate oxide degradation and junction temperature are critical for SiC MOSFETs, as these parameters are key for device-level health management. However, the indicators used in existing evaluation methods primarily focus on one aspect and do not effectively integrate the assessment of both targets, as they require different indicators. To address this problem, this paper proposes a unified evaluation method that uses a single indicator to simultaneously estimate both gate oxide degradation and junction temperature. An on-state resistance (R_ON) model is used as the indicator. The R_ON model is first proposed to characterize the influence of temperature and gate degradation on R_ON. An iterative approach is introduced to determine the R_ON model parameters, utilizing R_ON measurements across various temperatures and gate degradation levels, while accounting for the physical characteristics of the parameters. Furthermore, an in situ estimation method for gate degradation and junction temperature is developed based on a two-level turn-on strategy. By analyzing R_ON before and after gate voltage changes, the gate degradation level and junction temperature can be simultaneously estimated. The proposed method’s effectiveness is demonstrated in a DC-DC converter application. Full article

In this paper, a high-speed motor system for an Electric Vehicle (EV) is designed, of which the rated DC-link voltage is 800 V and peak power can reach 200 kW with a high-efficiency Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor (SiC-MOSFET). With the help of optimization motor design methods, such as pole–slot combination optimization, process optimization and control optimization, the motor can reach its maximal speed of 25,000 rpm and maximal torque of 240 Nm. Finally, the performance of the high-voltage motor system based on the SiC-MOSFET power module is evaluated by simulation and experiment. Full article