A Gate Oxide Degradation and Junction Temperature Evaluation Method for SiC MOSFETs Based on an On-State Resistance Model

Abstract

In situ estimations of gate oxide degradation and junction temperature are critical for SiC MOSFETs, as these parameters are key for device-level health management. However, the indicators used in existing evaluation methods primarily focus on one aspect and do not effectively integrate the assessment of both targets, as they require different indicators. To address this problem, this paper proposes a unified evaluation method that uses a single indicator to simultaneously estimate both gate oxide degradation and junction temperature. An on-state resistance (R_ON) model is used as the indicator. The R_ON model is first proposed to characterize the influence of temperature and gate degradation on R_ON. An iterative approach is introduced to determine the R_ON model parameters, utilizing R_ON measurements across various temperatures and gate degradation levels, while accounting for the physical characteristics of the parameters. Furthermore, an in situ estimation method for gate degradation and junction temperature is developed based on a two-level turn-on strategy. By analyzing R_ON before and after gate voltage changes, the gate degradation level and junction temperature can be simultaneously estimated. The proposed method’s effectiveness is demonstrated in a DC-DC converter application.

1. Introduction

SiC MOSFETs feature high switching speed, low switching loss, high breakdown voltage, and a high maximum operating junction temperature, making them widely used in power electronics applications [1]. As a key component in power electronic systems, the reliability of SiC MOSFETs is of paramount importance. More than 50% of converter failures are initially triggered by power-switching devices [2], resulting in substantial economic losses and safety concerns. Therefore, enhancing the operational reliability of SiC MOSFETs has become a critical research focus. In situ state monitoring, by tracking critical changes in key indicators, allows for the early prediction of SiC MOSFETs’ reliability, making it a vital method for enhancing their performance.

Gate oxide degradation is a critical factor affecting the reliability of SiC MOSFETs. Compared to silicon (Si) devices, SiC MOSFETs are more susceptible to gate oxide degradation. Specifically, the presence of carbon increases the charge interface defect density at the SiC/SiO₂ interface to approximately twice that of the Si/SiO₂ interface [3,4,5]. This results in reduced channel mobility and higher power losses. Additionally, SiC MOSFETs are designed with a thinner gate oxide layer to reduce channel resistance, which exposes the gate to higher electric fields [6]. The increased electric field enhances electron injection into the oxide layer through Fowler–Nordheim tunneling [7], accelerating gate oxide degradation and compromising long-term device reliability.

In addition to gate degradation, junction temperature (T_j) is another critical factor significantly influencing the reliability of SiC MOSFETs [8]. More than 50% of switching device failures are due to high junction temperature and large T_j fluctuations [9]. High T_j can cause the device to operate beyond its thermal limits, leading to overheating and potential physical damage. Furthermore, high T_j increases the energy of charge carriers, thereby enhancing hot carrier injection and electron tunneling into the gate oxide layer. These mechanisms accelerate the formation of oxide traps and interface states at the SiC/SiO₂ interface, resulting in V_TH shifts and an increase in the on-state resistance (R_ON) [10]. The increased R_ON leads to higher conduction losses, further raising T_j. This process accelerates the further degradation of the SiC MOSFETs, forming a positive feedback loop that accelerates device failure. As a result, both T_j and gate degradation prediction are crucial for improving SiC MOSFET reliability.

Currently, the T_j evaluation and gate degradation assessment methods for SiC MOSFET are widely implemented using electrical parameter methods. Among them, thermal-sensitive electrical parameter (TSEP) methods are commonly used for T_j estimation. TSEP can be classified into dynamic and static parameters. Dynamic parameters primarily characterize the electrical behavior during turn-on and turn-off transitions, including di/dt during turn-on [11,12], dV/dt during turn-on [13], peak gate current during turn-on [14,15], turn-off delay time [16], integration of passive turn-on delay time [17], V_DS falling edge time [18], turn-off oscillation frequency of V_DS [19], turn-off miller plateau voltage [20], and so on. However, dynamic parameters are strongly correlated with V_TH, and as gate degradation [21], the correlation between V_TH and temperature shifts, leading to inaccurate T_j prediction. Static parameters are typically used for steady-state measurements, with R_ON [22] being a commonly used parameter. Similarly, R_ON is also strongly correlated with V_TH, and its relationship with temperature is affected by gate degradation.

Since V_TH is strongly correlated with gate degradation [23], both V_TH [10] and other closely related parameters, such as turn-on delay time [24], are commonly used in gate degradation assessment. To minimize the temperature effects on gate degradation assessment, temperature-insensitive parameters, such as miller capacitance [25], are selected. Additionally, parameters strongly correlated with the miller capacitor, such as gate plateau voltage [26], time of gate plateau [27], frequency information of V_G within a specific frequency band during the turn-on transient [28], and others, are also studied. However, high-resolution, in situ measurement of these capacitances, whether direct or indirect, remains challenging. More importantly, these methods focus solely on gate degradation predictions, without addressing the simultaneous estimation of both gate degradation and T_j using a single, easily measurable parameter.

This paper proposes a method for simultaneously predicting gate degradation and T_j of SiC MOSFETs using a single, easily measurable precursor, R_ON. R_ON primarily consists of R_S and R_CH, with R_S being temperature-sensitive and R_CH being sensitive to both temperature and gate degradation. A theoretical R_ON model is derived to characterize the effects of temperature and gate degradation on R_S and R_CH, and it also characterizes the relationship between R_ON, V_G, T_j, and V_TH. In order to standardize the impact of gate degradation on both V_TH and µ_N, an auxiliary parameter k_{un_aged} is introduced, allowing V_TH to comprehensively represent the effects of gate degradation on V_TH, µ_N, and its influence on R_ON. Simultaneously, a method based on iterative calculations for R_ON model parameter extraction is proposed to derive the parameters of the R_ON model. This method defines the boundary conditions and temperature dependencies of the parameters, based on their physical characteristics, ensuring efficient convergence during the computational process. The accuracy is validated by comparing theoretical calculations with experimental data across different levels of gate degradation and temperatures. Finally, a method for real-time, simultaneous evaluation of T_j and gate degradation level is introduced.

The outline of this paper is organized as follows: Section 2 presents the theoretical basis of the proposed method. In Section 3, the evaluating strategy for gate degradation and T_j of SiC MOSFETs are described. Section 4 details the experimental setup. Section 5 discusses the analysis of the experimental results. Finally, Section 6 presents the conclusions of this paper.

2. Analysis of Temperature Sensitivity and Gate Oxide Degradation Impacts on R_ON

2.1. General Analysis of R_ON

Figure 1 illustrates the structure of R_ON, showing the resistance contributions from different layers and regions in the SiC MOSFET, with R_ON expressed in (1).

$$R_{\mathrm{ON}}=R_{\mathrm{CS}}+R_{\mathrm{N}+}+R_{\mathrm{CH}}+R_{\mathrm{A}}+R_{\mathrm{JFET}}+R_{\mathrm{D}}+R_{\mathrm{SUB}}+R_{\mathrm{CD}}$$

(1)

R_CH, R_D, and R_JFET constitute the primary components of R_ON [29]. R_CH can be simplified and expressed by (2),

$$R_{\mathrm{CH}}={\displaystyle \frac{L_{\mathrm{CH}}}{2{\mu }_{\mathrm{N}}{W}_{\mathrm{CELL}}{C}_{\mathrm{OX}}}}{\displaystyle \frac{1}{V_{\mathrm{G}}-V_{\mathrm{TH}}-0.5V_{\mathrm{CH}}}}\approx {\displaystyle \frac{L_{\mathrm{CH}}}{2{\mu }_{\mathrm{N}}{W}_{\mathrm{CELL}}{C}_{\mathrm{OX}}}}{\displaystyle \frac{1}{V_{\mathrm{G}}-V_{\mathrm{TH}}}}$$

(2)

µ_N is composed of four components [30,31], as described in (3). µ_C dominates low-field mobility under low gate bias at room temperature. In contrast, µ_SR becomes the predominant factor affecting low-field mobility at higher V_G [32].

$${\displaystyle \frac{1}{{\mu }_{\mathrm{N}}}}={\displaystyle \frac{1}{{\mu }_{\mathrm{B}}}}+{\displaystyle \frac{1}{{\mu }_{\mathrm{PH}}}}+{\displaystyle \frac{1}{{\mu }_{\mathrm{C}}}}+{\displaystyle \frac{1}{{\mu }_{\mathrm{SR}}}}$$

(3)

V_TH can be expressed as (4) [10],

$$V_{\mathrm{TH}}={\displaystyle \frac{\sqrt{4{\epsilon }_{\mathrm{S}}{k}_B{T}_{\mathrm{j}}{N}_{\mathrm{A}}\ln \left(\frac{N_{\mathrm{A}}}{n_{\mathrm{i}}}\right)}}{C_{\mathrm{OX}}}}+{\displaystyle \frac{2k{T}_{\mathrm{j}}}{q}}\ln \left({\displaystyle \frac{N_{\mathrm{A}}}{n_{\mathrm{i}}}}\right)-{\displaystyle \frac{Q_{\mathrm{ot}}}{C_{\mathrm{OX}}}}+{\displaystyle \frac{Q_{\mathrm{it}}}{C_{\mathrm{OX}}}}$$

(4)

The specific JFET resistance is given by (5) [33],

$$R_{\mathrm{JFET}}={\displaystyle \frac{{\rho }_{\mathrm{JFET}}{\chi }_{\mathrm{jP}}{W}_{\mathrm{cell}}}{a}}$$

(5)

The specific R_D is given by (6),

$$R_{\mathrm{d}}={\displaystyle \frac{L_{\mathrm{d}}}{q{\mu }_{\mathrm{N}\text{\_}\mathrm{d}}{N}_{\mathrm{d}}{A}_{\mathrm{d}}}}$$

(6)

µ_{N_d} can be expressed as (7).

$${\mu }_{\mathrm{N}\text{\_}\mathrm{d}}=947{\left(1+{\displaystyle \frac{N_{\mathrm{d}}}{1.94\times {10}^{17}}}\right)}^{-0.61}{\left({\displaystyle \frac{T_{\mathrm{j}}}{T_0}}\right)}^{-2.15}$$

(7)

R_S is defined as the R_ON excluding R_CH [34], and its main components are R_JFET and R_D.

2.2. Effect of Gate Oxide Degradation on R_ON

2.2.1. Mechanism of Gate Oxide Degradation

The gate oxide degradation of SiC MOSFETs is one of the most common chip-level degradation modes and can be classified into two types: time-dependent dielectric breakdown (TDDB) and single-event gate rupture (SEGR) [25]. TDDB is the more significant failure mechanism in most applications, which arises mainly from defect accumulation within the gate oxide. TDDB is the more prominent failure mechanism in most applications, primarily caused by the accumulation of defect charges in the oxide layer.

2.2.2. Impact of Gate Oxide Degradation on V_TH, µ_N, and R_ON

Among the factors contributing to TDDB, both Q_it and Q_ot primarily lead to a reduction in mobility in the SiC MOSFET channel and variations in the threshold voltage. During electron injection into the oxide layer via tunneling, the electrons are captured by near-interface traps (NITs) with energy levels below the conduction band, forming stable negative charges. The accumulation of these negatively charged Q_it compensates for the effect of the oxide field. Consequently, a higher electric field is required across the oxide to maintain the channel, which leads to an increase in V_TH.

The empirical expression modeling the effect of the gate oxide degradation mechanism on V_TH shift is given by (8) [35], where the specific shift in V_TH can be defined as ΔV_{TH_drift}.

$$\mathrm{\Delta }{V}_{\mathrm{TH}\text{\_}\mathrm{drift}}=-{\displaystyle \frac{\mathrm{\Delta }{Q}_{\mathrm{ot}}}{C_{\mathrm{OX}}}}+{\displaystyle \frac{\mathrm{\Delta }{Q}_{\mathrm{it}}}{C_{\mathrm{OX}}}}$$

(8)

Meanwhile, the accumulation of both Q_ot and Q_it significantly impacts channel carrier mobility, resulting in a direct reduction in µ_N [36]. The primary mechanism through which Q_it affects this reduction is charge scattering, which directly contributes to mobility degradation [35]. The empirical expression modeling the effect of the gate oxide degradation mechanism on channel mobility is given by (9) [37], which is based on the Single Transistor Mobility Technique.

$${\mu }_{\mathrm{N}}={\displaystyle \frac{{\mu }_{\mathrm{N}0}}{1+{\alpha }_{\mathrm{ot}}\frac{\mathrm{\Delta }{Q}_{\mathrm{ot}}}{q}+{\alpha }_{\mathrm{it}}\frac{\mathrm{\Delta }{Q}_{\mathrm{it}}}{q}}}$$

(9)

It can be observed that as the gate degrades, the accumulation of Q_it increases, exacerbating this effect and further reducing µ_N. Therefore, gate oxide degradation not only affects V_TH but also deteriorates electron mobility.

C_OX is the capacitance of the gate oxide layer, determined by the physical dimensions of the gate oxide layer and the permittivity of SiO₂ [36]. It remains unaffected by gate degradation and T_j variations. L_CH and W_CELL are the physical structural dimensions of the SiC MOSFET, which remain constant after chip fabrication and remain unaffected by temperature variations and gate degradation.

As the gate oxide layer of SiC MOSFETs degrades, µ_N exhibits a significant decline, while V_TH shows a clear increase. Meanwhile, C_OX, L_CH, and W_CELL remain unaffected during this process. Based on (2), it can be inferred from the analysis that R_CH increases with gate degradation. In contrast, according to (5) and (6), R_D and R_JFET are unaffected by gate degradation, indicating that R_S is not significantly influenced by gate degradation.

Therefore, it can be inferred that changes in the R_CH component of R_ON in SiC MOSFETs can serve as a reliable indicator for assessing gate degradation.

2.3. Effect of Temperature on R_ON

2.3.1. Effect of Temperature on V_TH, µ_N, and R_ON

The temperature characteristic of V_TH can be analyzed based on (4), which shows that it decreases as the temperature increases, as already analyzed in [10]. µN is primarily influenced by surface roughness scattering, which increases with temperature (approximately below 170 °C) [32]. C_OX, L_CH, and W_CELL remain unchanged with temperature, which are dependent on the physical parameters of SiC MOSFETs structure.

As a result, based on (2), R_CH exhibits a negative temperature coefficient and decreases with increasing temperature, as also verified by [38].

2.3.2. Effect of Temperature on R_S

In (7), N_d represents the donor doping concentration, which refers to the fixed number of donor atoms introduced during the doping process to supply free electrons. N_d does not vary with temperature, as it is a fixed physical quantity determined by the doping process. According to (7), the mobility μ_{N_d} decreases exponentially with increasing temperature, exhibiting a significant negative temperature dependence. Based on (6), R_D is inversely proportional to μ_{N_d}. Therefore, as temperature increases, the reduction in mobility directly leads to a significant increase in R_D with rising T_j.

This analysis indicates that R_D exhibits favorable temperature characteristics, which have also been validated in [38,39]. Since R_D is the primary component of R_S, it makes R_S a reliable parameter for predicting junction temperature.

2.4. Derivation of the R_ON Model

This chapter presents a R_ON equation that characterizes the effects of gate degradation and T_j on R_ON, thereby facilitating the use of R_ON to predict gate degradation and T_j.

2.4.1. Derivation of the Expression for μ_N

μ_N is influenced by V_G and temperature [32], which can be described by the empirical Equation (10) [30]. μ_N is also influenced by gated oxide degradation, as previously explained in (8) and (9).

$${\mu }_{\mathrm{N}}={\displaystyle \frac{{\mu }_{\mathrm{N}0}}{1+\theta (V_{\mathrm{G}}-V_{\mathrm{TH}})}}$$

(10)

According to [10,22], when the gate is subjected to positive stress, V_TH exhibits a positive shift. This is because, after a certain period of gate degradation, interface traps become dominant. These traps interact with charge carriers and capture electrons, resulting in the formation of negative charges in n-channel MOSFETs, which has been introduced in Section II. Due to Q_it dominating in the V_TH shift instead of Q_ot [35], (8) can be simplified to (11),

$$\mathrm{\Delta }{V}_{\mathrm{TH}\text{\_}\mathrm{drift}}=-{\displaystyle \frac{\mathrm{\Delta }{Q}_{\mathrm{ot}}}{C_{\mathrm{OX}}}}+{\displaystyle \frac{\mathrm{\Delta }{Q}_{\mathrm{it}}}{C_{\mathrm{OX}}}}\approx {\displaystyle \frac{\mathrm{\Delta }{Q}_{\mathrm{it}}}{C_{\mathrm{OX}}}}$$

(11)

Meanwhile, based on the approach described in [37], α_it >> α_ot and Q_it dominates [36], after which (5) can be simplified to

$${\mu }_{\mathrm{N}}={\displaystyle \frac{{\mu }_{\mathrm{N}0}}{1+({\alpha }_{\mathrm{ot}}\mathrm{\Delta }{Q}_{\mathrm{ot}}+{\alpha }_{\mathrm{it}}\mathrm{\Delta }{Q}_{\mathrm{it}})/q}}\approx {\displaystyle \frac{{\mu }_{\mathrm{N}0}}{1+{\alpha }_{\mathrm{it}}\mathrm{\Delta }{Q}_{\mathrm{it}}/q}}$$

(12)

By substituting (11) into (12) and replacing the unknown variable α_it, C_OX, and q with a new parameter, k_{un_aged}, (13) can be obtained.

$${\mu }_{\mathrm{N}}={\displaystyle \frac{{\mu }_{\mathrm{N}0}}{1+{\alpha }_{\mathrm{it}}{C}_{\mathrm{OX}}\mathrm{\Delta }{V}_{\mathrm{TH}\text{\_}\mathrm{drift}}/q}}={\displaystyle \frac{{\mu }_{\mathrm{N}0}}{1+k_{\mathrm{un}\text{\_}\mathrm{aged}}\mathrm{\Delta }{V}_{\mathrm{TH}\text{\_}\mathrm{drift}}}}$$

(13)

Based on (13), the impact of gate degradation on µ_N can be calculated based on V_TH drift. This approach enables ΔV_{TH_drift} to simultaneously characterize the changes in both µ_N and V_TH during gate degradation. The key advantage of this method is that it allows the monitoring of two critical parameters using a single variable, ΔV_TH, simplifying the evaluation process and reducing the reliance on additional measurement techniques.

In summary, the expression incorporating the effects of gate degradation, T_j, and V_G on µ_N is derived and presented in (14).

$${\mu }_{\mathrm{N}}={\displaystyle \frac{{\mu }_{\mathrm{N}0}}{(1+k_{\mathrm{un}\text{\_}\mathrm{aged}}\mathrm{\Delta }{V}_{\mathrm{TH}\text{\_}\mathrm{drift}})(1+\theta (V_{\mathrm{G}}-V_{\mathrm{TH}}))}}$$

(14)

At high gate voltages, surface roughness scattering consistently dominates the behavior of carrier mobility (u_N0) across a wide temperature range, and its value remains nearly independent of temperature [32]. In addition, the extracted mobility values from the tested devices in this study also demonstrate a weak dependence of u_N0 on temperature. To facilitate the subsequent model formulation and parameter extraction while maintaining high modeling accuracy in high-temperature operating regimes, u_N0 is treated as a temperature-independent constant in this work.

2.4.2. Derivation of the Expression for R_ON

The I_DS have a relationship with V_G, V_TH, V_CH, and other parameters as proposed in (15) [29].

$$I_{\mathrm{DS}}={\displaystyle \frac{W_{CELL}{C}_{\mathrm{OX}}}{L_{\mathrm{CH}}}}{\mu }_{\mathrm{N}}[V_{\mathrm{G}}-V_{\mathrm{TH}}-0.5V_{\mathrm{CH}}]V_{\mathrm{CH}}$$

(15)

By substituting (14) into (15) and accounting for the short-channel effect λ [40], while replacing the temperature- and gate degradation-independent terms C_OX, L_CH, and W_CELL, as well as u_N0, with a parameter k, the final R_ON model, as given in (16), can be obtained.

$$\begin{array}{l}{I}_{\mathrm{DS}}={\displaystyle \frac{k}{(1+k_{\mathrm{un}\text{\_}\mathrm{aged}}\mathrm{\Delta }{V}_{\mathrm{TH}\text{\_}\mathrm{drift}})}}{\displaystyle \frac{(V_{\mathrm{G}}-V_{\mathrm{TH}}-0.5V_{\mathrm{CH}})V_{\mathrm{CH}}(1+\lambda V_{\mathrm{CH}})}{1+\theta (V_{\mathrm{G}}-V_{\mathrm{TH}})}}\\ V_{\mathrm{CH}}=V_{\mathrm{DS}}-R_{\mathrm{S}}{I}_{\mathrm{DS}}=I_{\mathrm{DS}}{R}_{\mathrm{ON}},k={\displaystyle \frac{W_{CELL}{C}_{\mathrm{OX}}}{L_{\mathrm{CH}}}}{\mu }_{\mathrm{N}0}\end{array}$$

(16)

3. Proposed Evaluation Strategy for Gate Degradation and T_j

This section consists of two parts. The first part introduces the parameter calculation method for the R_ON model, while the second part presents the gate degradation prediction and T_j prediction methods based on the R_ON model.

3.1. Parameter Calculation of R_ON Model

The parameters of the R_ON model can be calculated based on the process, which is illustrated in Figure 2. Both test data before and after gate degradation (110 h HTGB) are used, with the latter applied to calculate k_{un_aged}, and the details are as below:

• Step 1: DPT and Measurement Aggregation

DPT needs to be conducted under different temperatures, I_DS, and two different V_G, with the specific testing conditions detailed in Section 4. The measurement is aggregated based on the level of gate oxide degradation, temperature, I_DS, and V_G.

2.

Step 2~3: Parameter Classification and Initialization

A parameter calculation method based on nonlinear least-squares optimization is proposed. It combines global variables and local variables. The global variables (k, θ, and k_{un_aged}) are the parameters that are not affected by temperature based on the analysis in Section 2, while the local variables (λ and R_S) are temperature-dependent. This means that, at the same level of gate degradation, under varying temperatures, gate voltages, and currents, the global variables remain constant, while the local variables change with temperature. The variation characteristics of the local variables are consistent with the physical properties of the parameters analyzed in Section 2.

The ΔV_TH is the parameter to indicate the gate oxide degradation that is used to calculate the parameter k_un-age. Initial values for these parameters are needed and constrained within predefined bounds to ensure the physical significance and convergence of the algorithm.

3.

Step 4: Model Accuracy Validation

Due to the nonlinearity of R_ON model, it is difficult to solve directly through the equation. Therefore, an error function is designed to quantify the deviation between the calculated values and experimental data. A computational program based on MATLAB’s nonlinear least-squares solver is developed, which adjusts both global and local parameters to minimize the error. Through iterative calculations, the solution for the conduction impedance model parameters is obtained by minimizing the total error between the calculated and measured R_ON. The residuals provide a quantitative measure of the model’s fit to the experimental data, validating its overall performance.

Finally, the temperature-independent parameters k, θ, and k_{un_aged} are calculated. Simultaneously, the values of variables (V_TH, λ, and R_S) at different temperatures are determined, and their temperature functions are established and named f_VTH, f_λ, and f_RS, respectively. The R_ON model is then constructed according to (16).

3.2. Prediction Method for Junction Temperature and Gate Degradation

The flowchart for estimating the gate degradation and T_j is shown in Figure 3. Based on the R_ON model, if T_j is known, V_TH becomes the only unknown parameter, which can be calculated directly and used to accurately assess the gate degradation level. Similarly, if the gate degradation level (ΔV_{TH_drift}) is known, the T_j can also be accurately calculated because the parameters V_TH, λ, and R_S can be expressed as functions of T_j, which has been calculated. However, in industrial applications, both the T_j and gate degradation levels are unknown.

To solve this, two sets of I_DS and V_DS with two different V_GS at the same temperature are required, denoted as I_DS1, V_DS1, I_DS2, and V_DS2. By substituting these two sets of data into (16), two nonlinear equations are obtained, from which the two unknowns, T_j and ΔV_{TH_drift}, can be simultaneously solved. Solving these nonlinear equations typically requires significant computational resources. To address this, a trial-and-error method is employed in this study. The process is as follows:

First, the ΔV_{TH_drift} matrix (ΔV_TH-M) is defined to represent the V_TH offset calculation range, while the T_j matrix (T_j_M) represents the temperature range for T_j calculation. Both matrices are one-dimensional, with values incremented by their respective step sizes, and their lengths denoted as n1 and n2, respectively. The range of ΔV_TH-M is set from 0 V to 2 V, with a step size of 0.1 V, and the range of T_j_M is from 30 °C to 170 °C, with a step size of 0.01 °C.

Next, under the condition of V_GS = V₁, the matrix of R_ON named (R_{ON1_M}) is calculated by substituting the measured I_DS1 and I_DS2 into the R_ON model, along with the assumed ΔV_TH-M and T_{j_M}. In each iteration, the rows represent variations in ΔV_TH-M, while the columns represent variations in T_{j_M}. This method results in a matrix representing the calculated R_ON values for the given ΔV_TH-M and T_{j_M}.

Third, the difference between R_{ON1_M} and the actual measured R_ON1 is calculated and recorded as error_R_{ON1_M} (17). Similarly, under the condition of V_G = V₂, the measured I_DS2 and V_DS2 are substituted into R_ON model, and the same method is applied to calculate the error between calculation and measurement, named error_R_{ON2_M}.

$$\begin{array}{l}\mathrm{error}\text{\_}{R}_{\mathrm{ON}1}=R_{\mathrm{ON}1}-R_{\mathrm{ON}1\text{-}\mathrm{M}}\\ \mathrm{error}\text{\_}{R}_{\mathrm{ON}2}=R_{\mathrm{ON}2}-R_{\mathrm{ON}2\text{-}\mathrm{M}}\\ \mathrm{error}\text{\_}{R}_{\mathrm{ON}}=\left|error\text{\_}{R}_{\mathrm{ON}1}\right|+\left|error\text{\_}{R}_{\mathrm{ON}2}\right|\end{array}$$

(17)

Fourth, the total error (error_R_ON) is computed based on (17), and the corresponding matrix indices a1 and b1 are identified where the error is minimized. The minimum error_R_ON occurs when the calculated values of R_ON1 and R_ON2, derived from ΔV_TH-M (a1) and T_{j_M} (b1) under the conditions of V_GS1 and V_GS2, exhibit the least deviation from the measured values. Therefore, ΔV_TH-M (a1) and T_{j_M} (b1) are taken as the estimated values for ΔV_{TH_drift} and T_j, respectively.

Figure 4 illustrates the process of applying the previously described calculation method in actual computations. By inputting V_G1, I_DS1, V_DS1, V_G2, I_DS2, and V_DS2, along with the known R_ON model, the variation in error_R_ON is calculated under different assumptions of T_j and ΔV_TH. The minimum R_ON occurs when T_j = 100 °C and ΔV_TH = 0.4 V, where the R_ON1 and R_ON2 calculated using the R_ON model exhibit the smallest deviation from the actual measured values. This minimum value of error_R_ON indicates that, at this point, the calculated R_ON at the two gate voltages exhibits the smallest error compared to the actual test values. For clarity, the calculations shown in the figure are based on a V_TH step size of 0.2 V, with an actual calculation step size of 0.01 V.

4. Experimental Methodology

4.1. Design of Gate Drive Circuit

To obtain two sets of I_DS and V_DS with two different V_G at the same temperature, a two-level, turn-on gate drive circuit is designed, capable of completing the V_G transition within 1 µs. During this transition, the T_j of the SiC MOSFET is assumed to remain constant. Therefore, two sets of I_DS and V_DS values before and after the gate voltage transition can be measured. It mainly consists of three modules, the control module, the gate drive module, and the V_DS detection module, as illustrated in Figure 5 [41].

In the gate drive module, S₁ and S₂ are controlled by the FPGA to achieve efficient and rapid voltage switching, enabling precise control of the turn-on and turn-off states of the SiC MOSFET.

For the V_DS detection module, a silicon-based, high-voltage fast recovery diode STTH112 is used to block the DC voltage. This diode is silicon-based and, therefore, does not experience gate degradation. The impact of temperature variations on the forward voltage drop (V_F) of D₁ is mitigated using a compensation technique with a diode of the same type (D₁₁). Both D₁ and D₁₁ are exposed to identical thermal conditions and have similar current conditions, ensuring that the forward voltages of D₁ and D₁₁ are similar. In this circuit, R₁, R₁₁, R₂, and R₁₂ have the same values, allowing AD_VDS to be calculated as (18) [41]:

$$\mathrm{AD}\text{\_}{V}_{\mathrm{DS}}=V_{\mathrm{DS}}+V_{\mathrm{F}\text{\_}\mathrm{D}1}-V_{\mathrm{F}\text{\_}\mathrm{D}11}=2(V_{\mathrm{DS}\text{\_}\mathrm{AD}}-V_{\mathrm{REF}})$$

(18)

To reduce noise in the sampling circuit, a FIR filter is applied in the calculation of V_DS, effectively mitigating high-frequency noise interference. The actual switching curve of V_G is shown in Figure 6. It shows that the switching of V_G is completed within 1 μs and the V_DS-AD has a significant drop at the same time, which is also stabilized in 1 μs. The reason for the V_DS-AD dropping is that R_CH decreases as V_G increases, which has already been analyzed in (8). This measurement process is performed within one PWM period by the gate drive circuit, without affecting the actual control signals. Additionally, this action has minimal impact on the conduction losses of the SiC MOSFET due to its short duration, lasting only a few microseconds when gate degradation level and T_j estimation are required, with negligible increases in conduction loss (since both V₁ and V₂ are higher than V_TH). This approach can be integrated into the drive circuit, requiring no specific timing or additional control strategies, which has great significance for practical applications.

4.2. Experimental Configuration for R_ON Model Extraction Based on DPT Measurement

A half-bridge inverter based on SiC MOSFETs has been constructed, including a high-voltage power supply, heating equipment, inductive load, power board, and gate driver board, as shown in Figure 7. The current probe N2779A, voltage probe N2790A, and oscilloscope (Agilent MSO44) are used to capture the I_DS, V_REF, and V_DS-AD. An electric heating plate (BK946S) is used to heat the DUT to the set temperature, and a thermocouple is attached to the DUT for temperature verification. The configuration of the experimental equipment and the test conditions are shown in

Table 1. Test information for the R_ON model.

Items	Details/Information
Test Temperature	50 °C, 70 °C, 90 °C, 116 °C, 132 °C, 148 °C
Test Current	DUT1: 6–18 A
HTGB Hours	DUT1: Non-aged, 110 h;
UDC	200~300 V
Inductor	2 mH
Gate Voltage	V1 = 12 V, V2 = 16.2 V
Information of DUT1	SCT3080KR(ROHM) with trench gate structure.

.

4.3. Experimental Configuration for Validation of the Proposed Method in the DC-DC Converter

To verify the effectiveness of the proposed strategy, this paper designed an experimental method based on a DC-DC converter to evaluate T_j and gate degradation. A SiC MOSFET from ROHM, model SCT3080KR, was selected, featuring a typical voltage rating of 1200 V, a typical R_DS of 80 mΩ at 25 °C, and I_DS of 22 A at 100 °C. The experimental setup is also illustrated in Figure 7, and the topology of the converter is a boost circuit. The control circuit utilized a DSP (model: TMS320F28335) to generate control signals by monitoring input and output voltages. The input bus voltage was fixed at 100 V, with the duty cycle ranging from 0.5 to 0.7, and the output voltage was adjusted according to the duty cycle. To accommodate the DUT’s current-carrying capability, the duty cycle was adjusted to regulate the inductor current, resulting in a current range of 10.5 A to 18 A flowing through the SiC MOSFET before and after the gate transition. Additionally, the experimental temperature range was set to 50~150 °C. The details are listed in

Table 2. Key information of invertor test for DUT1.

Items	Details Information
Test Temperature	50 °C, 70 °C, 90 °C, 116 °C, 132 °C, 148 °C
Test Current	DUT1, 10.5–18 A
HTGB Hours	173 h;
DUT1	SCT3080KR (ROHM)
Input Voltage	100 V
Output Voltage	200~330 V
Inductor Value	2 mH
Load	20 Ω
Gate Voltage	V1 = 12 V, V2 = 16.2 V
Switching Frequency	10 kHz
Capacitor for Input	470 uF (Aluminum capacitor), 2.2 uF × 2(PP film capacitor)
Capacitor for Output	220 uF (Aluminum capacitor), 2.2 uF × 2(PP film capacitor)
DSP	TMS320F28335
FPGA	10M08SCE144I7G

.

4.4. Experimental Configuration for Accelerated Testing of Gate Oxide Degradation

To evaluate the impact of gate oxide degradation on device performance and reliability, this paper adopts the High-Temperature Gate Bias (HTGB) test as the accelerated degradation method. Following the JEDEC standard (JESD22-A108D) [42], the HTGB test applies high electric field stress under elevated temperatures to simulate the operational stress experienced by devices during prolonged usage, thereby accelerating the degradation of the gate oxide [25]. In this experiment, the test conditions were set to a V_GS of 30 V and a temperature of 175 °C. These conditions ensure that the experimental results accurately reflect the actual influence of gate degradation on device performance, providing reliable data for further analysis.

To simulate long-term operational degradation, the DUT underwent five HTGB aging tests. After each aging test, a V_TH extraction test was conducted to measure and analyze the changes in V_TH of the DUT at different stages of degradation. After the first and third aging tests, DPT experiments were performed to measure and analyze the variations in R_ON at different degradation stages, which were also used to establish the R_ON model. After the fifth aging test, the DUT was installed in a DC-DC inverter for continuous pulse testing to validate the effectiveness and reliability of the proposed method.

5. Experimental Verification

This section includes five experimental results: (1) the extraction of V_TH under different accelerated aging times, (2) the results of the double-pulse test, (3) the extraction of on-resistance based on the double-pulse test, (4) the prediction of junction temperature aging and gate degradation aging based on the double-pulse test, and (5) the prediction results of junction temperature and gate aging based on the DC-DC converter.

5.1. Experimental Results of V_TH Extraction and Gate Oxide Degradation

Figure 8 illustrates the variations in the V_TH under different temperatures and degradation levels, with the calculations based on the transfer characteristics curve measured by B1505. It can be observed that, regardless of whether the device is degraded or not, V_TH consistently decreases with increasing temperature. Furthermore, under gate degradation conditions, the magnitude of V_TH shift increases significantly as the level of degradation intensifies, which aligns with the theoretical analysis presented in (8).

5.2. Experimental Results of DPT Test

Figure 9 illustrates the R_ON of the DUT before and after the aging test, which was obtained through DPT under varying V_G, I_DS, and T_j conditions. The results show that R_ON increases with rising T_j, while it significantly decreases as V_G increases. This demonstrates the contrasting influence of T_j and V_G on the R_ON of the device.

5.3. Experimental Results of R_ON Model Calculation

The R_ON model of the DUT1 was calculated based on the method described in Section 3 and the experimental data obtained in the previous section. The calculated results for the key parameters of the R_ON model are listed in (19).

$$\begin{array}{l}{f}_{\mathrm{Rs}}=2.45\times {10}^{-6}{T}_{\mathrm{j}}^2+1.17\times {10}^{-4}{T}_{\mathrm{j}}-0.0022\\ f_{\mathsf{\lambda }}=-4.2\times {10}^{-8}{T}_{\mathrm{j}}^3+1.35\times {10}^{-5}{T}_{\mathrm{j}}^2-9.7\times {10}^{-4}{T}_{\mathrm{j}}+0.021\\ f_{\mathrm{TH}}=-0.0167T_{\mathrm{j}}+6.88\\ k=2.526,k_{\mathrm{un}\text{\_}\mathrm{aged}}=0.073,\theta =0.087\end{array}$$

(19)

To validate the accuracy of the model, the calculated R_ON with the model was compared with the experimentally measured values. The results for new and 110 h-aged were in Figure 10a and 10b, respectively. The comparison error is defined as k_error and its calculation method is shown in (20).

$$k_{error}={\displaystyle \frac{|R_{\mathrm{ON}\text{\_}\mathrm{Calculation}}-R_{\mathrm{ON}\text{\_}\mathrm{DPT}}|}{R_{\mathrm{ON}\text{\_}\mathrm{DPT}}}}$$

(20)

5.3.1. Without Gate Oxide Degradation Conditions

In the I_DS range of 5 A to 18 A and T_j range of 50 °C to 160 °C, the relative error between calculation and measurement remained within 3%, as shown in Figure 10a. This indicates that the model demonstrates high accuracy and reliability under non-degraded conditions.

5.3.2. Under Gate Oxide Degradation Conditions

When gate degradation occurs at 110 h, the R_ON values calculated using the same model were compared with the measured values shown in Figure 10b. The results indicate that even under gate degradation, the calculated R_ON values maintain accuracy within a 4% error margin. The proposed conduction impedance model exhibits excellent accuracy under both non-degraded and gate-degraded conditions, with the error consistently controlled within 4%.

5.4. Prediction Results of Gate Oxide Degradation and T_j Based on DPT

5.4.1. The Explanation of the Calculation Process for Gate Degradation and T_j

Based on the known relationship between the parameters of the R_ON model and temperature, ΔV_{TH_drift} and T_j are solved to minimize the error between the R_ON model results and the actual test data (minimize error_R_ON). The corresponding values of ΔV_{TH_drift} and T_j at the minimum error represent the final solution. Taking the prediction of ΔV_{TH_drift} and T_j after 110 h of HTGB at 146 °C as an example, Figure 11 shows the variations in error_R_ON (the sum of the absolute errors between the calculated R_ON1 and R_ON2) under different ΔV_TH and T_j assumptions. It can be observed that when ΔV_{TH_drift} is 0.4 V and T_j is 148.1 °C, the error_R_ON reaches its minimum value. The predicted results at this point closely match the actual T_j of 146 °C and V_TH deviation of 0.5 V (Figure 8), validating the effectiveness of this method for predicting gate degradation and junction temperature.

5.4.2. Experimental Conditions and Results

The gate degradation and T_j of the device are predicted under different temperatures, gate degradation levels, and current conditions based on DPT. For both before aging and after 110 h of aging, the gate degradation and T_j of DUT1 were predicted at six temperatures between 70 °C and 168 °C. At each temperature, six current levels were selected. The prediction results are presented in Figure 12 and Figure 13.

The prediction results for gate degradation and T_j within the temperature range of 69 °C to 170 °C for the non-aged DUT are presented in Figure 12. Specifically, Figure 12a illustrates the estimation results of T_j, while Figure 12b shows the results for V_TH. The results indicate that, for the non-aged DUT, the accuracy of the V_TH is less than 0.1 V from 70 °C to 170 °C; this is because the effect of gate degradation on R_ON is characterized to possess V_TH. At the same time, the maximum absolute error of the estimation remains below 5 °C when T_j is in the range of 90~150 °C. Moreover, as T_j increases, the accuracy improves significantly, achieving an error range of 2~3 °C at 110 °C~168 °C. The observed improvement is primarily due to the temperature-dependent behavior of the R_D, which plays a dominant role at elevated temperatures, as indicated by (7). The estimated error of T_j at 69 °C is near 9 °C, primarily due to the 3% accuracy of the R_ON model in this temperature range and the relatively small contribution of R_S at lower temperatures based on Figure 10.

Figure 13a presents the T_j and V_TH prediction results after 110 h of HTGB. After 110 h of aging, V_TH exhibits a significant shift from its original value (marked in green) to the aged value (marked in red). The degree of this shift varies at different temperatures, indicated by the purple markings. However, the proposed method calculates V_TH with an error of less than 0.2 V compared to the V_TH measurement, within the temperature range of 69 °C to 169 °C under these aging conditions. This is because the R_ON model uses kun_aged, which expresses the impact of gate degradation on µ_N through V_TH. Therefore, the R_ON model can characterize the impact of gate degradation on R_ON solely through V_TH. The T_j prediction achieves an error of less than 5 °C across the temperature range of 50 °C to 150 °C, maintaining the same level of accuracy as with under unaged conditions. These results validate that the proposed method can simultaneously achieve accurate T_j prediction and gate degradation verification under DPT, across different samples and aging conditions.

5.5. Experimental Results Based on a DC-DC Converter

To validate the accuracy of the method proposed in this paper at the inverter level, DC-DC (boost) inverter-based predictions of gate degradation and T_j were conducted for the test sample under 173 h of gate degradation conditions. The details of the DC-DC inverter have been described in Section 4. The DUT was heated by the hot plate as the initial temperature. Under the same temperature conditions, during the first 20 ms of continuous operation, 10 pulses with varying currents are selected for T_j prediction. The 20 ms duration is chosen because, due to the thermal resistance and capacitance of the MOSFET, the junction temperature of the device remains relatively stable during this period.

Figure 14 displays the waveforms of V_G, V_DS, and I_DS at 145 °C. It can be observed that V_GS increases rapidly while R_ON decreases simultaneously, consistent with the results of the DPT test. Since the FPGA manages the V_G transition command in the gate driver circuit, it can easily perform I_DS1 and V_DS1 sampling before the transition and then capture I_DS2 and V_DS2 1 µs after the V_GS transition. To reduce sampling errors throughout the testing process, three points are selected before and after the transition, and their average values are used for calculating named I_DS and V_DS. This testing and calculation process were repeated under different temperature conditions to ensure the reliability and consistency of the data, with the results shown in Figure 15. Both the V_TH and T_j can be calculated based on (16) and Figure 3, which is the same as the DPT test.

Figure 15a,b present the estimated V_TH and T_j results after 173 h of accelerated gate degradation testing in the DC-DC inverter. It is observed that the maximum error of V_TH is below 0.2 V between 50 and 150 °C, which is slightly higher than that of the unaged and 110 h-aged conditions. This indicates that, although the calculation of k_{un_aged} relies only on data from the unaged and 110 h aging stages, the error in the V_TH calculation at the 173 h aging stage increases by only 0.05 V while still maintaining good accuracy.

5.6. Impact of Voltage and Current on the Proposed Method

The R_ON is insensitive to the DC voltage, which has been verified by [41]. According to (2) and (6), R_ON is sensitive to current variations; however, the R_ON model has effectively characterized the relationship between current and R_ON, which ensures that variations in current do not significantly affect the prediction accuracy. In the validation of both the DPT and DC-DC inverter tests, a different current was used. The current values in the DC-DC tests are shown in Figure 16, with each point corresponding to the current value of the respective point in Figure 15. The blue color represents the average of three sampling points at V_G = V₁, while the red color represents the average of three sampling points at V_G = V₂. The results show that changes in current do not significantly impact the prediction accuracy. This is because the R_ON model effectively decouples the relationship between current and R_ON, thus maintaining the prediction accuracy.

5.7. Gate Oxide Degradation and T_j Prediction Results Based on Planar SiC MOSFET

To validate the effectiveness of this method on planar SiC MOSFETs, DUT 2 was selected for DPT testing. The DPT test method, gate drive circuit, and parameter extraction process are consistent with DUT1. The current of the tested sample has been adjusted according to the rated current of DUT2, and the specific test data is shown in

Table 3. Test information for the R_ON model of DUT2.

Items	Details Information
Test Temperature	70 °C, 90 °C, 116 °C, 132 °C, 148 °C
Test Current	DUT2: 6–12 A
HTGB Hours	DUT2: 0 h, 70 h, 90 h
UDC	200~300 V
Inductor	2 mH
Gate Voltage	V1 = 12 V, V2 = 16.2 V
Information of DUT2	C3M0120100K(CREE) planar gate structure

.

The calculated results for the key parameters of the R_ON model for DUT2 are presented in (21).

$$\begin{array}{l}{f}_{\mathrm{Rs}}=2.64\times {10}^{-6}{T}_{\mathrm{j}}^2+3.21\times {10}^{-5}{T}_{\mathrm{j}}-0.0193\\ f_{\mathsf{\lambda }}=2.86\times {10}^{-8}{T}_{\mathrm{j}}^3-5.2\times {10}^{-6}{T}_{\mathrm{j}}^2+7\times {10}^{-5}{T}_{\mathrm{j}}-0.019\\ f_{\mathrm{TH}}=-0.013T_{\mathrm{j}}+4.9518\\ k=1.84,k_{\mathrm{un}\text{\_}\mathrm{aged}}=0.065,\theta =0.0749\end{array}$$

(21)

The R_ON calculated by the model were compared with the experimentally measured results, with the results for the new sample presented in Figure 17. The error is defined as k_error as provided in (20). As shown within the measurement range in Table 3, the accuracy of the R_ON model is within 5%, which is consistent with the results shown in Figure 10. This demonstrates that the R_ON model extracted using this method maintains accuracy for the unaged condition and is also applicable to planar SiC MOSFET.

For three different gate degradation levels (new, after 70 h of HTGB, and after 96 h of HTGB), the gate degradation and T_j of DUT2 were predicted using the method proposed in this paper at five different temperatures within the range of 70 °C to 148 °C. At each temperature, six different currents were selected for measurement, with the current range provided in Table 3. The corresponding prediction results are shown in Figure 18.

It can be observed that as DUT2 is unaged, the prediction of V_TH within the range of 70 °C to 148 °C demonstrates high accuracy. This is attributed to the fact that the R_ON model was primarily calibrated based on the unaged condition. Additionally, it can be observed that the prediction error of the T_j is within 6 °C, which is due to a certain difference between the R_ON model and the actual test data. After 70 h and 96 h of aging, the prediction error of V_TH is within 0.2 V, except for one point. Although it is slightly larger compared to DUT1, it still accurately characterizes the gate degradation. At this stage, the prediction accuracy of T_j is also within 6 °C, similar to the results of DUT1. Therefore, the above tests demonstrate the effectiveness of the proposed method in different SiC MOSFET structures under varying degrees of gate degradation and junction temperature.

5.8. Comparison of Porposed Method with Conventional R_ON Mapping Methods Without Considering Gate Degradation

Based on the experimental data obtained from unaged devices at a gate voltage of V_G equals 16.2 V, a mapping relationship among R_ON, junction temperature T_j, and current was established. The conventional one-dimensional look-up table method [22], which does not account for gate degradation effects, was then used to predict junction temperature under the conditions shown in Figure 15b. The prediction results were compared with those obtained by the proposed method, as shown in Figure 19.

It is clearly observed that the conventional one-dimensional look-up table method exhibits significantly increased errors after gate degradation. For example, the prediction error at 69 °C reaches 20 °C, which is about 15 °C higher than that of the proposed method. At 160 °C, the average prediction error for the conventional method is 6.9 °C, while the proposed method reduces it to 3.5 °C.

The main reason for the significant decline in accuracy of the conventional method is that it does not consider the effects of gate degradation, specifically the positive shift in threshold voltage and the reduction in carrier mobility, both of which lead to increased channel resistance. At lower temperatures, channel resistance represents a larger proportion of the total R_ON, making R_ON more sensitive to gate degradation effects. Ignoring these effects can easily result in large prediction errors.

In contrast, the proposed R_ON model inherently accounts for these degradation factors, not only significantly improving the accuracy of junction temperature prediction compared to the conventional method, but also enabling quantitative evaluation of gate oxide degradation, thereby improving the accuracy and practical utility of device health assessment.

5.9. The Limitations of the Proposed Method

Package degradation can also alter the relationship between R_ON and temperature. In power second cycling tests of power devices, package degradation increases the contact resistance at the bond wires and die surface, while in minute-level power cycling, it increases the contact resistance at the interface between the chip and substrate. When package degradation occurs, the increase in contact resistance alters the relationship between R_S and temperature, potentially affecting the accuracy of the proposed method. The primary cause of package degradation is related to the packaging process, and its impact can be mitigated through advancements in packaging technologies. For example, the widespread application of silver sintering [43] and direct copper bonding (DTS) technologies in high-reliability applications, such as electric vehicles, has significantly reduced the impact of package degradation on device performance.

Gate degradation is caused by the design of the gate oxide layer in SiC MOSFETs, which requires improvements in the chip design. The method proposed in this paper primarily focuses on the analysis and prediction of gate degradation and does not address package degradation.

To focus on accuracy at a high-temperature range (50–175 °C), this work assumes u_N0 to be temperature-independent. However, this may introduce deviations at lower temperatures due to the increasing role of temperature-dependent scattering mechanisms.

6. Conclusions

This paper primarily investigates the use of the R_ON model for gate oxide degradation and T_j prediction in SiC MOSFETs, addressing the challenge that existing evaluation methods focus on a single aspect and fail to integrate both targets effectively. During operation, variations in R_ON, driven by gate voltage changes, are strongly correlated with both T_j and gate degradation. By extracting the temperature dependencies of the parameters in the R_ON model, all parameters are expressed as functions of temperature, leaving T_j and ΔV_{TH_drift} as the only unknowns. By using two sets of I_DS and V_DS measurements, taken before and after the gate voltage change, both T_j and ΔV_{TH_drift} can be derived from the R_ON model. Experimental results under DPT test conditions, the V_TH prediction error for DUT1 remains within 0.2 V across the temperature range of 70 °C to 140 °C, both before and after 110 h of HTGB. The T_j prediction error is within 6 °C when T_j is above 96 °C. For DUT2, the prediction error of V_TH remains within 0.2 V in the temperature range of 69 °C to 148 °C, under no aging, 70 h of HTGB, and 96 h of HTGB, with T_j prediction accuracy within 6 °C. DUT1 was tested under DC-DC boost inverter conditions after 173 h of HTGB using the proposed method. The V_TH prediction accuracy remained within 0.2 V across the temperature range of 50 °C to 150 °C, consistent with the results obtained under DPT test conditions. These results validate that the proposed method effectively estimates both T_j and gate degradation levels in SiC MOSFETs.

This paper integrates the R_ON model with the gate driver circuit to simultaneously estimate both T_j and V_TH, offering a novel approach for SiC MOSFET reliability assessment. Future work will focus on improving the accuracy of both T_j and V_TH.