Sign in to use this feature.

Years

Between: -

Subjects

remove_circle_outline
remove_circle_outline
remove_circle_outline
remove_circle_outline
remove_circle_outline
remove_circle_outline

Journals

Article Types

Countries / Regions

Search Results (55)

Search Parameters:
Keywords = magnetic tunnel junctions (MTJs)

Order results
Result details
Results per page
Select all
Export citation of selected articles as:
12 pages, 7323 KiB  
Article
WinEdge: Low-Power Winograd CNN Execution with Transposed MRAM for Edge Devices
by Milad Ashtari Gargari, Sepehr Tabrizchi and Arman Roohi
Electronics 2025, 14(12), 2485; https://doi.org/10.3390/electronics14122485 - 19 Jun 2025
Viewed by 396
Abstract
This paper presents a novel transposed MRAM architecture (WinEdge) specifically optimized for Winograd convolution acceleration in edge computing devices. Leveraging Magnetic Tunnel Junctions (MTJs) with Spin Hall Effect (SHE)-assisted Spin-Transfer Torque (STT) writing, the proposed design enables a single SHE current to simultaneously [...] Read more.
This paper presents a novel transposed MRAM architecture (WinEdge) specifically optimized for Winograd convolution acceleration in edge computing devices. Leveraging Magnetic Tunnel Junctions (MTJs) with Spin Hall Effect (SHE)-assisted Spin-Transfer Torque (STT) writing, the proposed design enables a single SHE current to simultaneously write data to four MTJs, substantially reducing power consumption. Additionally, the integration of stacked MTJs significantly improves storage density. The proposed WinEdge efficiently supports both standard and transposed data access modes regardless of bit-width, achieving up to 36% lower power, 47% reduced energy consumption, and 28% faster processing speed compared to existing designs. Simulations conducted in 45 nm CMOS technology validate its superiority over conventional SRAM-based solutions for convolutional neural network (CNN) acceleration in resource-constrained edge environments. Full article
(This article belongs to the Special Issue Emerging Computing Paradigms for Efficient Edge AI Acceleration)
Show Figures

Figure 1

11 pages, 1700 KiB  
Article
Compact Modeling and Exploration of the Light Metal Insertion Effect for a Voltage-Controlled Spin–Orbit Torque Magnetic Tunnel Junction
by Weixiang Li, Jiaqi Lu, Chengzhi Wang and Dongsheng Wang
Electronics 2025, 14(7), 1272; https://doi.org/10.3390/electronics14071272 - 24 Mar 2025
Viewed by 416
Abstract
Magnetic random-access memory, recognized as a breakthrough in spintronics, demonstrates substantial potential for next-generation nonvolatile memory and logic devices due to its unique magnetization-switching mechanism. However, realizing reliable perpendicular magnetization switching via spin–orbit torque necessitates an externally applied in-plane magnetic bias, a requirement [...] Read more.
Magnetic random-access memory, recognized as a breakthrough in spintronics, demonstrates substantial potential for next-generation nonvolatile memory and logic devices due to its unique magnetization-switching mechanism. However, realizing reliable perpendicular magnetization switching via spin–orbit torque necessitates an externally applied in-plane magnetic bias, a requirement that complicates integration in high-density device architectures. This study proposes a novel device architecture where geometric asymmetry engineering in an interlayer design generates an intrinsic equivalent in-plane magnetic field. By strategically introducing a non-symmetrical spacer between the heavy metal and ferromagnetic layers, we establish deterministic magnetization reversal while eliminating external field dependency. Furthermore, the energy barrier during magnetization switching is dynamically adjusted by applying a voltage across a perpendicular-anisotropy magnetic tunnel junction, leveraging the voltage-controlled magnetic anisotropy effect. We established a physics-driven compact model to assess the design and performance of voltage-controlled spin–orbit torque magnetic tunnel junction (VCSOT-MTJ) devices. Simulations reveal that the introduction of a minimally asymmetric light metal layer effectively resolves the issue of incomplete switching in field-free spin-orbit torque systems. Full article
Show Figures

Figure 1

13 pages, 3859 KiB  
Article
Design of a 2–4 Decoder Based on All-Spin Logic and Magnetic Tunnel Junction
by Sen Wang, Yongfeng Zhang and Dan Shan
Magnetochemistry 2025, 11(2), 17; https://doi.org/10.3390/magnetochemistry11020017 - 15 Feb 2025
Viewed by 686
Abstract
A 2–4 decoder based on all-spin logic (ASL) and magnetic tunnel junction (MTJ) is proposed. The decoder employs five-input minority gates to realize three-input NOR gates, which reduces the circuit size compared to the three-input minority gates. Simultaneously, the inputs of the original [...] Read more.
A 2–4 decoder based on all-spin logic (ASL) and magnetic tunnel junction (MTJ) is proposed. The decoder employs five-input minority gates to realize three-input NOR gates, which reduces the circuit size compared to the three-input minority gates. Simultaneously, the inputs of the original and reverse variables are implemented by initializing the MTJ fixed layer magnetization in different directions, which avoids the use of inverters. In addition, the 2–4 decoder adopts a single-input single-fan-out (SISF) structure, which reduces the channel length. To illustrate the advantages of the five-input minority gate, inverter-free structure, and SISF structures in designing the proposed 2–4 decoder, a second 2–4 decoder is proposed that uses three-input minority gates, inverters, and a single-input multiple-fan-out structure. Compared with the second decoder, the first decoder has the layout area reduced to 37.9%, the total channel length reduced to 40.8%, and the number of clock cycles reduced to one-third. Importantly, the design methods used in this work, such as multi-input minority gates, SISF structure, and inverter-free structure, provide an interesting approach for designing large-scale ASL logic circuits. Full article
(This article belongs to the Special Issue Design and Application of Spintronic Devices)
Show Figures

Figure 1

16 pages, 2893 KiB  
Article
Cryo-SIMPLY: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing
by Tatiana Moposita, Esteban Garzón, Adam Teman and Marco Lanuzza
Nanomaterials 2025, 15(1), 9; https://doi.org/10.3390/nano15010009 - 25 Dec 2024
Cited by 1 | Viewed by 1317
Abstract
This paper presents Cryo-SIMPLY, a reliable smart material implication (SIMPLY) operating at cryogenic conditions (77 K). The assessment considers SIMPLY schemes based on spin-transfer torque magnetic random access memory (STT-MRAM) technology with single-barrier magnetic tunnel junction (SMTJ) and double-barrier magnetic tunnel junction (DMTJ). [...] Read more.
This paper presents Cryo-SIMPLY, a reliable smart material implication (SIMPLY) operating at cryogenic conditions (77 K). The assessment considers SIMPLY schemes based on spin-transfer torque magnetic random access memory (STT-MRAM) technology with single-barrier magnetic tunnel junction (SMTJ) and double-barrier magnetic tunnel junction (DMTJ). Our study relies on a temperature-aware macrospin-based Verilog-A compact model for MTJ devices and a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. The DMTJ-based SIMPLY demonstrates a significant improvement in read margin at 77 K, overcoming the conventional SIMPLY scheme at room temperature (300 K) by approximately 2.3 X. When implementing logic operations with the SIMPLY scheme operating at 77 K, the DMTJ-based scheme assures energy savings of about 69%, as compared to its SMTJ-based counterpart operating at 77 K. Overall, our results prove that the SIMPLY scheme at cryogenic conditions is a promising solution for reliable and energy-efficient logic-in-memory (LIM) architectures. Full article
(This article belongs to the Section Nanoelectronics, Nanosensors and Devices)
Show Figures

Figure 1

9 pages, 2190 KiB  
Article
Optimization of Bifurcated Switching by Enhanced Synthetic Antiferromagnetic Layer
by Yihui Sun, Fantao Meng, Junlu Gong, Yang Gao, Ruofei Chen, Lei Zhao, Dinggui Zeng, Ting Fu, Weiming He and Yaohua Wang
Electronics 2024, 13(23), 4771; https://doi.org/10.3390/electronics13234771 - 3 Dec 2024
Viewed by 1003
Abstract
Defects in the free layer are considered to be the main cause of the balloon effect, but there is little insight into the synthetic antiferromagnetic (SAF) layer. To address this shortcoming, in this work, an optimized SAF layer was introduced in the perpendicular [...] Read more.
Defects in the free layer are considered to be the main cause of the balloon effect, but there is little insight into the synthetic antiferromagnetic (SAF) layer. To address this shortcoming, in this work, an optimized SAF layer was introduced in the perpendicular magnetic tunneling junction (pMTJ) stack to eliminate the low-probability bifurcated-switching phenomenon. The results indicated that the Hf field in the film stack improved significantly from ~5700 Oe to ~7500 Oe. A magnetoresistive random access memory (MRAM) test chip was also fabricated with a 300 mm process, resulting in a significantly improved ballooning effect. The results also indicated that the switching voltage decreased by 18.6% and the writing energy decreased by 33.7%. In addition, the low-probability stray field along the x-axis was thought to be the main cause of the ballooning effect, and was experimentally optimized for the first time by enhancing the SAF layer. This work provides a new perspective on spin-flipping dynamics, facilitating a deeper comprehension of the internal mechanism and helping to secure improvements in MRAM performance. Full article
(This article belongs to the Special Issue Advanced CMOS Devices and Applications, 2nd Edition)
Show Figures

Figure 1

24 pages, 972 KiB  
Article
Enhancing Security and Power Efficiency of Ascon Hardware Implementation with STT-MRAM
by Nathan Roussel, Olivier Potin, Grégory Di Pendina, Jean-Max Dutertre and Jean-Baptiste Rigaud
Electronics 2024, 13(17), 3519; https://doi.org/10.3390/electronics13173519 - 4 Sep 2024
Viewed by 1594
Abstract
With the outstanding growth of Internet of Things (IoT) devices, security and power efficiency of integrated circuits can no longer be overlooked. Current approved standards for cryptographic algorithms are not suitable for constrained environments. In this context, the National Institute of Standards and [...] Read more.
With the outstanding growth of Internet of Things (IoT) devices, security and power efficiency of integrated circuits can no longer be overlooked. Current approved standards for cryptographic algorithms are not suitable for constrained environments. In this context, the National Institute of Standards and Technology (NIST) started a lightweight cryptography (LWC) competition to develop new algorithm standards that can be fit into small devices. In 2023, NIST has decided to standardize the Ascon family for LWC. This algorithm has been designed to be more resilient to side-channel and fault-based analysis. Nonetheless, hardware implementations of Ascon have been broken by multiple statistical fault analysis and power analysis. These attacks have underlined the necessity to develop adapted countermeasures to side-channel and perturbation-based attacks. However, existing countermeasures are power and area consuming. In this article, we propose a new countermeasure for the Ascon cipher that does not significantly increase the area and power consumption. Our architecture relies on the nonvolatile feature of the Magnetic Tunnel Junction (MTJ) that is the single element of the emerging Magnetic Random Access Memories (MRAM). The proposed circuit removes the bias exploited by statistical attacks. In addition, we have duplicated and complemented the permutation of Ascon to enhance the power analysis robustness of the circuit. Besides the security aspect, our circuit can save current manipulated data, ensuring energy saving from 11% to 32.5% in case of power failure. The area overhead, compared to an unprotected circuit, is ×2.43. Full article
(This article belongs to the Special Issue Advanced Memory Devices and Their Latest Applications)
Show Figures

Figure 1

17 pages, 12303 KiB  
Article
Optimization of Magnetic Tunnel Junction Structure through Component Analysis and Deposition Parameters Adjustment
by Crina Ghemes, Mihai Tibu, Oana-Georgiana Dragos-Pinzaru, Gabriel Ababei, George Stoian, Nicoleta Lupu and Horia Chiriac
Materials 2024, 17(11), 2554; https://doi.org/10.3390/ma17112554 - 25 May 2024
Cited by 2 | Viewed by 1597
Abstract
In this work, we focus on a detailed study of the role of each component layer in the multilayer structure of a magnetic tunnel junction (MTJ) as well as the analysis of the effects that the deposition parameters of the thin films have [...] Read more.
In this work, we focus on a detailed study of the role of each component layer in the multilayer structure of a magnetic tunnel junction (MTJ) as well as the analysis of the effects that the deposition parameters of the thin films have on the performance of the structure. Various techniques including atomic force microscopy (AFM), scanning electron microscopy (SEM), and transmission electron microscopy (TEM) were used to investigate the effects of deposition parameters on the surface roughness and thickness of individual layers within the MTJ structure. Furthermore, this study investigates the influence of thin films thickness on the magnetoresistive properties of the MTJ structure, focusing on the free ferromagnetic layer and the barrier layer (MgO). Through systematic analysis and optimization of the deposition parameters, this study demonstrates a significant improvement in the tunnel magnetoresistance (TMR) of the MTJ structure of 10% on average, highlighting the importance of precise control over thin films properties for enhancing device performance. Full article
(This article belongs to the Special Issue Preparation of Thin Films by PVD/CVD Deposition Techniques)
Show Figures

Figure 1

20 pages, 2278 KiB  
Review
Progress in Spin Logic Devices Based on Domain-Wall Motion
by Bob Bert Vermeulen, Bart Sorée, Sebastien Couet, Kristiaan Temst and Van Dai Nguyen
Micromachines 2024, 15(6), 696; https://doi.org/10.3390/mi15060696 - 24 May 2024
Cited by 4 | Viewed by 2671
Abstract
Spintronics, utilizing both the charge and spin of electrons, benefits from the nonvolatility, low switching energy, and collective behavior of magnetization. These properties allow the development of magnetoresistive random access memories, with magnetic tunnel junctions (MTJs) playing a central role. Various spin logic [...] Read more.
Spintronics, utilizing both the charge and spin of electrons, benefits from the nonvolatility, low switching energy, and collective behavior of magnetization. These properties allow the development of magnetoresistive random access memories, with magnetic tunnel junctions (MTJs) playing a central role. Various spin logic concepts are also extensively explored. Among these, spin logic devices based on the motion of magnetic domain walls (DWs) enable the implementation of compact and energy-efficient logic circuits. In these devices, DW motion within a magnetic track enables spin information processing, while MTJs at the input and output serve as electrical writing and reading elements. DW logic holds promise for simplifying logic circuit complexity by performing multiple functions within a single device. Nevertheless, the demonstration of DW logic circuits with electrical writing and reading at the nanoscale is still needed to unveil their practical application potential. In this review, we discuss material advancements for high-speed DW motion, progress in DW logic devices, groundbreaking demonstrations of current-driven DW logic, and its potential for practical applications. Additionally, we discuss alternative approaches for current-free information propagation, along with challenges and prospects for the development of DW logic. Full article
(This article belongs to the Special Issue Magnetic and Spin Devices, 3rd Edition)
Show Figures

Figure 1

10 pages, 2637 KiB  
Communication
A Radiation-Hardened Triple Modular Redundancy Design Based on Spin-Transfer Torque Magnetic Tunnel Junction Devices
by Shubin Zhang, Peifang Dai, Ning Li and Yanbo Chen
Appl. Sci. 2024, 14(3), 1229; https://doi.org/10.3390/app14031229 - 1 Feb 2024
Cited by 1 | Viewed by 1840
Abstract
Integrated circuits suffer severe deterioration due to single-event upsets (SEUs) in irradiated environments. Spin-transfer torque magnetic random-access memory (STT-MRAM) appears to be a promising candidate for next-generation memory as it shows promising properties, such as non-volatility, speed, and unlimited endurance. One of the [...] Read more.
Integrated circuits suffer severe deterioration due to single-event upsets (SEUs) in irradiated environments. Spin-transfer torque magnetic random-access memory (STT-MRAM) appears to be a promising candidate for next-generation memory as it shows promising properties, such as non-volatility, speed, and unlimited endurance. One of the important merits of STT-MRAM is its radiation hardness, thanks to its core component, a magnetic tunnel junction (MTJ), being capable of good function in an irradiated environment. This property makes MRAM attractive for space and nuclear technology applications. In this paper, a novel radiation-hardened triple modular redundancy (TMR) design for anti-radiation reinforcement is proposed based on the utilization of STT-MTJ devices. Simulation results demonstrate the radiation-hardened performance of the design. This shows improvements in the design’s robustness against ionizing radiation. Full article
(This article belongs to the Special Issue Integrated Circuit Design in Post-Moore Era)
Show Figures

Figure 1

17 pages, 1008 KiB  
Article
Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation
by Prashanth Barla, Hemalatha Shivarama, Ganesan Deepa and Ujjwal Ujjwal
J. Low Power Electron. Appl. 2024, 14(1), 3; https://doi.org/10.3390/jlpea14010003 - 6 Jan 2024
Cited by 2 | Viewed by 3662
Abstract
Hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) circuits based on in-memory-computation (IMC) architecture is considered as the next-generation candidate for the digital integrated circuits. However, the energy consumption during the MTJ write process is a matter of concern in these hybrid circuits. [...] Read more.
Hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) circuits based on in-memory-computation (IMC) architecture is considered as the next-generation candidate for the digital integrated circuits. However, the energy consumption during the MTJ write process is a matter of concern in these hybrid circuits. In this regard, we have developed a novel write circuit for the contemporary three-terminal perpendicular-MTJs that works on the voltage-gated spin orbit torque (VG+SOT) switching mechanism to store the information in hybrid circuits for IMC architecture. Investigation of the novel write circuit reveals a remarkable reduction in the total energy consumption (and energy delay product) of 92.59% (95.81) and 92.28% (42.03%) than the conventional spin transfer torque (STT) and spin-Hall effect assisted STT (SHE+STT) write circuits, respectively. Further, we have developed all the hybrid logic gates followed by nonvolatile full adders (NV-FAs) using VG+SOT, STT, and SHE+STT MTJs. Simulation results show that with the VG+SOT NOR-OR, NAND-AND, XNOR-XOR, and NV-FA circuits, the reduction in the total power dissipation is 5.35% (4.27%), 5.62% (3.2%), 3.51% (2.02%), and 4.46% (2.93%) compared to STT (SHE+STT) MTJs respectively. Full article
(This article belongs to the Special Issue Recent Advances in Spintronics)
Show Figures

Figure 1

13 pages, 2819 KiB  
Article
Equivalent Noise Analysis and Modeling for a Magnetic Tunnel Junction Magnetometer with In Situ Magnetic Feedback
by Aiyu Dou, Ru Bai, Yucheng Sun, Jiakun Tu, Chuanjia Kou, Xin Xie and Zhenghong Qian
Magnetochemistry 2023, 9(10), 214; https://doi.org/10.3390/magnetochemistry9100214 - 29 Sep 2023
Cited by 3 | Viewed by 2304
Abstract
Magnetic tunnel junction (MTJ) sensors have been one of the excellent candidates for magnetic field detection due to their high sensitivity and compact size. In this paper, we design a magnetometer with in situ magnetic feedback consisting of an MTJ sensor. To analyze [...] Read more.
Magnetic tunnel junction (MTJ) sensors have been one of the excellent candidates for magnetic field detection due to their high sensitivity and compact size. In this paper, we design a magnetometer with in situ magnetic feedback consisting of an MTJ sensor. To analyze and evaluate the detectivity of the MTJ magnetometer, a noise model of the MTJ sensor in the magnetometer without magnetic feedback is first developed. Then, the noise model of the MTJ magnetometer with in situ magnetic feedback is also established, including the noises of the MTJ sensor and the signal conditioning circuit, as well as the feedback circuit. The equivalent noise model of the MTJ magnetometer with in situ magnetic feedback is evaluated through nonlinear fitting for the noise voltage spectrum. Although the noise generated by the MTJ sensor is much greater than that of the signal conditioning circuit, the noise introduced by the feedback coils into the MTJ sensor is slightly more than twice that generated by the MTJ sensor itself. The measurement results show that the detectivity of the MTJ magnetometer with in situ magnetic feedback reaches 526 pT/Hz1/2 at 10 Hz. The equivalent noise analysis method presented in this paper is suitable for the detectivity analysis of magnetometers with magnetic feedback. Full article
(This article belongs to the Special Issue New Trends in Spintronic Materials and Devices)
Show Figures

Figure 1

12 pages, 5576 KiB  
Article
Realization of Artificial Neurons and Synapses Based on STDP Designed by an MTJ Device
by Manman Wang, Yuhai Yuan and Yanfeng Jiang
Micromachines 2023, 14(10), 1820; https://doi.org/10.3390/mi14101820 - 23 Sep 2023
Cited by 2 | Viewed by 1715
Abstract
As the third-generation neural network, the spiking neural network (SNN) has become one of the most promising neuromorphic computing paradigms to mimic brain neural networks over the past decade. The SNN shows many advantages in performing classification and recognition tasks in the artificial [...] Read more.
As the third-generation neural network, the spiking neural network (SNN) has become one of the most promising neuromorphic computing paradigms to mimic brain neural networks over the past decade. The SNN shows many advantages in performing classification and recognition tasks in the artificial intelligence field. In the SNN, the communication between the pre-synapse neuron (PRE) and the post-synapse neuron (POST) is conducted by the synapse. The corresponding synaptic weights are dependent on both the spiking patterns of the PRE and the POST, which are updated by spike-timing-dependent plasticity (STDP) rules. The emergence and growing maturity of spintronic devices present a new approach for constructing the SNN. In the paper, a novel SNN is proposed, in which both the synapse and the neuron are mimicked with the spin transfer torque magnetic tunnel junction (STT-MTJ) device. The synaptic weight is presented by the conductance of the MTJ device. The mapping of the probabilistic spiking nature of the neuron to the stochastic switching behavior of the MTJ with thermal noise is presented based on the stochastic Landau–Lifshitz–Gilbert (LLG) equation. In this way, a simplified SNN is mimicked with the MTJ device. The function of the mimicked SNN is verified by a handwritten digit recognition task based on the MINIST database. Full article
(This article belongs to the Special Issue Artificial Intelligence for Micro/Nano Materials and Devices)
Show Figures

Figure 1

11 pages, 2249 KiB  
Article
The Influence of Capping Layers on Tunneling Magnetoresistance and Microstructure in CoFeB/MgO/CoFeB Magnetic Tunnel Junctions upon Annealing
by Geunwoo Kim, Soogil Lee, Sanghwa Lee, Byonggwon Song, Byung-Kyu Lee, Duhyun Lee, Jin Seo Lee, Min Hyeok Lee, Young Keun Kim and Byong-Guk Park
Nanomaterials 2023, 13(18), 2591; https://doi.org/10.3390/nano13182591 - 19 Sep 2023
Cited by 4 | Viewed by 3082
Abstract
This study investigates the effects of annealing on the tunnel magnetoresistance (TMR) ratio in CoFeB/MgO/CoFeB-based magnetic tunnel junctions (MTJs) with different capping layers and correlates them with microstructural changes. It is found that the capping layer plays an important role in determining the [...] Read more.
This study investigates the effects of annealing on the tunnel magnetoresistance (TMR) ratio in CoFeB/MgO/CoFeB-based magnetic tunnel junctions (MTJs) with different capping layers and correlates them with microstructural changes. It is found that the capping layer plays an important role in determining the maximum TMR ratio and the corresponding annealing temperature (Tann). For a Pt capping layer, the TMR reaches ~95% at a Tann of 350 °C, then decreases upon a further increase in Tann. A microstructural analysis reveals that the low TMR is due to severe intermixing in the Pt/CoFeB layers. On the other hand, when introducing a Ta capping layer with suppressed diffusion into the CoFeB layer, the TMR continues to increase with Tann up to 400 °C, reaching ~250%. Our findings indicate that the proper selection of a capping layer can increase the annealing temperature of MTJs so that it becomes compatible with the complementary metal-oxide-semiconductor backend process. Full article
(This article belongs to the Special Issue Advanced Spintronic and Electronic Nanomaterials)
Show Figures

Figure 1

14 pages, 17280 KiB  
Article
A Comprehensive Study of Temperature and Its Effects in SOT-MRAM Devices
by Tomáš Hadámek, Nils Petter Jørstad, Roberto Lacerda de Orio, Wolfgang Goes, Siegfried Selberherr and Viktor Sverdlov
Micromachines 2023, 14(8), 1581; https://doi.org/10.3390/mi14081581 - 11 Aug 2023
Cited by 5 | Viewed by 2403
Abstract
We employ a fully three-dimensional model coupling magnetization, charge, spin, and temperature dynamics to study temperature effects in spin-orbit torque (SOT) magnetoresistive random access memory (MRAM). SOTs are included by considering spin currents generated through the spin Hall effect. We scale the magnetization [...] Read more.
We employ a fully three-dimensional model coupling magnetization, charge, spin, and temperature dynamics to study temperature effects in spin-orbit torque (SOT) magnetoresistive random access memory (MRAM). SOTs are included by considering spin currents generated through the spin Hall effect. We scale the magnetization parameters with the temperature. Numerical experiments show several time scales for temperature dynamics. The relatively slow temperature increase, after a rapid initial temperature rise, introduces an incubation time to the switching. Such a behavior cannot be reproduced with a constant temperature model. Furthermore, the critical SOT switching voltage is significantly reduced by the increased temperature. We demonstrate this phenomenon for switching of field-free SOT-MRAM. In addition, with an external-field-assisted switching, the critical SOT voltage shows a parabolic decrease with respect to the voltage applied across the magnetic tunnel junction (MTJ) of the SOT-MRAM cell, in agreement with recent experimental data. Full article
(This article belongs to the Special Issue Magnetic and Spin Devices, Volume II)
Show Figures

Figure 1

45 pages, 12047 KiB  
Review
Electromagnetic Radiation Effects on MgO-Based Magnetic Tunnel Junctions: A Review
by Dereje Seifu, Qing Peng, Kit Sze, Jie Hou, Fei Gao and Yucheng Lan
Molecules 2023, 28(10), 4151; https://doi.org/10.3390/molecules28104151 - 17 May 2023
Cited by 8 | Viewed by 3480
Abstract
Magnetic tunnel junctions (MTJs) have been widely utilized in sensitive sensors, magnetic memory, and logic gates due to their tunneling magnetoresistance. Moreover, these MTJ devices have promising potential for renewable energy generation and storage. Compared with Si-based devices, MTJs are more tolerant to [...] Read more.
Magnetic tunnel junctions (MTJs) have been widely utilized in sensitive sensors, magnetic memory, and logic gates due to their tunneling magnetoresistance. Moreover, these MTJ devices have promising potential for renewable energy generation and storage. Compared with Si-based devices, MTJs are more tolerant to electromagnetic radiation. In this review, we summarize the functionalities of MgO-based MTJ devices under different electromagnetic irradiation environments, with a focus on gamma-ray radiation. We explore the effects of these radiation exposures on the MgO tunnel barriers, magnetic layers, and interfaces to understand the origin of their tolerance. This review enhances our knowledge of the radiation tolerance of MgO-based MTJs, improves the design of these MgO-based MTJ devices with better tolerances, and provides information to minimize the risks of irradiation under various irradiation environments. This review starts with an introduction to MTJs and irradiation backgrounds, followed by the fundamental properties of MTJ materials, such as the MgO barrier and magnetic layers. Then, we review and discuss the MTJ materials and devices’ radiation tolerances under different irradiation environments, including high-energy cosmic radiation, gamma-ray radiation, and lower-energy electromagnetic radiation (X-ray, UV–vis, infrared, microwave, and radiofrequency electromagnetic radiation). In conclusion, we summarize the radiation effects based on the published literature, which might benefit material design and protection. Full article
Show Figures

Figure 1

Back to TopTop