Design of a 2–4 Decoder Based on All-Spin Logic and Magnetic Tunnel Junction

Abstract

A 2–4 decoder based on all-spin logic (ASL) and magnetic tunnel junction (MTJ) is proposed. The decoder employs five-input minority gates to realize three-input NOR gates, which reduces the circuit size compared to the three-input minority gates. Simultaneously, the inputs of the original and reverse variables are implemented by initializing the MTJ fixed layer magnetization in different directions, which avoids the use of inverters. In addition, the 2–4 decoder adopts a single-input single-fan-out (SISF) structure, which reduces the channel length. To illustrate the advantages of the five-input minority gate, inverter-free structure, and SISF structures in designing the proposed 2–4 decoder, a second 2–4 decoder is proposed that uses three-input minority gates, inverters, and a single-input multiple-fan-out structure. Compared with the second decoder, the first decoder has the layout area reduced to 37.9%, the total channel length reduced to 40.8%, and the number of clock cycles reduced to one-third. Importantly, the design methods used in this work, such as multi-input minority gates, SISF structure, and inverter-free structure, provide an interesting approach for designing large-scale ASL logic circuits.

1. Introduction

As CMOS technology approaches its physical limits, many researchers are beginning to explore alternative technologies. Spin-based devices possess the advantages of robustness, ultra-low power consumption, and non-volatility, and are likely to become important candidates in the post-CMOS era [1,2,3,4,5,6,7]. Many spin-based devices have been proposed, such as spin field-effect transistors [8], nanomagnetic logic [9], magnetic domain wall logic [10], all-spin logic (ASL) [11], spin-wave-bus devices [12], spin gain transistors [13], etc.

In particular, ASL does not require additional hardware for repeated spin-charge conversion, which has attracted considerable attention [14,15,16,17,18,19,20,21,22,23,24]. Various types of logic circuits based on ASL have been proposed, such as inverter, majority/minority gate [11], D flip-flop [25], full adder [26], RS flip-flop [27], and XOR gate [28]. However, as an important element in logic circuits, the decoder has not been reported in the public as much as we know. A possible reason for this is as follows: decoders are medium-scale circuits that require the combination of several basic logic gates through non-magnetic channels, which usually require long channels to transmit spin information. However, due to the dramatic dissipation of the spin current in the channel, the use of long channels will offset any possible advantage and even cause the circuit to malfunction.

In addition, ASL circuits use the magnetization direction to represent binary information, so it is necessary to initialize the magnetization direction to determine the initial values of ASL circuits. Ref. [29] proposed a single-input single-fan-out (SISF) structure based on a magnetic tunnel junction (MTJ) to provide input signals for ASL circuits. The SISF structure can reduce the channel length in large-scale ASL circuits with multiple identical inputs, which in turn reduces the dissipation of spin current in the channel.

Unlike traditional CMOS technology, the basic logic gates in ASL circuits are no longer NAND/NOR gates but inverter/buffer and majority/minority gates, as shown in Figure 1. Each device consists of four parts, namely a ferromagnet (FM), channel, spacer, and ground. The magnetization of every FM has two stable states representing binary data, “1” and “0”, respectively. If the polarity of the supply voltage V_ASL is positive, as in Figure 1a, the magnetization direction of the output FM will be opposite to the magnetization of the input FM, and the inverter can be realized [11]. In Figure 1b, the magnetization direction of the output FM will be opposite to the majority of the magnetization directions of the three input FMs; that is, the minority gate is realized [27].

Based on the three-input minority gate as shown in Figure 1b, a two-input NOR gate can be implemented [27]. However, it would be more convenient to implement a 2–4 decoder using three-input NOR gates. Therefore, it is necessary to use a five-input minority gate to implement three-input NOR gates. Inspired by the above analysis, a 2–4 decoder based on ASL is proposed, which employs SISF structure and five-input minority gates.

2. Design of the Proposed 2–4 Decoder

The truth table of a 2–4 decoder is shown in

Table 1. The truth table of 2–4 decoder.

S	A1	A0	Y3	Y2	Y1	Y0
1	×	×	0	0	0	0
0	0	0	0	0	0	1
0	0	1	0	0	1	0
0	1	0	0	1	0	0
0	1	1	1	0	0	0

. The decoder has an enable terminal S, two inputs A₁ and A₀, and four outputs Y₀~Y₃.

According to Table 1, the expressions for each output can be written as follows:

$$\begin{array}{l}{Y}_0=\overline{S}\overline{A_1}\overline{A_0}=\overline{S+A_1+A_0}\\ Y_1=\overline{S}\overline{A_1}{A}_0=\overline{S+A_1+\overline{A_0}}\\ Y_2=\overline{S}{A}_1\overline{A_0}=\overline{S+\overline{A_1}+A_0}\\ Y_3=\overline{S}{A}_1{A}_0=\overline{S+\overline{A_1}+\overline{A_0}}\end{array}$$

(1)

Moreover, if two inputs are set to 1, the expression for the 5-input minority gate becomes

$$M_5\left(A,B,C,1,1\right)=\overline{A+B+C}$$

(2)

and the 3-input NOR logic function is realized. Therefore, to realize Y₀ to Y₃ with 5-input minority gates, the expression for Y₀ to Y₃ can be written as follows:

$$\begin{array}{l}{Y}_0=\overline{S+A_1+A_0}=M_5\left(S,A_1,A_0,1,1\right)\\ Y_1=\overline{S+A_1+\overline{A_0}}=M_5\left(S,A_1,\overline{A_0},1,1\right)\\ Y_2=\overline{S+\overline{A_1}+A_0}=M_5\left(S,\overline{A_1},A_0,1,1\right)\\ Y_3=\overline{S+\overline{A_1}+\overline{A_0}}=M_5\left(S,\overline{A_1},\overline{A_0},1,1\right)\end{array}$$

(3)

According to the Equation (3), the schematic of the 2–4 decoder is shown in Figure 2.

As shown in Figure 2, the 2–4 decoder consists of four 5-input minority gates, two inverters, and several connecting lines. Additionally, there are several minority gates that share the same input signal. In ASL circuits, a common method is to use channels to connect input ports and minority gates, resulting in the use of long channels to transmit spin signals. However, as the length of the channel increases, the spin current decays exponentially, leading to a large increase in energy dissipation. In particular, when the length of the channel exceeds the spin diffusion length, the spin current cannot effectively rotate the magnetization direction of the FM.

Moreover, it is necessary to initialize the magnetization direction of FMs in ASL circuits. To avoid the use of long channels and to initialize the magnetization direction of the 2–4 decoder, an SISF structure is used, as shown in Figure 3a. Here, an MTJ is used to realize the charge-to-spin conversion, and there is only one fan-out for each input. Figure 3b is the front view of Figure 3a. The white arrow indicates the magnetization direction of the FMs, where the magnetization direction of the fixed layer remains unchanged, while the magnetization direction of the free layer is determined by the polarity of current I.

Figure 4 shows the variation of the magnetization of the free layer in the SISF with the polarity of the current density flowing into the MTJ. It can be seen that the magnetization direction of the free layer is opposite to the polarity of the current density when the magnetization direction of the fixed layer points to the +x axis, while the magnetization direction of the free layer is the same as the polarity of the current density when the magnetization direction of the fixed layer points to the −x axis. Based on this, an original or a reverse variable can be input by setting the initial magnetization direction of the fixed layer. Specifically, when the magnetization direction of the fixed layer is set to the +x axis, the inverse variable is input, and when the magnetization direction of the fixed layer is set to the −x axis, the original variable is input.

According to Equation (3), the inputs of the original variable and the inverse variable are necessary for the decoder. The general practice is to use inverters to transform original variables into inverse variables, as shown in Figure 2. However, according to the above, it is possible to implement the inputs of the original and inverse variables by initializing the MTJ fixed layer in different directions, which eliminates the use of an inverter, thus reducing the signal transmission path and shortening the clock cycle.

Based on the above description, Figure 5 shows the local layouts of Y₀ to Y₃, where each local layout is a 5-input minority gate with an SISM structure. FM1, FM2, and FM3 are both the free layers of the MTJ and the inputs of the 5-input minority gate. Their magnetization directions are determined by the input signals S, A₁, and A₀, respectively. FM4 and FM5 are the inputs of the minority gate, and their magnetizations are fixed to the +x axis direction, representing input logic 1. FM6 is the output of the minority gate, and its magnetization direction is determined by the magnetization direction of the five inputs. When a positive voltage V_ASL is applied, the 3-input NOR logic function shown in Equation (2) can be realized.

It should be noted that although all four local layouts are structurally the same, the magnetization direction of the fixed layer is different in each local layout. If the input is an original variable, the magnetization of the fixed layer connected to that input is initialized to the −x axis direction, and if the input is an inverse variable, the magnetization of the fixed layer is initialized to the +x axis direction.

The four local layouts shown in Figure 5 are connected together to form a complete 2–4 decoder, as shown in Figure 6.

3. Functional Verification of the 2–4 Decoder

The proposed 2–4 decoder consists of four identical 5-input minority gates, and in each minority gate, the magnetizations of FM1~FM3 are affected by the current flowing through the MTJ and the operating voltage V_ASL, and their magnetization dynamic behavior can be described as follows [29]:

$$\begin{array}{cc}{\displaystyle \frac{\mathrm{d}{m}_n}{\mathrm{d}t}}=-\gamma {\mu }_0{m}_n\times H_{\mathrm{eff}}+\alpha m_n\times {\displaystyle \frac{\mathrm{d}{m}_n}{\mathrm{d}t}}+\xi m_n\times \left(m_n\times M_n\right)+{\displaystyle \frac{1}{q{N}_S}}{m}_n\times \left(I_{Sn}\times m_n\right)& n=1,2,3\end{array}$$

(4)

where γ, μ₀, α, q, and N_s represent the electron gyromagnetic ratio, the free space permeability, the Gilbert damping of the magnetic material, the magnitude of the electron charge, and the number of Bohr magnetons of FMs, respectively; $m_n$ and $M_n$ are the normalized magnetization of the nth MTJ free-layer and fixed-layer magnets, respectively; and $I_{Sn}$ is the spin current flowing into the nth FM. $H_{\mathrm{eff}}$ is the effective magnetic field of FM, and $\xi$ is the asymmetric Slonczewski type torque coefficient [19,29].

FM4~FM6 are only affected by the spin current in channels, and their magnetization dynamic behavior can be described as follows [30]:

$$\begin{array}{cc}{\displaystyle \frac{\mathrm{d}{m}_n}{\mathrm{d}t}}=-\gamma {\mu }_0{m}_n\times H_{\mathrm{eff}}+\alpha m_n\times {\displaystyle \frac{\mathrm{d}{m}_n}{\mathrm{d}t}}+{\displaystyle \frac{1}{q{N}_{\mathrm{S}}}}{m}_n\times \left(I_{Sn}\times m_n\right)& n=4,5,6\end{array}$$

(5)

From Equations (4) and (5), it can be seen that to obtain the magnetization precession trajectory of the FMs, it is also necessary to know the spin current $I_S$. This requires a spin transport model [30] to obtain the spin currents. The equivalent spin transport model for the 5-input minority gate is constructed as shown in Figure 7. $G_k^{\mathrm{FM}}\left(k=1,2,\cdots ,9\right)$ is the interface conductance matrix of the interface, $G_k^{\mathrm{seg}}\left(k=1,2,\cdots ,8\right)$ and $G_k^{\mathrm{shg}}\left(k=1,2,\cdots ,8\right)$ are the series conductance matrix and shunt conductance matrix of the GNDs, and $G_k^{\sec \mathrm{h}}\left(k=1,2,\cdots ,6\right)$ and $G_k^{\mathrm{shch}}\left(k=1,2,\cdots ,6\right)$ are the series conductance matrix and shunt conductance matrix of channels [17].

The voltage vector of each node in Figure 7 can be obtained by a node analysis. And the currents flowing into the FMs can be obtained by the voltage vectors. With the obtained currents, the magnetizations of the FMs are obtained by Equations (4) and (5). By iteratively solving the spin transport model and the magnetization dynamics model, which is usually called the magnetization dynamics/spin transport simulation framework [25,30], the magnetization precession trajectory of the FMs can be obtained.

To make the 2–4 decoder work properly, an asynchronous clock control scheme is proposed, as shown in Figure 8, where the input signals are divided into three phases, called “Reset”, “Input”, and “Hold”, and the operating voltage is divided into two phases, called “Keep” and “Switch”. One clock cycle is assumed to be 6ns. It is important to note that the assumed clock period is merely a conservative estimate based on the parameters listed in

Table 2. Default dimension and material parameters for 2–4 decoder.

Parameters	Description	Values	Parameters	Description	Values
lFM_L (nm)	length of FM 1, 2, and 3	100	$\alpha$	Gilbert damping constant of Py	0.007
lFM_R (nm)	length of FM 4, 5, and 6	50	$\chi$	TMR asymmetry parameter	4
lFM_F (nm)	length of MTJ fixed layers	40	${\lambda }_{\mathrm{Cu}}$ (nm)	spin flip length of Cu	350
lchannel_L (nm)	length of channel 1, 3, 4, and 5	250	T (K)	Kelvin temperature	300
lchannel_S (nm)	length of channels 2 and 6	200	$\epsilon$	spin polarization efficiency constant	0.35
lGND1 (nm)	length of MTJ GND	70	${\rho }_{\mathrm{Cu}}$ ($\mathsf{\Omega }\cdot \mathrm{nm}$)	resistivity of Cu	34
tchannel (nm)	thickness of channel	50	$M_S$ (A·m−1)	saturation magnetization of Py	$8\times {10}^5$
tFM (nm)	thickness of FMs	0.8	TMR	tunnel magneto-resistance of MTJ	10%
tGND1 (nm)	thickness of MTJ GND	20	$K_{\mathsf{\mu }} {(\mathrm{Jm}}^{-3})$	uniaxial anisotropy parameter for FMs	$1.923\times {10}^4$
tGND2 (nm)	thickness of minority GND	40	Nd1	demagnetizing tensor for FM1~3	[0.012 0.041 0.947]
w(nm)	width of device	30	Nd2	demagnetizing tensor for FM4~6	[0.023 0.039 0.938]
lGND2 (nm)	length of minority GND	20	RA ($\mathsf{\Omega }{\mathrm{m}}^2$)	resistance area product of MTJ	$0.8\times {10}^{-12}$

, ensuring the decoder’s normal operation. By optimizing the magnet’s size or material [17], or opting for materials with long spin diffusion lengths, such as grapheme, as the channel [16], the clock period can be further shortened.

For the input signal, during the “Reset” phase, the current density is −0.1 × 10¹² A/m², which causes the magnetization direction of the MTJ free layer to rotate from the initial state to the same direction as that of the MTJ fixed layer, which is called “Reset”.

In the “Input” phase, if the input is a logic “0”, the current density is 0, which causes the magnetization of the free layer to remain constant; if the input is a logic “1”, the current density is 0.1 × 10¹² A/m², which causes the magnetization direction of the free layer to be opposite to that of the fixed layer.

In the “Hold” phase, the current densities of S, A₁, and A₀ are all zero, and the magnetizations of FM1, FM2, and FM3 remain unchanged in preparation for the minority gate operation.

For the operating voltage, during the “Keep” phase, the operating voltage V_ASL applied to the minority gate is 0, the minority gate does not operate, and the magnetization of the FM6 remains unchanged.

In the “Switch” phase, the operating voltage applied to the minority gate becomes 10 mV, and the minority gate starts to operate. The magnetization of FM6 depends on the magnetizations of the five inputs.

In the 2–4 decoder, the parameters of the four 5-input minority gates are completely identical except for the different magnetization directions of the fixed layer. The default parameters are shown in Table 2.

Suppose that the initial magnetization directions of FM4 and FM5 are both + x axis, and the initial magnetization directions of the other FMs are all −x axis. Figure 9 shows the time evolution of magnetization in the x-direction of the 2–4 decoder under the signals shown in Figure 8. Due to space limitations, Figure 9 shows only the time evolution of the x-direction magnetization of six FMs in Y₁ (Figure 5b). Assume that when the x-direction magnetization is 1, it means logic 1, and when it is −1, it means logic 0.

During 0~1 ns, the input signals are in the “Reset” phase and the magnetization directions of the MTJ fixed layers are as shown in Figure 5b, so m_1x and m_2x basically remain at −1, while m_3x rotates from −1 to +1. At this time, the operating voltage is in the “Keep” phase, the minority gate does not operate, and m_4x, m_5x, and m_6x remain unchanged.

During 1~3 ns, the input signals are in the “Input” phase, the current density of S and A₁ is 0, and the current density of A₀ is 1 × 10¹¹ A/m², so that m_1x and m_2x remain basically unchanged at −1, while m_3x rotates from +1 to −1. At this time, the operating voltage is still in the “Keep” phase, and m_4x, m_5x, and m_6x remain unchanged.

During 3~6 ns, the input signals are in the “Hold” phase, so that m_1x, m_2x, and m_3x remain at −1. At this time, the operating voltage is in the “Switch” phase, and the minority gate begins to operate. Since two of the five input FMs’ magnetization directions point to the +x axis, which is a minority, m_6x rotates from −1 to +1.

During the period of 6~12 ns, it is the next clock cycle, and the analysis is basically the same as above, so it does not need to be repeated here. In addition, as can be seen in Figure 9, m_4x and m_5x remain approximately +1 throughout the cycle, indicating that the magnetization directions of FM4 and FM5 always point to the +x axis direction, which is consistent with our expectations.

To verify the function of each subcircuit shown in Figure 5, Figure 10 shows the time evolution of the x-direction magnetization of outputs Y₀, Y₁, Y₂, and Y₃ under different inputs.

From Figure 10a–d, in the “switch” phase, when SA₁A₀ = 000, Y₀Y₁Y₂Y₃ = 1000; when SA₁A₀ = 000 = 001, Y₀Y₁Y₂Y₃ = 0100; when SA₁A₀ = 000, Y₀Y₁Y₂Y₃ = 0010; and when SA₁A₀ = 000 = 011, Y₀Y₁Y₂Y₃ = 0001. Moreover, Figure 10e shows that there is Y₀Y₁Y₂Y₃ = 0000 when SA₁A₀=110. (Due to space limitations, only the simulation results of SA₁A₀ = 110 are shown. If SA₁A₀ = 100, SA₁A₀ = 101, or SA₁A₀ = 111, there is still Y₀Y₁Y₂Y₃ = 0000.) This is entirely consistent with Table 1, which verifies that the 2–4 decoder functions correctly.

4. The Results and Discussions

The total energy dissipation of the 2–4 decoder consists of the energy dissipation of the MTJs and the energy dissipation of the minority gates, as follows:

$$E_{\mathrm{total}}=E_{\mathrm{MTJ}}+E_{\mathrm{Minority}}$$

(6)

The energy dissipation of the MTJs is

$$E_{\mathrm{MTJ}}={\displaystyle {\int }_0^T{\displaystyle \sum _{k=1}^3{I}_k^2}}{R}_k^{\mathrm{MTJ}}\mathrm{d}t={\displaystyle {\int }_0^T{\displaystyle \sum _{k=1}^3{\left(J_k{S}_k^{\mathrm{MTJ}}\right)}^2{R}_k^{\mathrm{MTJ}}}}\mathrm{d}t$$

(7)

where T is the clock cycle, $S_k^{\mathrm{MTJ}}$ is the cross-sectional area of the k-th MTJ, and $R_k^{\mathrm{MTJ}}$ is the resistance of the k-th MTJ, and can be expressed as

$$R^{\mathrm{MTJ}}=R_{\mathrm{P}}+{\displaystyle \frac{1}{2}}\left(R_{\mathrm{AP}}-R_{\mathrm{P}}\right)\left(1-\cos \theta \left(t\right)\right)$$

(8)

$R_{\mathrm{P}}$ and $R_{\mathrm{AP}}$ are the MTJ resistances when the magnetization directions of the fixed layer and the free layer are parallel and anti-parallel, respectively. And θ(t) is the angle between the magnetization vectors of free layer and fixed layer, which varies with time.

The energy dissipation of minority gates is

$$E_{\mathrm{Minority}}={\displaystyle \sum _{i=0}^3{\displaystyle {\int }_0^T{\displaystyle \sum _{k=1}^6{V}_{\mathrm{ASL}}{I}_{i,k}^C}\mathrm{d}t}}$$

(9)

where $I_{i,k}^C$ is the charge current flowing into the k-th FM in the i-th minority gate.

Table 3. The energy dissipation of MTJs and minority gates under different inputs.

SA1A0	${\mathit{E}}_{\mathbf{MTJ}}$ (pJ)	${\mathit{E}}_{\mathbf{Minority}}$ (pJ)	SA1A0	${\mathit{E}}_{\mathbf{MTJ}}$ (pJ)	${\mathit{E}}_{\mathbf{Minority}}$ (pJ)
000	0.116	9.299	100	0.194	9.297
001	0.195	9.299	101	0.272	9.297
010	0.195	9.299	110	0.272	9.296
011	0.273	9.299	111	0.351	9.297

shows the energy dissipation of the MTJs and minority gates under different inputs. It can be seen that the $E_{\mathrm{Minority}}$ is basically the same under different inputs, which is about 9.30 pJ. This is because the energy dissipation of minority gates is mainly determined by the charge currents flowing into FMs and the operating voltage V_ASL applied to them, and the charge currents are not affected by the inputs, so different inputs have little effect on the energy dissipation of minority gates. However, the $E_{\mathrm{MTJ}}$ varies greatly under different inputs, because when the input signal changes, the current density flowing into the MTJs changes accordingly, and it can be seen from Equation (8) that the $E_{\mathrm{MTJ}}$ will be different.

The energy dissipation of the MTJ, which is also the energy dissipation of the SISF structure, only has an average value of about 0.23 pJ, which is about 1/40 of the energy dissipation of the MTJs and minority gate. This shows that the increase in the energy dissipation of the MTJs due to the increase in the number of MTJs resulting from the employment of the SISF structure is negligible.

In addition, according to the research findings presented in Refs. [31,32], replacing the insulating layer in the MTJ with Sr2RuO4, an unconventional superconducting material, could potentially eliminate the charge current and only retain the spin current within the MTJ, thereby further reducing its energy consumption. Consequently, the marginal increase in energy consumption resulting from an increase in the number of SISFs will become even more negligible.

To illustrate the advantages of the five-input minority gate and SISF structure in designing the 2–4 decoder, another 2–4 decoder designed using three-input minority gates, inverters, and a single-input multi-fan-out (SIMF) structure is given below and is called the second decoder for convenience. The logical expression for the second decoder is

$$\begin{array}{l}{Y}_0=\overline{S+A_1+A_0}=M_3\left(\overline{M_3\left(S,A_1,1\right)},A_0,1\right)\\ Y_1=\overline{S+A_1+\overline{A_0}}=M_3\left(\overline{M_3\left(S,A_1,1\right)},\overline{A_0},1\right)\\ Y_2=\overline{S+\overline{A_1}+A_0}=M_3\left(\overline{M_3\left(S,\overline{A_1},1\right)},A_0,1\right)\\ Y_3=\overline{S+\overline{A_1}+\overline{A_0}}=M_3\left(\overline{M_3\left(S,\overline{A_1},1\right)},\overline{A_0},1\right)\end{array}$$

(10)

where $M_3\left(A,B,C\right)$ denotes a three-input minority gate, and when one of the inputs is set to 1, its logical expression becomes

$$M_3\left(A,B,1\right)=\overline{A+B}$$

(11)

According to Equation (11), the 2D schematic diagram of the second decoder is shown in Figure 11. To avoid the crossover of channels, the three inputs are not in the same plane. The channel connected to A₁ is in the top layer, A₀ is in the middle layer, and S is in the bottom layer. The white arrow indicates that the input FM of the three-input minority gate is magnetized in the +x-axis direction, representing logic 1.

Table 4. Performance comparison of the two decoders.

Performance	First Decoder	Second Decoder
Maximum channel length (nm)	250	1430
Total length of channels (nm)	5200	12,740
Number of FMs	36	26
Layout area (um2)	0.319	0.841
Number of clock cycles	1	3

shows the performance comparison of the two types of 2–4 decoders. The dimensional parameters in Table 2 are used for both decoders, and in addition, the spacing between each minority gate is assumed to be 20 nm. Compared to the second decoder, the first decoder (decoder shown in Figure 5) reduces the total channel length to 40.8%, the layout area to 37.9%, and the number of clock cycles to one-third. In particular, the second decoder has a maximum channel length of 1430 nm, which exceeds the spin diffusion length of most currently known metallic materials, which would cause the decoder to fail. Therefore, the simulation results for the operation of the second decoder are not provided here. In addition, despite the increase in the number of FMs in the first decoder, mainly by nine MTJs, its impact on energy dissipation is negligible according to the previous description.

In summary, for logic circuits such as 2–4 decoders with multiple identical inputs, the use of the SISF structure and multiple-input minority gates can result in significant improvements in terms of layout area, clock cycles, and so on.

5. Conclusions

In this paper, a 2–4 decoder based on ASL and a MTJ is proposed, and its logic function is verified by a magnetization dynamics/spin transport self-consistent simulation framework. The proposed 2–4 decoder employs an SISF structure to provide input to the circuit, thus reducing the channel length of the circuit. At the same time, five-input minority gates are employed, which greatly simplifies the circuit scale. In addition, the original variables and the inverse variables are realized by setting the magnetization of the MTJ fixed layer in different directions, which avoids the use of inverters and further reduces the circuit scale. Compared to the 2–4 decoder using three-input minority gates, inverters, and the SIMF structure, the proposed 2–4 decoder shows significant improvement in maximum channel length, total channel length, layout area, and the number of clock cycles, except for the number of FMs. Most importantly, the design methods used in this paper, such as the SISF structure, multi-input majority/minority gate, and inverter-free structure, provide a way to design more large-scale ASL circuits in the future.