Search Results (89)

An altermagnet, characterized by its distinctive magnetic properties, may hold potential applications in diverse fields such as magnetic materials, spintronics, data storage, and quantum computing. As a prototypical altermagnet, RuO₂ exhibits spin polarization and demonstrates the advantageous characteristics of high electrical conductivity and low thermal conductivity. These exceptional properties endow it with considerable promise in the emerging field of thermal spintronics. We studied the electronic structure and thermoelectric properties of RuO₂; the constructed RuO₂/TiO₂/RuO₂ all-antiferromagnetic tunnel junction (AFMTJ) exhibited thermally induced magnetoresistance (TIMR), reaching a maximum TIMR of 1756% at a temperature gradient of 5 K. Compared with prior studies on RuO₂-based antiferromagnetic tunnel junctions, the novelty of this work lies in the thermally induced magnetoresistance based on its superior thermoelectric properties. In parallel structures, the spin-down current dominates the transmission spectrum, whereas in antiparallel structures, the spin-up current governs the transmission spectrum, underscoring the spin-polarized thermal transport. In addition, thermoelectric efficiency emphasizes the potential of RuO₂ to link antiferromagnetic robustness with ferromagnetic spin functionality. These findings promote the development of efficient spintronic devices and spin-based storage technology for waste heat recovery and emphasize the role of spin splitting in zero-magnetization systems. Full article

This paper presents a novel transposed MRAM architecture (WinEdge) specifically optimized for Winograd convolution acceleration in edge computing devices. Leveraging Magnetic Tunnel Junctions (MTJs) with Spin Hall Effect (SHE)-assisted Spin-Transfer Torque (STT) writing, the proposed design enables a single SHE current to simultaneously write data to four MTJs, substantially reducing power consumption. Additionally, the integration of stacked MTJs significantly improves storage density. The proposed WinEdge efficiently supports both standard and transposed data access modes regardless of bit-width, achieving up to 36% lower power, 47% reduced energy consumption, and 28% faster processing speed compared to existing designs. Simulations conducted in 45 nm CMOS technology validate its superiority over conventional SRAM-based solutions for convolutional neural network (CNN) acceleration in resource-constrained edge environments. Full article

The demand for computing power has been growing exponentially with the rise of artificial intelligence (AI), machine learning, and the Internet of Things (IoT). This growth requires unconventional computing primitives that prioritize energy efficiency, while also addressing the critical need for scalability. Neuromorphic computing, inspired by the biological brain, offers a transformative paradigm for addressing these challenges. This review paper provides an overview of advancements in 2D spintronics and device architectures designed for neuromorphic applications, with a focus on techniques such as spin-orbit torque, magnetic tunnel junctions, and skyrmions. Emerging van der Waals materials like CrI₃, Fe₃GaTe₂, and graphene-based heterostructures have demonstrated unparalleled potential for integrating memory and logic at the atomic scale. This work highlights technologies with ultra-low energy consumption (0.14 fJ/operation), high switching speeds (sub-nanosecond), and scalability to sub-20 nm footprints. It covers key material innovations and the role of spintronic effects in enabling compact, energy-efficient neuromorphic systems, providing a foundation for advancing scalable, next-generation computing architectures. Full article

Magnetic random-access memory, recognized as a breakthrough in spintronics, demonstrates substantial potential for next-generation nonvolatile memory and logic devices due to its unique magnetization-switching mechanism. However, realizing reliable perpendicular magnetization switching via spin–orbit torque necessitates an externally applied in-plane magnetic bias, a requirement that complicates integration in high-density device architectures. This study proposes a novel device architecture where geometric asymmetry engineering in an interlayer design generates an intrinsic equivalent in-plane magnetic field. By strategically introducing a non-symmetrical spacer between the heavy metal and ferromagnetic layers, we establish deterministic magnetization reversal while eliminating external field dependency. Furthermore, the energy barrier during magnetization switching is dynamically adjusted by applying a voltage across a perpendicular-anisotropy magnetic tunnel junction, leveraging the voltage-controlled magnetic anisotropy effect. We established a physics-driven compact model to assess the design and performance of voltage-controlled spin–orbit torque magnetic tunnel junction (VCSOT-MTJ) devices. Simulations reveal that the introduction of a minimally asymmetric light metal layer effectively resolves the issue of incomplete switching in field-free spin-orbit torque systems. Full article

Accurate measurement of magnetic fields holds immense significance across various disciplines, such as IC circuit measurement, geological exploration, and aerospace. The sensitivity and noise parameters of magnetic field sensors play a vital role in detecting minute fluctuations in magnetic fields. However, the current detection capability of tunneling magnetoresistance (TMR) is insufficient to meet the requirements for weak magnetic field measurement. This study investigates the impact of structural and fabrication parameters on the performance of TMR sensors. We fabricated series-connected TMR sensors with varying long-axis lengths of the elliptical cross-section and adjusted their performance by modifying annealing magnetic fields and magnetic field bias along the easy axis. The results demonstrate that TMR sensitivity decreases with increasing long-axis length, increases initially and then decreases with an annealing magnetic field, and decreases with a higher bias magnetic field along the easy axis. The voltage noise level of TMR sensors decreases as the long-axis length increases. Notably, the detection capability of TMR sensors exhibits a non-monotonic dependence on long-axis length. Moreover, we optimized the hysteresis of TMR sensors by applying a magnetic field bias along the easy axis. When the bias along the easy axis reached 16 Oe or −40 Oe, the hysteresis level was reduced to below 0.5 Oe. After encapsulating the TMR devices into a full Wheatstone bridge structure, we achieved a detection capability of 17 nT/$\sqrt{\mathrm{Hz}}$@1Hz. This study highlights that the detection capability of TMR devices is jointly influenced by fabrication parameters. By optimizing parameter configuration, this work provides theoretical guidance for further enhancing the performance of TMR devices in magnetic field measurements. Full article

The so-call SQUIDs (abbreviated from superconducting quantum interference device) are very sensitive apparatuses especially built for metering very low magnetic fields. These systems have applications in various practical fields—biology, geology, medicine, different engineering areas, etc. Their features are mainly based on superconductors and the Josephson effect. They can be differentiated into two main groups—direct current (DC) and radio frequency (RF) SQUIDs. Both of them were constructed in the 1960s at Ford Research Labs. The main difference between them is that the second ones use only one superconducting tunnel junction. This reduces their sensitivity, but makes them significantly cheaper. We investigate namely the rf-SQUIDs in the present work. A number of authors devote their research to the rf-SQUIDs driven by an oscillating external flux. We aim to enlarge the theoretical base of these systems by adding new factors in their dynamics. Several particular cases are explored and simulated. We demonstrate also some specialized modules for investigating the proposed model. One application for possible control over oscillations is also discussed. It is based on the Fourier transform and, as a consequence, on the characteristic function of some probability distributions. Full article

A 2–4 decoder based on all-spin logic (ASL) and magnetic tunnel junction (MTJ) is proposed. The decoder employs five-input minority gates to realize three-input NOR gates, which reduces the circuit size compared to the three-input minority gates. Simultaneously, the inputs of the original and reverse variables are implemented by initializing the MTJ fixed layer magnetization in different directions, which avoids the use of inverters. In addition, the 2–4 decoder adopts a single-input single-fan-out (SISF) structure, which reduces the channel length. To illustrate the advantages of the five-input minority gate, inverter-free structure, and SISF structures in designing the proposed 2–4 decoder, a second 2–4 decoder is proposed that uses three-input minority gates, inverters, and a single-input multiple-fan-out structure. Compared with the second decoder, the first decoder has the layout area reduced to 37.9%, the total channel length reduced to 40.8%, and the number of clock cycles reduced to one-third. Importantly, the design methods used in this work, such as multi-input minority gates, SISF structure, and inverter-free structure, provide an interesting approach for designing large-scale ASL logic circuits. Full article

A Probabilistic Bit (P-Bit) device serves as the core hardware for implementing Ising computation. However, the severe intrinsic variations of stochastic P-Bit devices hinder the large-scale expansion of the P-Bit array, significantly limiting the practical usage of Ising computation. In this work, a behavioral model which attributes P-Bit variations to two parameters, $\alpha$ and $\Delta V$, is proposed. Then the weight compensation method is introduced, which can mitigate $\alpha$ and $\Delta V$ of P-Bit device variations by rederiving the weight matrix, enabling them to compute as ideal identical P-Bits without the need for weights retraining. Accurately extracting the $\alpha$ and $\Delta V$ simultaneously from a large P-Bit array which is prerequisite for the weight compensation method is a crucial and challenging task. To solve this obstacle, we present the novel automatic variation extraction algorithm which can extract device variations of each P-Bit in a large array based on Boltzmann machine learning. In order for the accurate extraction of variations from an extendable P-Bit array, an Ising Hamiltonian based on a 3D ferromagnetic model is constructed, achieving precise and scalable array variation extraction. The proposed Automatic Extraction and Compensation algorithm is utilized to solve both 16-city traveling salesman problem (TSP) and 21-bit integer factorization on a large P-Bit array with variation, demonstrating its accuracy, transferability, and scalability. Full article

This paper presents Cryo-SIMPLY, a reliable smart material implication (SIMPLY) operating at cryogenic conditions (77 K). The assessment considers SIMPLY schemes based on spin-transfer torque magnetic random access memory (STT-MRAM) technology with single-barrier magnetic tunnel junction (SMTJ) and double-barrier magnetic tunnel junction (DMTJ). Our study relies on a temperature-aware macrospin-based Verilog-A compact model for MTJ devices and a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. The DMTJ-based SIMPLY demonstrates a significant improvement in read margin at 77 K, overcoming the conventional SIMPLY scheme at room temperature (300 K) by approximately 2.3 X. When implementing logic operations with the SIMPLY scheme operating at 77 K, the DMTJ-based scheme assures energy savings of about 69%, as compared to its SMTJ-based counterpart operating at 77 K. Overall, our results prove that the SIMPLY scheme at cryogenic conditions is a promising solution for reliable and energy-efficient logic-in-memory (LIM) architectures. Full article

Defects in the free layer are considered to be the main cause of the balloon effect, but there is little insight into the synthetic antiferromagnetic (SAF) layer. To address this shortcoming, in this work, an optimized SAF layer was introduced in the perpendicular magnetic tunneling junction (pMTJ) stack to eliminate the low-probability bifurcated-switching phenomenon. The results indicated that the Hf field in the film stack improved significantly from ~5700 Oe to ~7500 Oe. A magnetoresistive random access memory (MRAM) test chip was also fabricated with a 300 mm process, resulting in a significantly improved ballooning effect. The results also indicated that the switching voltage decreased by 18.6% and the writing energy decreased by 33.7%. In addition, the low-probability stray field along the x-axis was thought to be the main cause of the ballooning effect, and was experimentally optimized for the first time by enhancing the SAF layer. This work provides a new perspective on spin-flipping dynamics, facilitating a deeper comprehension of the internal mechanism and helping to secure improvements in MRAM performance. Full article

With the outstanding growth of Internet of Things (IoT) devices, security and power efficiency of integrated circuits can no longer be overlooked. Current approved standards for cryptographic algorithms are not suitable for constrained environments. In this context, the National Institute of Standards and Technology (NIST) started a lightweight cryptography (LWC) competition to develop new algorithm standards that can be fit into small devices. In 2023, NIST has decided to standardize the Ascon family for LWC. This algorithm has been designed to be more resilient to side-channel and fault-based analysis. Nonetheless, hardware implementations of Ascon have been broken by multiple statistical fault analysis and power analysis. These attacks have underlined the necessity to develop adapted countermeasures to side-channel and perturbation-based attacks. However, existing countermeasures are power and area consuming. In this article, we propose a new countermeasure for the Ascon cipher that does not significantly increase the area and power consumption. Our architecture relies on the nonvolatile feature of the Magnetic Tunnel Junction (MTJ) that is the single element of the emerging Magnetic Random Access Memories (MRAM). The proposed circuit removes the bias exploited by statistical attacks. In addition, we have duplicated and complemented the permutation of Ascon to enhance the power analysis robustness of the circuit. Besides the security aspect, our circuit can save current manipulated data, ensuring energy saving from 11% to 32.5% in case of power failure. The area overhead, compared to an unprotected circuit, is $\times 2.43$. Full article

In this work, we focus on a detailed study of the role of each component layer in the multilayer structure of a magnetic tunnel junction (MTJ) as well as the analysis of the effects that the deposition parameters of the thin films have on the performance of the structure. Various techniques including atomic force microscopy (AFM), scanning electron microscopy (SEM), and transmission electron microscopy (TEM) were used to investigate the effects of deposition parameters on the surface roughness and thickness of individual layers within the MTJ structure. Furthermore, this study investigates the influence of thin films thickness on the magnetoresistive properties of the MTJ structure, focusing on the free ferromagnetic layer and the barrier layer (MgO). Through systematic analysis and optimization of the deposition parameters, this study demonstrates a significant improvement in the tunnel magnetoresistance (TMR) of the MTJ structure of 10% on average, highlighting the importance of precise control over thin films properties for enhancing device performance. Full article

Spintronics, utilizing both the charge and spin of electrons, benefits from the nonvolatility, low switching energy, and collective behavior of magnetization. These properties allow the development of magnetoresistive random access memories, with magnetic tunnel junctions (MTJs) playing a central role. Various spin logic concepts are also extensively explored. Among these, spin logic devices based on the motion of magnetic domain walls (DWs) enable the implementation of compact and energy-efficient logic circuits. In these devices, DW motion within a magnetic track enables spin information processing, while MTJs at the input and output serve as electrical writing and reading elements. DW logic holds promise for simplifying logic circuit complexity by performing multiple functions within a single device. Nevertheless, the demonstration of DW logic circuits with electrical writing and reading at the nanoscale is still needed to unveil their practical application potential. In this review, we discuss material advancements for high-speed DW motion, progress in DW logic devices, groundbreaking demonstrations of current-driven DW logic, and its potential for practical applications. Additionally, we discuss alternative approaches for current-free information propagation, along with challenges and prospects for the development of DW logic. Full article

Integrated circuits suffer severe deterioration due to single-event upsets (SEUs) in irradiated environments. Spin-transfer torque magnetic random-access memory (STT-MRAM) appears to be a promising candidate for next-generation memory as it shows promising properties, such as non-volatility, speed, and unlimited endurance. One of the important merits of STT-MRAM is its radiation hardness, thanks to its core component, a magnetic tunnel junction (MTJ), being capable of good function in an irradiated environment. This property makes MRAM attractive for space and nuclear technology applications. In this paper, a novel radiation-hardened triple modular redundancy (TMR) design for anti-radiation reinforcement is proposed based on the utilization of STT-MTJ devices. Simulation results demonstrate the radiation-hardened performance of the design. This shows improvements in the design’s robustness against ionizing radiation. Full article

Hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) circuits based on in-memory-computation (IMC) architecture is considered as the next-generation candidate for the digital integrated circuits. However, the energy consumption during the MTJ write process is a matter of concern in these hybrid circuits. In this regard, we have developed a novel write circuit for the contemporary three-terminal perpendicular-MTJs that works on the voltage-gated spin orbit torque (VG+SOT) switching mechanism to store the information in hybrid circuits for IMC architecture. Investigation of the novel write circuit reveals a remarkable reduction in the total energy consumption (and energy delay product) of 92.59% (95.81) and 92.28% (42.03%) than the conventional spin transfer torque (STT) and spin-Hall effect assisted STT (SHE+STT) write circuits, respectively. Further, we have developed all the hybrid logic gates followed by nonvolatile full adders (NV-FAs) using VG+SOT, STT, and SHE+STT MTJs. Simulation results show that with the VG+SOT NOR-OR, NAND-AND, XNOR-XOR, and NV-FA circuits, the reduction in the total power dissipation is 5.35% (4.27%), 5.62% (3.2%), 3.51% (2.02%), and 4.46% (2.93%) compared to STT (SHE+STT) MTJs respectively. Full article