Search Results (182)

Broadband optical amplifiers operating in the 2 μm spectral region are critical for advancing mid-infrared photonic systems, yet achieving high gain with low noise remains challenging. In this work, we demonstrate a high-performance tapered fiber amplifier incorporating PbS quantum dots (QDs) as the gain medium. By optimizing the tapering geometry and QD doping concentration, we achieve a broadband on-off gain of >15 dB across a 200 nm bandwidth (1900–2100 nm). The unique combination of PbS QDs’ size-tunable bandgap and the tapered fiber’s enhanced evanescent field interaction enables efficient pump-probe overlap, resulting in a broader gain bandwidth compared to conventional rare-earth-doped fiber amplifiers. This work establishes a promising platform for compact, high-bandwidth mid-infrared light sources and amplifiers. Full article

In loop-powered 4–20 mA transmitter systems, sensors like temperature, pressure, flow, and gas sensors are chosen based on specific application requirements. These systems are widely adopted in high-precision measurement scenarios, including industrial automation, process control, and environmental monitoring. The transmitter requires a high-performance analog front end (AFE) for precise amplification and signal conditioning. This paper presents a low-noise instrumentation amplifier (IA) for high-precision transmitter front ends, featuring a Successive Approximation Register (SAR)-assisted offset calibration architecture. The proposed structure integrates a chopper current-feedback instrumentation amplifier (CFIA) with an automatic offset calibration loop (AOCL), significantly suppressing internal offset errors and enabling high-accuracy signal acquisition under stringent power and environmental temperature constraints. The designed amplifier provides four selectable gain settings, covering a range from ×32 to ×256. Fabricated in a 0.18 μm CMOS process, the CFIA operates at a 1.8 V supply voltage, consumes a static current of 182 μA, and achieves an input-referred noise as low as 20.28 nV/√Hz at 1 kHz, with a common-mode rejection ratio (CMRR) up to 122 dB and a power-supply rejection ratio (PSRR) up to 117 dB. Experimental results demonstrate that the proposed amplifier exhibits excellent performance in terms of input-referred noise, offset voltage, PSRR, and CMRR, making it well-suited for front-end detection in field instruments that require direct interfacing with measured media. Full article

This paper presents the design and implementation of an ultra-wideband (UWB) and flat gain low noise amplifier (LNA) using 0.15 µm GaAs pHEMT technology, specifically tailored for applications that benefit from multi-band capability, such as satellite communication. The designed LNA consists of three stages: Two stages are cascoded using source degeneration with a resistor for low noise and high linearity, and the third cascaded stage is utilized for high gain. The designed UWB LNA exhibits a measured gain of 17.4 ± 1 dB between 312 and GHz and a 3 dB bandwidth of 12.4 GHz (1.6–14 GHz). It achieves a noise figure (NF) of 2.5–4.3 dB and an output P1dB of 15 dBm. The chip size is $3\times 1$${\mathrm{mm}}^2$, and it operates without the need for any external components. When compared to LNAs in the literature, the proposed design stands out for its flat gain in the specified frequency band, making the LNA particularly attractive for volume-limited and power-constrained applications. Full article

For high-voltage signal detection applications, an auto-zero and chopper operational amplifier (OPA) is proposed in this paper. With the auto-zero and chopper technique, the OPA adopts an eight-channel Ping-Pong mechanism to reduce the high-frequency ripple and glitch generated by chopper modulation. The main transconductor effectively suppresses low-frequency noise and offset by combining input coarse and output fine auto-zero. A common-mode voltage tracking circuit is presented to ensure constant gate-source and gate-substrate voltages of the chopper, which reduces the charge injection caused by threshold voltage drift of their transistors and improves output signal resolution. The OPA is implemented using CMOS 180 nm BCD process. The post-simulation results show that the unit gain bandwidth (UGB) is 2.5 MHz and common-mode rejection ratio (CMRR) is 137 dB when the power supply voltage is 5–55 V. The noise power spectral density (PSD) is 6.6 nV/√Hz, and the offset is about 47 µV. The overall circuit consumes current of 960 µA. Full article

With their superior switching speed, GaN high-electron-mobility transistors (HEMTs) enable high power density, reduce energy losses, and increase power efficiency in a wide range of applications, such as power electronics, due to their high breakdown voltage. GaN-HEMT devices are subject to long-term reliability due to the self-heating effect and lattice mismatch between the SiC substrate and the GaN. Depletion-mode GaN HEMTs are utilized for radio frequency applications, and this work investigates three wide-bandgap (WBG) GaN HEMT fixed-frequency oscillators with output buffers. The first GaN-on-SiC HEMT oscillator consists of an HEMT amplifier with an LC feedback network. With the supply voltage of 0.8 V, the single-ended GaN oscillator can generate a signal at 8.85 GHz, and it also supplies output power of 2.4 dBm with a buffer supply of 3.0 V. At 1 MHz frequency offset from the carrier, the phase noise is −124.8 dBc/Hz, and the figure of merit (FOM) of the oscillator is −199.8 dBc/Hz. After the previous study, the hot-carrier stressed RF performance of the GaN oscillator is studied, and the oscillator was subject to a drain supply of 8 V for a stressing step time equal to 30 min and measured at the supply voltage of 0.8 V after the step operation for performance benchmark. Stress study indicates the power oscillator with buffer is a good structure for a reliable structure by operating the oscillator core at low supply and the buffer at high supply. The second balanced oscillator can generate a differential signal. The feedback filter consists of a left-handed transmission-line LC network by cascading three unit cells. At a 1 MHz frequency offset from the carrier of 3.818 GHz, the phase noise is −131.73 dBc/Hz, and the FOM of the 2nd oscillator is −188.4 dBc/Hz. High supply voltage operation shows phase noise degradation. The third GaN cross-coupled VCO uses 8-shaped inductors. The VCO uses a pair of drain inductors to improve the Q-factor of the LC tank, and it uses 8-shaped inductors for magnetic coupling noise suppression. At the VCO-core supply of 1.3 V and high buffer supply, the FOM at 6.397 GHz is −190.09 dBc/Hz. This work enhances the design techniques for reliable GaN HEMT oscillators and knowledge to design high-performance circuits. Full article

This paper introduces a 0.5–5.8 GHz low-noise amplifier (LNA) incorporating a gyrator-C-based active inductor (AI) and an enhanced deep trench isolation (DTI) electrostatic discharge (ESD) diode. Results suggest that AIs exhibit excellent consistency under various process voltage temperatures (PVTs) as well as input powers and the improved DTI diodes reduce parasitic capacitance by an average of 8.5% compared to conventional ones. In terms of circuit design, comprehensive analyses of gain flatness and noise are conducted. Fabricated using a 0.18 μm SiGe BiCMOS technology, the LNA delivers a high S21 of 18.3 ± 0.3 dB, a minimum noise figure of 2.6 dB, and an S11 and S22 of less than −10 dB over the entire frequency band. Operating from a 3.3 V supply voltage with a core area of 0.049 mm², it consumes 10 mA of current. Full article

This paper proposes relaxed Simultaneous Signal and Noise Matching (SSNM) conditions to address limitations in selecting source degeneration inductors for multistage LNA design, achieved by introducing controlled mismatches at the external ports. Additionally, a novel frequency-bounded mismatch envelope is introduced to guide load termination selection based on desired IM-OM (input mismatch-output mismatch) characteristics across the operating band. Building on these concepts, a systematic, easy-to-follow strategy is presented for implementing wideband multistage low-noise amplifiers (LNAs), significantly reducing reliance on blind CAD-based optimisation. This approach is validated through a three-stage MMIC LNA prototype, fabricated using a 0.15 μm GaAs process and operating from 28 to 34 GHz. The measured results closely match the simulation, demonstrating a stable gain of 23 ± 1 dB and a noise figure of 2–2.5 dB, confirming the practical effectiveness of the proposed design approach for wideband amplifiers. Full article

Encryption and decryption are essential components in signal processing and optical communication systems, providing data confidentiality, integrity, and secure high-speed transmission. We present a novel design and simulation of an all-optical encryption and decryption system operating at 120 Gb/s using carrier reservoir semiconductor optical amplifiers (CR-SOAs) embedded in Mach–Zehnder interferometers (MZIs). The architecture relies on two consecutive exclusive-OR (XOR) logic gates, implemented through phase-sensitive interference in the CR-SOA-MZI structure. The first XOR gate performs encryption by combining the input data signal with a secure optical key, while the second gate decrypts the encoded signal using the same key. The fast gain recovery and efficient carrier dynamics of CR-SOAs enable a high-speed, low-latency operation suitable for modern photonic networks. The system is modeled and simulated using Mathematica Wolfram, and the output quality factors of the encrypted and decrypted signals are found to be 28.57 and 14.48, respectively, confirming excellent signal integrity and logic performance. The influence of key operating parameters, including the impact of amplified spontaneous emission noise, on system behavior is also examined. This work highlights the potential of CR-SOA-MZI-based designs for scalable, ultrafast, and energy-efficient all-optical security applications. Full article

This paper presents a broadband near-field probe designed for measuring the normal magnetic field ($H_z$) in radio frequency (RF) circuits operating within a frequency range of 2–8 GHz. The proposed probe uses a cost-effective 4-layer printed circuit board (PCB) structure made with an FR-4 substrate. The probe primarily consists of an $H_z$ detection unit, a broadband microstrip balun, and a coaxial-like output. The broadband balun facilitates the conversion from differential to single-ended signals, thereby enhancing the probe’s common-mode rejection capability. This design ensures that the probe achieves both cost efficiency and high broadband measurement performance. Additionally, this work investigates the feasibility of employing microstrip lines as calibration standards for the $H_z$ probe. The probe’s structural parameters and magnetic field response were initially determined through simulations, and the calibration factor was subsequently verified by calibration experiments. In practical measurements, the field distributions above a microstrip line and a low-noise amplifier (LNA) were captured. The measured field distribution of the microstrip line was compared with simulation results to verify the probe’s performance. Meanwhile, the measured field distribution of the LNA was utilized to identify the radiating components within the amplifier. Full article

This paper presents an optimized 868 MHz low-noise amplifier (LNA) based on a bipolar junction transistor (BJT), specifically designed for wake-up receivers operating in the sub-GHz band. The proposed LNA achieves low noise, high gain, and good impedance matching while consuming only $3.2$ mA from a $3.3$ V supply, resulting in a total power consumption of $10.56$ mW. Designing efficient sub-GHz LNAs for low-power applications involves a careful balance between multiple performance metrics. Higher gain typically requires increased biasing current, which can raise power consumption, while achieving a low noise figure often conflicts with input-matching constraints. The presented design addresses these trade-offs by leveraging the BFP740 BJT and employing a stub-based microstrip matching network to simultaneously optimize the gain, noise figure, and input–output matching. Simulation results, using both external lumped elements and microstrip techniques, show a forward gain ($S_{21}$) of $15.2$ dB at 868 MHz, with an input reflection coefficient ($S_{11}$) of $-6.9$ dB and an output reflection coefficient ($S_{22}$) of $-6.3$ dB. The amplifier achieves a minimum noise figure of approximately $1.77$ dB, which is notably low for this frequency band. These results demonstrate that the proposed LNA offers a compact, energy-efficient, and cost-effective solution, ideally suited for always-on, low-power wireless applications such as Internet of Things (IoT) devices and wireless sensor networks. Full article

Compact, broadband, multi-channel RF chips with low loss and high integration are required for high-performance phased-array systems. Presented in this paper is a four-channel, multifunction RF chip operating in the 5–18 GHz frequency range that integrates broadband phase shifting, amplitude control, power amplification, and switching functions. The chip is designed to have flip-chip bonding and stacked gold bumps to enable the compact 3D integration of the GaAs pHEMT and Si-CMOS. To ensure high-density interconnects with minimal parasitic effects, a fan-in redistribution process is implemented. The RF front-end part of this chip, fabricated through a 0.15 µm GaAs pHEMT process, integrates 6-bit digital phase shifters, 6-bit digital attenuators, low-noise amplifiers (LNAs), power amplifiers (PAs), and single-pole double-throw (SPDT) switches. To enhance multi-channel isolation and reduce crosstalk between RF chips and digital circuits, high isolation techniques, including a ground-coupled shield layer in the fan-in process and on-chip shield cavities, are utilized, which achieve isolation levels greater than 41 dB between adjacent RF channels. The measurement results demonstrate a reception gain of 0 dB with ±0.6 dB flatness, an NF below 11 dB, and transmit gain of more than 10 dB, with a VSWR of below 1.6 over the entire 5–18 GHz frequency band. The 6-bit phase shifter achieves a root mean square (RMS) phase error below 2.5° with an amplitude variation of less than 0.8 dB, while the 6-bit attenuator exhibits an RMS attenuation error of below 0.5 dB and a phase variation of less than 7°. The RF and digital chips are heterogeneously integrated using flip-chip and fan-in technology, resulting in a compact chip size of 6.2 × 6.2 × 0.33 mm³. These results validate that this is a compact, high-performance solution for advanced phased-array radar applications. Full article

This article presents a low-noise amplifier (LNA) with high image rejection ratio (IRR) operating in the 5G millimeter-wave band using a 65 nm CMOS process. The circuit adopts an inter-stage notch filtering structure composed of a transformer and a switched capacitor array to achieve image suppression and impedance matching with no die area overhead. By adjusting the values of the switch capacitor array, the transmission zeros are positioned in the stopband while the poles are placed in the passband, thereby realizing image rejection. Furthermore, the number and distribution of poles under the both real and complex impedance conditions are analyzed. Moreover, the quality factor (Q) of the zero is derived to establish the relationship between Q and the image rejection ratio, guiding the optimization of both gain and IRR of the circuit design. Measurement results demonstrate that the LNA exhibits a gain of 18 dB and a noise figure (NF) of 4.4 dB at 40 GHz, with a corresponding IRR of 53.4 dB when the intermediate frequency (IF) is 6 GHz. The circuit demonstrates a 3 dB bandwidth from 36.3 to 40.7 GHz, with an IRR greater than 42 dB across this frequency range. The power consumption is 25.4 mW from a 1 V supply, and the pad-excluded core area of the entire chip is 0.13 mm². Full article

This work presents a novel three-stage low-noise amplifier (LNA) design methodology. The first two stages consist of common-source stages with inductive source degeneration, while the third stage consists of an RC network attached before the common-source FET transistor. The input matching network is designed to meet the optimum noise measurement termination, which results in a noise Figure of less than 1.6 dB. The highest gain level of 25 dB was measured, and the input and output reflection coefficients are better than 10 dB for the operating bandwidth, i.e., 13–15 GHz. The LNA’s large signal performance and robustness against continuous high input power and pulse waves are reported. This LNA can handle up to 15 dBm input pulse of 50 nS width and 10% duty cycle, and 18 dBm continuous wave without noticing an increment in the forward gate current. Full article

This paper presents a fully integrated bandpass filter (BPF) with high tunability based on a novel differential active inductor (DAI), designed for sensor interface circuits operating in the ultra-high frequency (UHF) band. The design of the proposed DAI is based on a symmetrical configuration, utilizing a differential amplifier for the feedforward transconductance and a common-source (CS) transistor for the feedback transconductance. By integrating a cascode scheme with a feedback resistor, the quality factor of the active inductor is significantly improved, leading to enhanced mid-band gain for the bandpass filter. To facilitate independent tuning of the BPF‘s center frequency and mid-band gain, an active resistor adjustment and bias voltage control are employed, providing precise control over the filter’s operational parameters. Post-layout simulations and process corner results are conducted with 0.13 µm CMOS technology at 1.2 V supply voltage. The proposed second order BPF achieves a broad tuning range of 280 MHz to 2.426 GHz, with a passband gain between 8.9 dB and 16.54 dB. The design demonstrates a maximum noise figure of 16.54 dB at 280 MHz, an input-referred 1 dB compression point of −3.78 dBm, and a third-order input intercept point (IIP3) of −0.897 dBm. Additionally, the BPF occupies an active area of only 68.2×30 µm², including impedance-matching part, and consumes a DC power of 14–20 mW. The compact size and low power consumption of the design make it highly suitable for integration into modern wireless sensor interfaces where performance and area efficiency are critical. Full article

This paper presents an ultra-wideband low-noise amplifier (LNA) with a new cross-coupling noise-canceling technique for 28 nm CMOS technology. The entire LNA contains two stages. The first stage employs inductively coupled Gm-boosted technology, while the second stage is a novel asymmetric cross-coupling noise-canceling structure (ACCNCS). Through the introduction of these two key techniques, the LNA achieves balanced performance across a relative bandwidth of 56%. Input/output/inter-stage impedance matching uses a transformer-based network with series-parallel combinations of inductors and capacitors. The LNA is designed in a 28 nm CMOS process with a chip core area of 335 × 665 µm². The operating frequency range is 26–46 GHz. Post-layout simulation results show that the peak gain of the LNA is 12.6 dB, and the noise figure is between 2.9 and 4.2 dB across the wideband range. At a center frequency of 36 GHz with a supply voltage (V_DD) of 0.9 V, the input 1 dB compression point (IP_1dB) is −7.6 dBm, while the power consumption is 22 mW. Full article