A 40 GHz High-Image-Rejection LNA with a Switchable Transformer-Based Notch Filter in 65 nm CMOS

Abstract

This article presents a low-noise amplifier (LNA) with high image rejection ratio (IRR) operating in the 5G millimeter-wave band using a 65 nm CMOS process. The circuit adopts an inter-stage notch filtering structure composed of a transformer and a switched capacitor array to achieve image suppression and impedance matching with no die area overhead. By adjusting the values of the switch capacitor array, the transmission zeros are positioned in the stopband while the poles are placed in the passband, thereby realizing image rejection. Furthermore, the number and distribution of poles under the both real and complex impedance conditions are analyzed. Moreover, the quality factor (Q) of the zero is derived to establish the relationship between Q and the image rejection ratio, guiding the optimization of both gain and IRR of the circuit design. Measurement results demonstrate that the LNA exhibits a gain of 18 dB and a noise figure (NF) of 4.4 dB at 40 GHz, with a corresponding IRR of 53.4 dB when the intermediate frequency (IF) is 6 GHz. The circuit demonstrates a 3 dB bandwidth from 36.3 to 40.7 GHz, with an IRR greater than 42 dB across this frequency range. The power consumption is 25.4 mW from a 1 V supply, and the pad-excluded core area of the entire chip is 0.13 mm².

1. Introduction

Millimeter wave technology plays a key role in fifth generation (5G) wireless communication, offering high bandwidth, low latency, and high data rates. The 5G millimeter-wave (mmWave) frequency band demonstrates significant system advantages through multi-band coordination, with the main operating frequency ranges including 24.25–27.5 GHz, 26.5–29.5 GHz, 27.5–28.35 GHz, and 37–40 GHz. In millimeter-wave transceiver front-end architectures, the low-noise amplifier (LNA) serves as a core module, and various innovative technical solutions have been developed to optimize its performance. Recent research on millimeter-wave LNA design has achieved remarkable progress. Numerous key technologies have been proposed to simultaneously achieve high gain and low noise figure (NF), significantly enhancing LNA performance [1,2,3,4]. Substantial research outcomes have also been obtained in broadband characteristics and low-power design [5,6]. However, in superheterodyne receivers, the nonlinear characteristics of the mixer cause both the desired signal and its image signal to be down-converted to the intermediate frequency (IF), resulting in signal overlap and interference. Therefore, image rejection techniques must be employed to suppress interference from the image frequency band, thereby improving the signal-to-noise ratio (SNR) of the received signal and ultimately enhancing overall system performance.

Several feasible methods have been proposed to address image interference issues. At the system level, the following approaches are currently available. For example, the transceiver front-end architecture incorporates a filter and implements an RF chopper switch to achieve transmitter self-interference suppression [7]. Alternatively, programmable RC networks can be incorporated into the transceiver system to achieve IF domain harmonic suppression and pre-calibration [8]. An IQ mixer can also be utilized for harmonic suppression to enhance anti-interference capability [9].

In addition to addressing image interference at the system level, incorporating filtering structures into the LNA can also achieve image rejection. In low-frequency circuits, LNAs utilize LC filter networks to enhance image rejection performance [10,11]. Additionally, a tri-coil electromagnetic coupling circuit is implemented to generate pole-zero pairs for further image frequency suppression [12,13]. At high frequencies, the following methods are also employed. For example, embedding filters within the LNA enables image rejection functionality [14,15]. Furthermore, a hybrid magnetic-electric coupling circuit architecture is proposed. This design precisely controls the cancelation effect between magnetic and electric coupling to generate transmission zeros outside the passband, achieving both image rejection and impedance transformation functionality [16]. The inter-stage and output matching networks incorporate switchable tri-coupled transformers and switchable capacitor arrays to achieve high image rejection performance [17]. A frequency-reconfigurable image rejection filter for the 5G FR2 band is proposed, utilizing a pole-zero inversion topology that switches between high-pass and low-pass modes to interchange poles and zeros [18]. However, this work only designs the filter and does not integrate it into a complete circuit.

For the application scenarios of multi-band millimeter wave receivers, there is a problem of image signal interference between different frequency bands [19,20,21,22,23]. As shown in Figure 1, when the receiver uses a local oscillator (LO) signal source for upper or lower sideband mixing reception, the signals in the 28 GHz and 40 GHz frequency bands will be mirror images of each other, and the corresponding IF will be 6 GHz.

Aiming at the challenges of achieving low noise amplification in the millimeter-wave receiving circuit as well as high image signal suppression, this article realizes 36.3–40.7 GHz LNA based on a 65 nm CMOS technology using a compact notch filter matching structure consisting of a transformer and a switch capacitor array. The organization of this article is as follows: Section 2 focuses on introducing the pole-zero analysis of the notch filter structure and the quality factor (Q) at zero and IRR effect; Section 3 presents the design method of the 40 GHz LNA; Section 4 demonstrates the experimental results of the LNA; and Section 5 draws the conclusions.

2. Analysis of the Switchable Transformer-Based Notch Filter

The proposed switchable notch filter is shown in Figure 2a. The filtering structure is composed of a transformer and a switchable capacitor. This structure establishes poles and zeros through the transformer and the capacitor. Furthermore, the positions of the poles and zeros can be adjusted using the switchable capacitor C_SW, so as to expand the operating range and achieve signal suppression over broadband frequencies.

When considering the situation of two cases in which the port impedance is classified into real impedance and complex impedance, respectively, the π-network models of the switchable filtering structure are shown in Figure 2b,c, and can be used to analyze its pole-zero characteristics.

2.1. Pole-Zero Analysis

First, consider the case in which the port impedance is real impedance, as shown in Figure 2b. At this time, the notch filter can be used as an independent filtering circuit. The transformer structure can be modeled as a π-type network, in which each inductor can be expressed as follows, where L_p and L_s are the primary and secondary coils of the inter-stage transformer, k is the transformer coupling coefficient, C_SW is the switch capacitance, and L_m is the mutual inductance between transformer windings, describing their magnetic coupling intensity:

$$L_1={\displaystyle \frac{L_p{L}_s-L_m^2}{L_s-L_m}},L_2={\displaystyle \frac{L_p{L}_s-L_m^2}{L_p-L_m}},L_3={\displaystyle \frac{\left(1-k^2\right)\sqrt{L_p{L}_s}}{k}}$$

(1)

In this design, Z₂₁ is used in simulations to clearly show the effect of poles and zeros on gain, while S₂₁ is used in measurements to match standard RF testing. For differential circuits with impedance matching, Z₂₁ and S₂₁ are related, and Z₂₁ trends qualitatively reflect S₂₁ responses. Therefore, Z₂₁ is used to obtain the poles and zeros of the circuit. The transfer impedance of the switchable notch filter, Z₂₁, can be derived as

$$Z_{21}={\displaystyle \frac{s\sqrt{L_p{L}_s}\left[k+s^2{C}_{SW}\sqrt{L_p{L}_s}\left(1-k^2\right)\right]}{1+s^2{C}_{SW}\left(L_p+L_s-2k\sqrt{L_p{L}_s}\right)}}$$

(2)

Accordingly, the transmission pole ω_p and transmission zero ω_z are as follows:

$${\omega }_p={\displaystyle \frac{1}{\sqrt{C_{SW}\left(L_p+L_s-2k\sqrt{L_p{L}_s}\right)}}}$$

(3)

$${\omega }_z=\sqrt{{\displaystyle \frac{1}{C_{SW}{L}_3}}}$$

(4)

It can be seen that when both the source impedance and load impedance are pure real impedance, this switchable notch filter structure has only one pole and one zero, as shown in Figure 3a. Furthermore, the pole-to-zero frequency ratio is

$${\displaystyle \frac{{\omega }_p}{{\omega }_z}}=\sqrt{{\displaystyle \frac{\left(1-k^2\right)\sqrt{L_p{L}_s}}{k\left(L_p+L_s-2k\sqrt{L_p{L}_s}\right)}}}$$

(5)

It can be found from (5) that the ratio of pole to zero only depends on the transformer parameters and is independent of C_SW. Therefore, by adjusting the switching capacitor value C_SW, it is possible to achieve a proportional migration of the poles and zeros, enabling pole-zero tracking.

When the switchable notch filter is integrated into a circuit, for example, embedded in an LNA as the inter-stage matching network to suppress the image signal, the impedances of its two ports are complex impedances. Under such circumstances, the port impedance can be expressed as the equivalent resistors (R_S, R_L) and capacitors (C_s, C_L) of the preceding and succeeding stage amplifiers, as shown in Figure 2c. The Z₂₁, pole expressions, and the ratio of pole to zero of the circuit can be expressed as follows:

$$Z_{21}=-{\displaystyle \frac{C_{SW}{L}_1{L}_2{L}_3{s}^3+L_1{L}_{2}s}{A{s}^4+B{s}^2+L_3+L_2+L_1}}$$

(6)

$${\omega }_{p1}=\sqrt{{\displaystyle \frac{C-\sqrt{D+E^2}}{2F}}},{\omega }_{p2}=\sqrt{{\displaystyle \frac{C+\sqrt{D+E^2}}{2F}}}$$

(7)

$${\displaystyle \frac{{\omega }_p}{{\omega }_z}}=\sqrt{{\displaystyle \frac{C_{SW}\left(C-\sqrt{D+E^2}\right)\left(\sqrt{L_p{L}_s}-k{L}_m\right)}{2Fk}}}$$

(8)

$$A=L_1{L}_2{L}_3\left(C_L\left(C_s+C_{SW}\right)+C_{SW}{C}_s\right)$$

(9)

$$B=L_1\left(\left(C_s+C_{SW}\right)L_3+\left(C_s+C_L\right)L_2\right)+L_2{L}_3\left(C_L+C_{SW}\right)$$

(10)

$$C=L_1\left(C_s{L}_2+C_{SW}{L}_3+C_s{L}_3+C_L{L}_2\right)+L_2{L}_3\left(C_L+C_{SW}\right)$$

(11)

$$D=-4L_1{L}_2{L}_3\left(L_1+L_2+L_3\right)\left(C_L{C}_s+C_{SW}\left(C_L+C_s\right)\right)$$

(12)

$$E=C_{SW}\left(L_1+L_2\right)L_3+C_L{L}_2\left(L_1+L_3\right)+C_s{L}_1\left(L_2+L_3\right)$$

(13)

$$F=L_1{L}_2{L}_3\left(C_L{C}_s+C_{SW}\left(C_L+C_s\right)\right)$$

(14)

Based on the poles and zeros derived from the complex impedance Z₂₁, one can deduce that there is a zero point in the complex impedance domain which coincides with the one in the real impedance domain. The difference, however, is that owing to the introduction of C_s or C_L, they resonate with L₁ and L₂, respectively, producing two poles. Moreover, under complex impedance conditions, when the C_SW changes, the second pole ω_p2 remains nearly unchanged, while only the first pole ω_p1 and the zero ω_z change accordingly, as shown in Figure 3b.

Furthermore, in the case of complex impedance, the pole to zero ratio depends not only on k and the impedance capacitors on both sides, but also on C_SW, meaning it is no longer independent of the switching capacitance. Figure 4 compares the ratio of poles to zeros (ratio) under two different port impedance conditions when the operating frequency and image frequency are 40 GHz and 28 GHz, respectively. It can be observed that, under complex impedance conditions, the pole to zero ratio slightly increases with the increase in C_SW, approximately maintaining a positive correlation.

2.2. Quality Factor at Zero and IRR of the Notch Filter

A notch filter can be used to implement an image rejection filter. That is, the zero point can be kept within the stopband and the pole within the passband to achieve the image rejection effect. At this point, it is necessary to minimize the loss at the poles and ensure that the notch depth at the zero is large enough to achieve the maximum IRR. The notch depth of the circuit is determined by the quality factor Q, so it is necessary to find the parameters that affect Q to ensure that the actual circuit exhibits good performance. When considering the parasitic resistance of notch filters, the Q value at the zero determines the overall image rejection of the structure. As shown in Figure 5, the transformer structure is first modeled as a T-model network. Taking into account the parasitic resistance of the inductors, the T-model structure is further transformed into a π-model structure to obtain the zero point network Z₁ of the notch filter. Consider the zero point network, which consists of a parallel resonant network consisting of the capacitor C_SW and the inductor L₃. When C_SW and L₃ resonate, the impedance is very high, and the signal is blocked from input to output, resulting in a zero point.

As shown in Figure 5, the Q of the zero network (Q_z) can be determined as follows, where R₃ is the parasitic resistance of L₃.

$$Q_z={\displaystyle \frac{\mathrm{Im}\left[Z_1\right]}{\mathrm{Re}\left[Z_1\right]}}={\displaystyle \frac{{\omega }_z{L}_3}{R_3}}$$

(15)

L_p1 and L_s1 are the inductors in the T-network model, and R_p and R_s are the parasitic resistances of L_p1 and L_s1. The relationship between R₃ of the π network and the parasitic resistance of the transformer is

$$R_3={\displaystyle \frac{R_p}{2}}\left(1+{\displaystyle \frac{L_{s1}}{L_m}}\right)+{\displaystyle \frac{R_s}{2}}\left(1+{\displaystyle \frac{L_{p1}}{L_m}}\right)$$

(16)

We can further derive the relationship of Q_z as shown in Equation (17).

$$Q_z={\displaystyle \frac{2\left(1-k^2\right)L_p{L}_s{\omega }_z}{L_s{R}_p+L_p{R}_s}}$$

(17)

Let the quality factors of the transformer coils L_p and L_s be Q_p and Q_s, respectively.

$$Q_p={\displaystyle \frac{\omega L_p}{R_p}},Q_s={\displaystyle \frac{\omega L_s}{R_s}}$$

(18)

Substitute Q_p and Q_s into Q_z to obtain the relationship between Q_z and Q_p, Q_s, as shown in Equation (19).

$${\displaystyle \frac{1}{Q_z}}={\displaystyle \frac{1}{2\left(1-k^2\right)}}\left({\displaystyle \frac{1}{Q_p}}+{\displaystyle \frac{1}{Q_s}}\right)\approx {\displaystyle \frac{1}{2}}\left({\displaystyle \frac{1}{Q_p}}+{\displaystyle \frac{1}{Q_s}}\right)$$

(19)

Figure 6 shows the relationship between IRR, Q_z, and Q_p, Q_s when the notch filter has been designed for a 40 GHz image rejection filter with the transmission zero located at 28 GHz. It can be observed that IRR and Q_z are directly proportional to Q_p and Q_s. During the design process, the maximum Q_p and Q_s can be selected to achieve the maximum Q_z. Since the IRR is primarily related to the quality factor at the zero point, a higher Q_z at the zero point results in greater IRR. When determining the structure of the transformer, it is necessary to maximize its quality factors Q_p and Q_s as much as possible and minimize the losses of the transformer in the design.

3. The 40 GHz LNA Circuit Design

3.1. Overall Circuit Design

A high-image-rejection LNA circuit with an operating frequency of 40 GHz was designed using 65 nm CMOS technology, as shown in Figure 7. The circuit consists of two stages of differential neutralized common-source structures, with M₁, M₂, M₃, and M₄ as differential common-source transistors. M₅ and M₆ act as switches for the switched capacitor array, while C₅ and C₆ are fixed capacitors that help adjust the switched capacitance. Capacitors C₁, C₂, C₃, and C₄ serve as neutralization capacitors. Transformers TF₁ and TF₂ provide input/output matching. Inductors L_p and L_s, together with C_SW, form the inter-stage notch filter. By introducing neutralization capacitors (C₁, C₂, C₃, C₄) to establish negative feedback paths, the gate-to-drain capacitance (C_gd) effects of the transistors are eliminated, thereby achieving improved gain and enhanced stability. The input and output matching network is composed of a pair of transformers for impedance matching. The inter-stage matching structure consists of a transformer and an array of two sets of switching capacitors, which together form a notch filter structure that achieves both inter-stage matching and out-of-band rejection. V_GS1 and V_GS2 are the gate voltages, V_DS is the drain voltage, and V_SW1 and V_SW2 are the switches of the switched capacitor array.

DC bias selection is crucial in circuit design. For maximum gain, drain voltage is set to the transistor’s 1 V safety limit. The gate voltage must optimize both the gain and noise figure in the differential common-source configuration. Figure 8 shows the simulated variation in maximum gain (MaxGain) and minimum noise figure (NFmin) of the differential common-source structure with respect to the gate voltage V_GS, while also considering the impact of gate-source voltage V_GS on power consumption.

As the gate voltage increases, the gain gradually rises and approaches a stable value, while the noise figure gradually decreases and then levels off. Meanwhile, power consumption increases with higher gate voltage. To meet gain and noise requirements under low-power conditions, the transistor’s maximum current handling capability must also be considered. In this case, a gate voltage of 0.5 V is chosen. Under the 65 nm CMOS process, the safe drain voltage for transistor testing is 1 V; therefore, a drain voltage of 1 V is selected in this work, and in the actual design, the bias lines are orthogonal to the transformer.

3.2. Switched Capacitor Array

The notch filter matching structure is a key part of circuit design, and by embedding it in the inter-stage of the amplifier, it can minimize the impact on the circuit gain and noise figure as much as possible. Based on the analysis in Section 2, the design process of the notch filter matching structure in this circuit is as follows:

Step 1: Considering that the impedance capacitors at both ends do not differ significantly, start by assuming that L_p = L_s. Using Equations (3)–(5), the parameters L_p, L_s, k, and C_SW under real impedance conditions can be determined. For example, when ω_p1 = 40 GHz, ω_z = 28 GHz, the values of L_p, L_s, k, and C_SW are obtained. These values are applicable to a single-ended circuit; in actual differential applications, the inductance values need to be multiplied by two.

Step 2: Based on Figure 4, under the same k, the pole-to-zero ratio for complex impedance is smaller than that for real impedance. Using the parameters L_p, L_s, k, and C_SW values obtained from Step 1 and substituting them into the complex impedance equations shows that the current pole-to-zero ratio will be reduced. To restore the pole-to-zero ratio to the desired value, k needs to be decreased to increase the pole-to-zero ratio.

Step 3: Adjust both k and C_SW for the complex impedance. While decreasing k, simultaneously adjust C_SW to move the zeros and poles to achieve the desired values.

Step 4: Based on the relationship of Q_z and the process characteristics, determine the physical dimensions of the transformer structure and capacitors.

Since the zero frequency of the inter-stage filtering structure needs to be set to 28 GHz, according to (1) and (4), it can be determined that the coupling coefficient k of the transformer satisfies k > 0, and the alternating current in the primary coil of the transformer is in the same direction. Therefore, the structure of the inter-stage transformer can be determined, as shown in Figure 9a. The coils L_p and L_s are designed with current in the same direction, and two additional inductors, L_s1 and L_s2, are introduced. Since the coils L_p and L_s do not overlap, both coils can be designed using the topmost thick metal layer (M9) to reduce losses. When connecting L_s1 and L_s2, the magnetic coupling between these inductors and L_s must be considered. Although this coupling coefficient is small, it affects the overall coupling coefficient of the transformer. Thus, L_s1 and L_s2 connections use another metal layer (M8), which has weaker coupling with the upper M9 layer, minimizing the impact on the overall coupling coefficient. The primary coil L_p of the inter-stage transformer has an inductance of 280 pH, while the secondary coil L_s has an inductance of 250 pH. The coupling coefficient between the primary and secondary coils is 0.13. The inductance values of L_s1 and L_s2 are 120 pH each, as shown in Figure 9b. Figure 9c shows the Q_p and Q_s of the actual transformer. As the frequency increases, the Q-factor first rises and then decreases, reaching above 16 for both Q_p and Q_s at 40 GHz.

The switched capacitor array consists of two parallel sections, each comprising a switched MOS transistor and two fixed capacitors. The switching action (ON/OFF) is controlled by the switched MOS gate voltage V_sw. When the gate voltage is at logic 1, the switch closes, equivalent to a resistor; at logic 0, it opens, equivalent to a capacitor. V_SW1 and V_SW2 represent the gate control voltages for each bit in the switching array, creating four possible states: 00, 01, 10, and 11. In this design, the 00 and 01 states do not provide optimal gain within the operational frequency band; therefore, only the 10 (State 1) and 11 (State 2) states are implemented in the final design. Considering the actual process, the larger the gate width of each switched MOS transistor, the higher its equivalent capacitance Q value in the ON state, and the smaller its equivalent resistance in the off state. Therefore, we chose switched MOS transistors with larger gate widths. For the design of fixed capacitors, we maximize the Q value of the capacitor by selecting appropriate metal layers and aspect ratios. By implementing the low loss matching design mentioned above, a high gain of the LNA circuit can be achieved. By selecting the appropriate capacitance value, specifically, when C_SW is in the range of 27–36 fF, the circuit can achieve an operating range covering 37–43 GHz. Therefore, C_SW values within this range were selected for the switched capacitor array. The capacitance value and Q-factor of the switched capacitor arrays are shown in Figure 10.

In Figure 3, the C_SW was designed based on the gate-drain impedance of the standalone differential common-source transistor. In Figure 10, the design also considers the effects of input/output matching networks, which alter the gate-drain impedance and adjust the C_SW capacitance accordingly. Additionally, at the 40 GHz operating frequency, the transformer’s inductance and coupling coefficient vary with frequency, causing differences between practical parameters and theoretical calculations, further affecting the C_SW value.

4. Measurement Results

Figure 11 shows the micrograph of the proposed LNA circuit with a core area of 0.13 mm² and a consumption of 25.4 mW at a 1 V supply.

As shown in Figure 12a, when the switching capacitor array is adjusted, the measured gain (S₂₁) reaches 16.3 dB at 40 GHz in State 1 and 18 dB in State 2. The circuit exhibits a 3 dB bandwidth of 36.3–40.7 GHz. As shown in Figure 12b, the measured IRR is 35.6 dB at 40 GHz in State 1 and improves to 53.4 dB in State 2 when the IF signal frequency is 6 GHz, meaning that the LNA circuit features high image-rejection capability. In the frequency range of 35–41.2 GHz, the IRR is consistently greater than 40 dB, while within 32–42 GHz, the IRR remains above 30 dB overall. As shown in Figure 13, at 40 GHz, the input reflection coefficient (S₁₁) is less than −10 dB in both switching states. Within the 37–42 GHz range, the S₁₁ remains below −10 dB across the entire band. The output reflection coefficient (S₂₂) is less than −15 dB in both switching states and the S₂₂ remains below −10 dB across the range of 33–50 GHz.

Compared to the simulation results, the measurements show a shift toward lower frequencies, primarily due to the accuracy issues of the MOS transistor model and the failure to account for the impact of MOS transistor switching on the transformer.

As shown in Figure 14a, at 40 GHz, the NF is 4.7 dB in State 1 and 4.4 dB in State 2, achieving good noise performance. As shown in Figure 14b, in State 1, the test result of input power at 1 dB compression point (IP1dB) in the 3 dB bandwidth is −14.9~−12.3 dBm, and in State 2, the test result of IP1dB in the 3 dB bandwidth is −16.2~−13.7 dBm. The linearity is satisfactory, and the results at 40 GHz are slightly higher than the simulation results because the gain values are lower than the results in the simulation.

To further analyze the factors affecting circuit performance, the impact of pole positions on linearity (such as IP1dB) is also investigated in this paper. As shown in Figure 15a, increasing the switching capacitor C_SW widens the spacing between the poles, leading to a broader bandwidth but a lower IP1dB, indicating reduced linearity. Conversely, decreasing C_SW narrows the bandwidth and increases IP1dB, thus improving linearity. Figure 15b illustrates that as the coupling coefficient k increases, the bandwidth decreases while IP1dB increases, resulting in enhanced linearity. When k is reduced, the bandwidth becomes wider, but IP1dB decreases, leading to poorer linearity. This is because in wideband circuits, gain variation across different frequencies is more pronounced. Certain frequencies may experience excessive amplification, pushing the circuit into compression and degrading linearity. Therefore, C_SW and k should be carefully optimized based on the target frequency to balance bandwidth and linearity, ensuring the LNA meets performance requirements.

To evaluate the robustness and reliability of the design, and to address the frequency discrepancies between measurements and simulations, transistor-level Monte Carlo simulations were further conducted based on this foundation. Figure 16a shows the S₂₁ simulation results under three process corners: tt, ff, and ss. The results indicate that the gain curves under the three process corners exhibit only minor deviations. Figure 16b and Figure 16c show the Monte-Carlo simulation results under State 1 and State 2, respectively, with 200 sample points generated for each.

Although the simulation results under the three process corners show minor variations, discrepancies with measurement results may still exist. The current Monte Carlo simulations only consider parameter variations in transistors and do not include process and environmental variations in passive components such as capacitors and inductors. Therefore, the simulation results may deviate from actual measurements. Passive components have a significant impact on high-frequency circuit performance, as they can influence parasitic parameters, quality factor (Q), and capacitance/inductance values, thereby affecting key metrics such as gain, bandwidth, and linearity. Future work should incorporate parameter variations in passive components and environmental effects into the simulations to achieve more accurate and comprehensive Monte Carlo analyses.

Table 1. Comparison of image rejection LNA performance.

Ref.	Technology	Freq/GHz	Peak Gain/dB	NF/dB	IRR/dB	Power/mW	Area/mm2	IP1dB/dBm
[3]	22-nm FD-SOI	19–36	21.5	1.7–2.2	6.5	17.3	0.05	−24.4~−23.4
		20–36	17.9	2.1–2.9		5.6
[4]	45-nm RF-SOI	27–46	21.2	2.74–3.24	21.2	25.5	0.38	−21
[13]	22-nm FD-SOI	21.6–34.2	32	2.3	>30	35	0.74	−37.2~−26.6
		21.5–26.5	32.4	2.7
		27.5–33	33.4	2.3
[14]	22-nm FD-SOI	20–44	28.5	3.3–5	>75	20.5	1.8 *	−29.5~−25
[15]	0.25-μm SiGe	29–37	28.5	3.1–4.1	>30	80	0.21 *	−22.1
[16]	28-nm CMOS	24–35	22	2.4–3.6	>25	26.8	0.13 *	−18.25
[17]	28-nm CMOS	23.8–33.5	18.1	2.5–3.5	>32.6	14	0.09 *	−19~−15.1
		34.4–41.4	18.9	2.8–3.5				−18.5~−15.2
This work	65-nm CMOS	36.3–40.7	18	4.4–4.9	40–53.4	25.4	0.13 *	−16.2

*: Excluding test pads.

shows the performance of the proposed LNAs and compares them to the state-of-the-art results, taking into account gain, NF, and IRR, as well as area, and the proposed high-image-rejection LNA based on inter-stage filtering structures maintains competitive overall performance in the above aspects.

5. Conclusions

This article presents a 40 GHz high-image-rejection low-noise amplifier implemented in 65 nm CMOS technology. To achieve superior image rejection, a switchable inter-stage filtering structure was developed. By strategically placing transmission zeros in the stopband and poles in the passband within this filtering structure, effective image rejection is realized. Notably, this architecture simultaneously performs impedance transformation while maintaining its filtering function. Measurement results demonstrate a gain of 18 dB with an NF of 4.4 dB at 40 GHz, while achieving outstanding image rejection of 53.4 dB at the target frequency. This design demonstrates significant advantages in image rejection and chip area, while operating at higher frequencies, making it particularly suitable for 5G millimeter-wave band circuit applications.