Search Results (130)

This paper introduces a 0.5–5.8 GHz low-noise amplifier (LNA) incorporating a gyrator-C-based active inductor (AI) and an enhanced deep trench isolation (DTI) electrostatic discharge (ESD) diode. Results suggest that AIs exhibit excellent consistency under various process voltage temperatures (PVTs) as well as input powers and the improved DTI diodes reduce parasitic capacitance by an average of 8.5% compared to conventional ones. In terms of circuit design, comprehensive analyses of gain flatness and noise are conducted. Fabricated using a 0.18 μm SiGe BiCMOS technology, the LNA delivers a high S21 of 18.3 ± 0.3 dB, a minimum noise figure of 2.6 dB, and an S11 and S22 of less than −10 dB over the entire frequency band. Operating from a 3.3 V supply voltage with a core area of 0.049 mm², it consumes 10 mA of current. Full article

This paper proposes relaxed Simultaneous Signal and Noise Matching (SSNM) conditions to address limitations in selecting source degeneration inductors for multistage LNA design, achieved by introducing controlled mismatches at the external ports. Additionally, a novel frequency-bounded mismatch envelope is introduced to guide load termination selection based on desired IM-OM (input mismatch-output mismatch) characteristics across the operating band. Building on these concepts, a systematic, easy-to-follow strategy is presented for implementing wideband multistage low-noise amplifiers (LNAs), significantly reducing reliance on blind CAD-based optimisation. This approach is validated through a three-stage MMIC LNA prototype, fabricated using a 0.15 μm GaAs process and operating from 28 to 34 GHz. The measured results closely match the simulation, demonstrating a stable gain of 23 ± 1 dB and a noise figure of 2–2.5 dB, confirming the practical effectiveness of the proposed design approach for wideband amplifiers. Full article

XSPICE models for a generic transmission line, a microstrip line, and coupled microstrips are presented. The developed models extend general-purpose circuit simulation tools using RF circuits design features. The models could be used for circuit simulation in frequency, DC, and time domains for any active or passive RF or microwave schematic (including microwave monolithic integrated circuits—MMICs) involving transmission lines. The presented models could be used with any circuit simulation backend supporting XSPICE extensions and could be integrated without patching the core simulator code. The presented XSPICE models for microstrip lines take into account the frequency dependency of characteristic impedance and dispersion. The models were designed using open-source circuit simulation software. This study provides a practical example of the low-noise RF amplifier (LNA) design with Ngspice simulation backend using the proposed models. Full article

This paper presents a wideband low-power/low-voltage 60-GHz low-noise amplifier (LNA) in a 28-nm bulk CMOS technology. The LNA has been designed for high-speed millimeter-wave (mm-wave) communications. It consists of two pseudo-differential amplifying stages and a buffer stage included for 50-Ohm on-wafer measurements. Two integrated input/output baluns guarantee both simultaneous 50-ohm input–noise/output matching at input/output radio frequency (RF) pads. A power-efficient design strategy is adopted to make the LNA suitable for low-power applications, while minimizing the noise figure (NF). Thanks to the adopted design strategy, the post-layout simulation results show an excellent trade-off between power gain and 3-dB bandwidth (BW_3dB) with 13.5 dB and 7 GHz centered at 60 GHz, respectively. The proposed LNA consumes only 11.6 mA from a 0.9-V supply voltage with an NF of 8.4 dB at 60 GHz, including the input transformer loss. The input 1 dB compression point (IP_1dB) of −15 dBm at 60 GHz confirms the first-rate linearity of the proposed amplifier. Human body model (HBM) electrostatic discharge (ESD) protection is guaranteed up to 2 kV at the RF input/output pads thanks to the input/output integrated transformers. Full article

This paper presents a 17–38 GHz wideband low-noise amplifier (LNA) designed in a 150-nm GaAs pHEMT process. The proposed amplifier adopts a cascode topology with an interstage inductor between the common-source (CS) and common-gate (CG) stages, and a series inductor at the source node of the CS stage for source degeneration. By incorporating these inductors in the amplification stage, simultaneous noise and input matching is facilitated, while achieving flat gain characteristics over a broad frequency range and ensuring stability. In addition, the amplification stage with inductors achieves input matching using only a shunt component in the DC bias path, without any series matching elements. This approach allows the amplifier to achieve simultaneous noise and input matching (SNIM), ensuring low-noise performance over a wide bandwidth. The simulation results show a flat gain of 20–23 dB and a low noise figure of 1.1–2.1 dB over the 17–38 GHz band. Full article

This paper presents a broadband near-field probe designed for measuring the normal magnetic field ($H_z$) in radio frequency (RF) circuits operating within a frequency range of 2–8 GHz. The proposed probe uses a cost-effective 4-layer printed circuit board (PCB) structure made with an FR-4 substrate. The probe primarily consists of an $H_z$ detection unit, a broadband microstrip balun, and a coaxial-like output. The broadband balun facilitates the conversion from differential to single-ended signals, thereby enhancing the probe’s common-mode rejection capability. This design ensures that the probe achieves both cost efficiency and high broadband measurement performance. Additionally, this work investigates the feasibility of employing microstrip lines as calibration standards for the $H_z$ probe. The probe’s structural parameters and magnetic field response were initially determined through simulations, and the calibration factor was subsequently verified by calibration experiments. In practical measurements, the field distributions above a microstrip line and a low-noise amplifier (LNA) were captured. The measured field distribution of the microstrip line was compared with simulation results to verify the probe’s performance. Meanwhile, the measured field distribution of the LNA was utilized to identify the radiating components within the amplifier. Full article

This paper presents an optimized 868 MHz low-noise amplifier (LNA) based on a bipolar junction transistor (BJT), specifically designed for wake-up receivers operating in the sub-GHz band. The proposed LNA achieves low noise, high gain, and good impedance matching while consuming only $3.2$ mA from a $3.3$ V supply, resulting in a total power consumption of $10.56$ mW. Designing efficient sub-GHz LNAs for low-power applications involves a careful balance between multiple performance metrics. Higher gain typically requires increased biasing current, which can raise power consumption, while achieving a low noise figure often conflicts with input-matching constraints. The presented design addresses these trade-offs by leveraging the BFP740 BJT and employing a stub-based microstrip matching network to simultaneously optimize the gain, noise figure, and input–output matching. Simulation results, using both external lumped elements and microstrip techniques, show a forward gain ($S_{21}$) of $15.2$ dB at 868 MHz, with an input reflection coefficient ($S_{11}$) of $-6.9$ dB and an output reflection coefficient ($S_{22}$) of $-6.3$ dB. The amplifier achieves a minimum noise figure of approximately $1.77$ dB, which is notably low for this frequency band. These results demonstrate that the proposed LNA offers a compact, energy-efficient, and cost-effective solution, ideally suited for always-on, low-power wireless applications such as Internet of Things (IoT) devices and wireless sensor networks. Full article

Compact, broadband, multi-channel RF chips with low loss and high integration are required for high-performance phased-array systems. Presented in this paper is a four-channel, multifunction RF chip operating in the 5–18 GHz frequency range that integrates broadband phase shifting, amplitude control, power amplification, and switching functions. The chip is designed to have flip-chip bonding and stacked gold bumps to enable the compact 3D integration of the GaAs pHEMT and Si-CMOS. To ensure high-density interconnects with minimal parasitic effects, a fan-in redistribution process is implemented. The RF front-end part of this chip, fabricated through a 0.15 µm GaAs pHEMT process, integrates 6-bit digital phase shifters, 6-bit digital attenuators, low-noise amplifiers (LNAs), power amplifiers (PAs), and single-pole double-throw (SPDT) switches. To enhance multi-channel isolation and reduce crosstalk between RF chips and digital circuits, high isolation techniques, including a ground-coupled shield layer in the fan-in process and on-chip shield cavities, are utilized, which achieve isolation levels greater than 41 dB between adjacent RF channels. The measurement results demonstrate a reception gain of 0 dB with ±0.6 dB flatness, an NF below 11 dB, and transmit gain of more than 10 dB, with a VSWR of below 1.6 over the entire 5–18 GHz frequency band. The 6-bit phase shifter achieves a root mean square (RMS) phase error below 2.5° with an amplitude variation of less than 0.8 dB, while the 6-bit attenuator exhibits an RMS attenuation error of below 0.5 dB and a phase variation of less than 7°. The RF and digital chips are heterogeneously integrated using flip-chip and fan-in technology, resulting in a compact chip size of 6.2 × 6.2 × 0.33 mm³. These results validate that this is a compact, high-performance solution for advanced phased-array radar applications. Full article

This article presents a low-noise amplifier (LNA) with high image rejection ratio (IRR) operating in the 5G millimeter-wave band using a 65 nm CMOS process. The circuit adopts an inter-stage notch filtering structure composed of a transformer and a switched capacitor array to achieve image suppression and impedance matching with no die area overhead. By adjusting the values of the switch capacitor array, the transmission zeros are positioned in the stopband while the poles are placed in the passband, thereby realizing image rejection. Furthermore, the number and distribution of poles under the both real and complex impedance conditions are analyzed. Moreover, the quality factor (Q) of the zero is derived to establish the relationship between Q and the image rejection ratio, guiding the optimization of both gain and IRR of the circuit design. Measurement results demonstrate that the LNA exhibits a gain of 18 dB and a noise figure (NF) of 4.4 dB at 40 GHz, with a corresponding IRR of 53.4 dB when the intermediate frequency (IF) is 6 GHz. The circuit demonstrates a 3 dB bandwidth from 36.3 to 40.7 GHz, with an IRR greater than 42 dB across this frequency range. The power consumption is 25.4 mW from a 1 V supply, and the pad-excluded core area of the entire chip is 0.13 mm². Full article

This work presents a novel three-stage low-noise amplifier (LNA) design methodology. The first two stages consist of common-source stages with inductive source degeneration, while the third stage consists of an RC network attached before the common-source FET transistor. The input matching network is designed to meet the optimum noise measurement termination, which results in a noise Figure of less than 1.6 dB. The highest gain level of 25 dB was measured, and the input and output reflection coefficients are better than 10 dB for the operating bandwidth, i.e., 13–15 GHz. The LNA’s large signal performance and robustness against continuous high input power and pulse waves are reported. This LNA can handle up to 15 dBm input pulse of 50 nS width and 10% duty cycle, and 18 dBm continuous wave without noticing an increment in the forward gate current. Full article

The global allocation of over 5 GHz of spectral bandwidth around the 60 GHz frequency band offers significant potential for ultra-high data rate wireless communication over short distances and enables the implementation of high-resolution frequency-modulated continuous-wave (FMCW) radar applications. In this study, a Front-End Receiver covering frequencies from 57 to 64 GHz was designed and characterized in a 40 nm CMOS process. The proposed architecture includes a Low-Noise Amplifier (LNA), a novel double-balanced mixer offering variable conversion gain, and a low-power class-C Voltage-Controlled Oscillator (VCO). From post-layout simulation results, the LNA presents a noise figure (NF) less than 4.8 dB and a gain more than 19 dB, while the input compression point (P1dB) reaches −15.6 dBm. The double-balanced mixer delivers a noise figure of less than 11 dB, a conversion gain of 14 dB, and an input-referred compression point of −13 dBm. The VCO achieves a phase noise of approximately −93 dBc/Hz at 1 MHz offset from 60 GHz and a tuning range of about 8 GHz, dissipating only 6.6 mW. Overall, the receiver demonstrates a maximum conversion gain of more than 39 dB, a noise figure of less than 9.2 dB, an input- referred compression point of −37 dBm, and a power dissipation of 56 mW. Full article

This manuscript provides insight into optimally noise-matched three-stage Low-Noise Amplifiers (LNAs) by proposing a novel chart that illustrates the relationship between the gain of a three-stage LNA and inter-stage mismatch levels. Under certain conditions, the chart also indicates the required feedback inductor values for all transistors. It is demonstrated that, under the specific assumption of optimal noise and signal matching, the LNA gain depends on the levels of two inter-stage mismatches. Contrary to common belief, the results show that the LNA gain increases as the inter-stage mismatch levels rise. This finding is supported through the discussion of two LNA designs, one with lower and one with higher inter-stage mismatch levels, achieving gains of 24 dB and 26 dB, respectively, with a Noise Figure of 1.7 dB at the center design frequency of 28 GHz. Subsequently, one LNA topology is validated in a Monolithic Microwave Integrated Circuit (MMIC) implementation using WIN Foundry’s PIH1-10 GaAs E-mode technology. The MMIC characterization aligns with the simulated behavior, accounting for the unavoidable losses in the matching networks. Full article

This paper presents an ultra-wideband low-noise amplifier (LNA) with a new cross-coupling noise-canceling technique for 28 nm CMOS technology. The entire LNA contains two stages. The first stage employs inductively coupled Gm-boosted technology, while the second stage is a novel asymmetric cross-coupling noise-canceling structure (ACCNCS). Through the introduction of these two key techniques, the LNA achieves balanced performance across a relative bandwidth of 56%. Input/output/inter-stage impedance matching uses a transformer-based network with series-parallel combinations of inductors and capacitors. The LNA is designed in a 28 nm CMOS process with a chip core area of 335 × 665 µm². The operating frequency range is 26–46 GHz. Post-layout simulation results show that the peak gain of the LNA is 12.6 dB, and the noise figure is between 2.9 and 4.2 dB across the wideband range. At a center frequency of 36 GHz with a supply voltage (V_DD) of 0.9 V, the input 1 dB compression point (IP_1dB) is −7.6 dBm, while the power consumption is 22 mW. Full article

This paper presents the design analysis of a low-power wideband single-ended CMOS low-noise amplifier (LNA). The proposed topology is based on a modified current- reuse circuit, in which two-stage common-source (CS) amplifiers consume the same DC current and are isolated from each other by large MIMCAPs, which results in good performance with low power consumption. The proposed circuit achieves a bandwidth of 2.5 GHz, suitable for several wireless communication standards such as GSM, WLAN, and Bluetooth. In the first stage, a current-reuse circuit with shunt feedback is used to satisfy input impedance matching and signal amplification with minimal noise injection. A common source (CS) with a source follower circuit forms the second stage to improve the noise figure (NF), harmonic distortion, and output impedance matching. The proposed LNA is designed in 65 nm CMOS technology and covers a frequency range of 0.17–2.68 GHz. The proposed LNA achieves a maximum gain of 17.24 dB, a minimum NF of 2.67 dB, a maximum IIP3 of −14.9 dBm, and input and output return losses of less than −10 dB. The power consumption of the proposed LNA is 3.52 mW from a 1 V power supply, and the core area is 0.3 mm². Full article

In this paper, a four-channel optical emission module is developed using hybrid integration technology that integrates directly modulated laser (DML) chips, low-noise amplifier (LNA) chips, and control circuits, with dimensions of 24.4 mm × 21 mm × 5.9 mm. This module enables high-gain signal output and minimizes crosstalk between neighboring channels while improving integration. An equivalent circuit model of radio frequency (RF) signal transmission is established, and the accuracy of the model and the effectiveness of the approach to improve signal gain are verified using simulations and experiments. With optimized thermal management, the module has the ability to operate at stable temperatures across an ambient range of −55 °C to 75 °C. The module has a channel wavelength spacing of approximately 1 nm, and the −3 dB bandwidth of each channel exceeds 20 GHz. The crosstalk between neighboring channels is less than −65 dB. In the range of 0.8~25 GHz, the four-channel gain is approximately 15 dB through the integration of the LNA chip. The module achieves a noise figure (NF) of less than 30 dB. Full article