Search Results (80)

The gate reliability issues in SiC-based devices with a gate dielectric formed through heat oxidation are important factors limiting their application in power devices. Aluminum oxide (Al₂O₃) and titanium dioxide (TiO₂) were combined using the ALD process to form a composite AlTiO gate dielectric on a 4H-SiC substrate. TDMAT and TMA were the precursors selected and deposited at 200 °C, and the samples were Ar or N₂ annealed at temperatures ranging from 300 °C to 700 °C. An XPS analysis suggested that the AlTiO film had been deposited with a high overall quality and the involvement of Ti atoms had increased the interfacial bonding with the substrate. The as-deposited MOS structure had band shifts of ΔE_C = 1.08 eV and ΔE_V = 2.41 eV. After annealing, the AlTiO bandgap increased by 0.85 eV at most, and better band alignment was attained. Leakage current and breakdown voltage characteristic investigations were conducted after Al electrode deposition. The leakage current density and electrical breakdown field of an MOS capacitor structure with a SiC substrate were ~10⁻³ A/cm² and 6.3 MV/cm, respectively. After the annealing process, both the measures of the JV performance of the MOS capacitor had improved to ~10⁻⁶ A/cm² and 7.2 MV/cm. The interface charge N_eff of the AlTiO layer was 4.019 × 10¹⁰ cm⁻². The AlTiO/SiC structure fabricated in this work proved the feasibility of adjusting the properties of single-component gate dielectric materials using the ALD method, and using a suitable thermal annealing process has great potential to improve the performance of the compound MOS dielectric layer. Full article

The advancement of portable high-definition organic light-emitting diode (OLED) displays necessitates thin film transistors (TFTs) with low power consumption and high pixel density. Amorphous indium gallium zinc oxide (a-IGZO) TFTs are promising candidates to meet these requirements. However, conventional silicon dioxide gate insulators provide limited channel modulation due to their low dielectric constant, while alternative high-k dielectrics often suffer from high leakage currents and poor surface quality. Plasma-enhanced atomic layer deposition (PEALD) enables the atomic-level control of film thickness, resulting in high-quality films with superior conformality and uniformity. In this work, a systematic investigation was conducted on the properties of HfO₂ films and the electrical characteristics of a-IGZO TFTs with different HfO₂ thicknesses. A Vth of −0.9 V, μ_sat of 6.76 cm²/Vs, SS of 0.084 V/decade, and I_on/I_off of 1.35 × 10⁹ are obtained for IGZO TFTs with 40 nm HfO₂. It is believed that the IGZO TFTs based on a HfO₂ gate insulating layer and prepared by PEALD can improve electrical performance. Full article

This work systematically analyses the electrical and structural properties of a bilayer gate dielectric composed of Sm₂O₃ and ZrO₂ on a 4H-SiC substrate. The bilayer thin film was fabricated using a sputtering process, followed by a dry oxidation step with an adjusted oxygen-to-nitrogen (O₂:N₂) gas concentration ratio. XRD analysis validated formation of an amorphous structure with a monoclinic phase for both Sm₂O₃ and ZrO₂ dielectric thin films. High-resolution transmission emission (HRTEM) analysis verified the cross-section of fabricated stacking layers, confirmed physical oxide thickness around 12.08–13.35 nm, and validated the amorphous structure. Meanwhile, XPS confirmed the presence of more stoichiometric dielectric oxide formation for oxidized/nitrided O₂:N₂-incorporated samples, and more sub-stochiometric thin films for samples only oxidized in ambient O₂. The oxidation/nitridation processes with N₂ incorporation influenced the band offsets and revealed conduction band offsets (CBOs) ranging from 2.24 to 2.79 eV. The affected charge movement and influenced electrical performance where optimized samples with gas concentration ratio of 90% O₂:10% N₂ achieved the highest electrical breakdown field of 10.1 MV cm⁻¹ at a leakage current density of 10⁻⁶ A cm⁻². This gate stack also improved key parameters such as the effective dielectric constant ($k_{eff}$) up to 29.75, effective oxide charge ($Q_{eff}$), average interface trap density ($D_{it}$), and slow trap density (STD). The bilayer gate stack of Sm₂O₃ and ZrO₂ revealed potential attractive characteristics as a candidate for high-k gate dielectric applications in metal-oxide-semiconductor (MOS)-based devices. Full article

This paper proposes a 1200V 4H-SiC MOSFET incorporating a High-K dielectric-integrated fused source-gate (HKSG) structure, engineered to concurrently enhance the third-quadrant operation and high-frequency figure of merit (HF-FOM). The High-K dielectric enhances the electric field effect, reducing the threshold voltage of the source-gate. As a result, the reverse conduction voltage drops from 2.79 V (body diode) to 1.53 V, and the bipolar degradation is eliminated. Moreover, by incorporating a shielding area within the merged source-gate architecture, the gate-to-drain capacitance C_gd of the HKSG-MOS is reduced. The simulation results show that the HF-FOM C_gd × R_on,sp and Q_gd × R_on,sp of the HKSG-MOS are decreased by 48.1% and 58.9%, respectively, compared with that of conventional SiC MOSFET. The improved performances make the proposed SiC MOSFEET have great potential in high-frequency power applications. Full article

This paper presents an advanced dielectric engineering approach utilizing a composition-dependent hafnium zirconium oxide (Hf_1-xZr_xO₂) superlattice (SL) structure for Si nanosheet gate-all-around field-effect transistors (Si NSGAAFETs). The dielectric (DE) properties of solid solution (SS) and SL Hf_1-xZr_xO₂ capacitors were systematically characterized through capacitance-voltage (C-V) and polarization-voltage (P-V) measurements under varying annealing conditions. A high dielectric constant (k-value) of 59 was achieved in SL-Hf_0.3Zr_0.7O₂, leading to a substantial reduction in equivalent oxide thickness (EOT). Furthermore, the SL-Hf_0.3Zr_0.7O₂ dielectric was integrated into Si NSGAAFETs, with the interfacial layer (IL) further optimized via NH₃ plasma treatment. The resulting devices exhibited superior electrical performance, including an enhanced ON-OFF current ratio (I_ON/I_OFF) reaching 10⁷, an increased drive current, and significantly reduced gate leakage. These results highlight the potential of SL-Hf_0.3Zr_0.7O₂ as a high-k dielectric solution for overcoming EOT scaling challenges in advanced CMOS technology and enabling further innovation in next-generation logic applications. Full article

In the context of increasing digitalization and the emergence of applications such as smart cities, embedded devices are becoming ever more pervasive, mobile, and ubiquitous. Due to increasing concerns around energy efficiency, gate density, and scalability in the semiconductor industry, there has been much interest recently in the fabrication of viable low-power energy-efficient devices. The Hetero-Dielectric Gate-All-Around (HD-GAA) MOSFET represents a cutting-edge transistor architecture designed for superior sustainability and energy efficiency, improving the overall efficiency of the system by reducing leakage and enhancing gate control; therefore, as part of the transition to a sustainable future, several semiconductor industries, including Intel, Samsung, Texas Instruments, and IBM, are using this technology. In this study, Hetero-Dielectric Single-Metal Gate-All-Around MOSFET (HD-SM-GAA MOSFET) devices and circuits were designed using Schottky source/drain contacts and tunable high-k dielectric Hf_xTi_1−xO₂ in the TCAD simulator using the following specifications: N-Channel HD-SM-GAA MOSFET (‘Device-I’) with a 5 nm radius and a 21 nm channel length alongside two P-Channel HD-SM-GAA MOSFETs (‘Device-II’ and ‘Device-III’) with radii of 5 nm and 8 nm, respectively, maintaining the same channel length. Thereafter, the inverters were implemented using these devices in the COGENDA TCAD simulator. The results demonstrated significant reductions in short-channel effects: subthreshold swing (SS) (‘Device-I’ = 61.5 mV/dec, ‘Device-II’ = 61.8 mV/dec) and drain-induced barrier lowering (DIBL) (‘Device-I’ = 8.2 mV/V, ‘Device-II’ = 8.0 mV/V) in comparison to the existing literature. Furthermore, the optimized inverters demonstrated significant improvements in noise margin values such as Noise Margin High (NM_H) and Noise Margin Low (NM_L), with Inverter-1 showing 38% and 44% enhancements and Inverter-2 showing 40% and 37% enhancements, respectively, compared to the existing literature. The results achieved illustrate the potential of using this technology (e.g., for power inverters) in embedded power control applications where energy efficiency and scalability are important, such as sustainable smart cities. Full article

The progression of SiC MOSFET technology from planar to trench structures requires optimized gate oxide layers within the trench to enhance device performance. In this study, we investigated the interface characteristics of HfO₂ and SiO₂/HfO₂ gate dielectrics grown by atomic layer deposition (ALD) on SiC trench structures. The trench structure morphology was revealed using scanning electron microscopy (SEM). Atomic force microscopy (AFM) measurements showed that the roughness of both films was below 1nm. Spectroscopic ellipsometry (SE) indicated that the physical thicknesses of HfO₂ and SiO₂/HfO₂ were 38.275 nm and 40.51 nm, respectively, demonstrating their comparable thicknesses. X-ray photoelectron spectroscopy (XPS) analysis of the gate dielectrics revealed almost identical Hf 4f core levels for both HfO₂ and the SiO₂/HfO₂ composite dielectrics, suggesting that the SiO₂ interlayer and the SiC substrate had minimal impact on the electronic structure of the HfO₂ film. The breakdown electric field of the HfO₂ film was recorded as 4.1 MV/cm, with a leakage current at breakdown of 1.1 × 10⁻³A/cm². The SiO₂/HfO₂ stacked film exhibited significantly better performance, with a breakdown electric field of 6.5 MV/cm and a marked reduction in leakage current to 3.7 × 10⁻⁴ A/cm². A detailed extraction and analysis of the leakage current mechanisms were proposed, and the data suggested that the introduction of thin SiO₂ interfacial layers effectively mitigated small bandgap offset issues, significantly reducing leakage current and improving device performance. Full article

The short-circuit (SC) robustness of SiC MOSFETs is critical for high-power applications, yet 1.2 kV devices often struggle to meet the industry-standard SC withstand time (SCWT) under practical operating conditions. Despite growing interest in higher voltage classes, no prior study has systematically evaluated the SC performance of 1.7 kV SiC MOSFETs. This study provides the first comprehensive evaluation of commercially available 1.7 kV SiC MOSFETs, analyzing their SC performance under varying electrical stress conditions. Results indicate a clear trade-off between SC withstand time (SCWT) and drain-source voltage (V_DS), with SCWT decreasing from 32 µs at 400 V to 4 µs at 1100 V. Under 600 V, a condition representative of practical use cases in many high-voltage applications, the devices achieved an SCWT of 12 µs, exceeding the industry-standard 10 µs benchmark—a threshold often unmet by 1.2 kV devices under similar conditions. Failure analysis revealed gate dielectric breakdown as the dominant failure mode at V_DS ≤ 600 V, while thermal runaway was observed at higher voltages (V_DS = 800 V and 1100 V). These findings underscore the critical importance of robust gate drive designs and effective thermal management. By surpassing the shortcomings of lower voltage classes, 1.7 kV SiC MOSFETs can be a more reliable, and efficient choice for operating at higher voltages in next-generation power systems. Full article

This paper reviews the recent development of organic–inorganic hybrid dielectric materials for application as gate dielectrics in thin-film transistors (TFTs). These hybrid materials consist of the blending of high-k inorganic dielectrics with polymers, and their resulting properties depend on the amount and type of interactions between the organic and inorganic phases. The resulting amorphous networks, characterized by crosslinked organic and inorganic phases, can be tailored for specific applications, including gate dielectrics in TFTs. As dielectric materials, they offer a synergistic combination of high dielectric constants, low leakage currents, and mechanical flexibility, crucial for next-generation flexible electronics. Furthermore, organic–inorganic hybrid materials are easily processed in solution, allowing for low-temperature deposition compatible with flexible substrates. Various configurations of these hybrid gate dielectrics, such as bilayer structures and polymer nanocomposites, are discussed, with an emphasis on their potential to enhance device performance. Despite the significant advancements, challenges remain in optimizing the performance and stability of these hybrid materials. This review summarizes recent progress and highlights the advantages and emerging applications of low-temperature, solution-processed hybrid dielectrics, with a focus on their integration into flexible, stretchable, and wearable electronic devices. Full article

This work investigates the gate oxide reliability of commercial 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The performance of threshold voltage $\left({\mathrm{V}}_{\mathrm{t}\mathrm{h}}\right)$ and gate leakage current $\left({\mathrm{I}}_{\mathrm{g}\mathrm{s}\mathrm{s}}\right)$ in SiC MOSFETs is evaluated under positive and negative gate voltage stress. The oxide lifetimes of SiC planar and trench MOSFETs at 150 °C are measured using constant voltage Time-Dependent Dielectric Breakdown (TDDB) testing. From the test results, it is found that electron trapping and hole trapping in ${\mathrm{S}\mathrm{i}\mathrm{O}}_2$ caused by oxide electric field $\left({\mathrm{E}}_{\mathrm{o}\mathrm{x}}\right)$ stress affect the ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$ of SiC MOSFETs. The saturation and turnaround behavior of the ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$ shift during positive and negative gate voltage stresses indicates that the influence of charge trapping in the gate oxide varies with stress time. The ${\mathrm{I}}_{\mathrm{g}\mathrm{s}\mathrm{s}}$ under positive and negative gate voltages depends on the tunneling barrier height for electrons and holes, respectively, which can be calculated using the Fowler–Nordheim (FN) tunneling mechanism. Moreover, the presence of near-interface traps (NITs) affects the barrier height for holes under negative gate voltages. The behavior of ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$ shift and ${\mathrm{I}}_{\mathrm{g}\mathrm{s}\mathrm{s}}$ under high-temperature gate bias reflects the charge trapping occurring in different regions of the gate oxide. In addition, compared to SiC planar MOSFETs, SiC trench MOSFETs with thicker gate oxide tend to exhibit higher lifetimes in TDDB tests. Full article

In this paper, we propose an ultrascaled WS₂ field-effect transistor equipped with a Pd/Pt sensitive gate for high-performance and low-power hydrogen gas sensing applications. The proposed nanosensor is simulated by self-consistently solving a quantum transport equation with electrostatics at the ballistic limit. The gas sensing principle is based on the gas-induced change in the metal gate work function. The hydrogen gas nanosensor leverages the high sensitivity of two-dimensional WS2 to its sur-rounding electrostatic environment. The computational investigation encompasses the nanosensor’s behavior in terms of potential profile, charge density, current spectrum, local density of states (LDOS), transfer characteristics, and sensitivity. Additionally, the downscaling-sensitivity trade-off is analyzed by considering the impact of drain-to-source voltage and the electrostatics parameters on subthreshold performance. The simulation results indicate that the downscaling-sensitivity trade-off can be optimized through enhancements in electrostatics, such as utilizing high-k dielectrics and reducing oxide thickness, as well as applying a low drain-to-source voltage, which also contributes to improved energy efficiency. The proposed nanodevice meets the prerequisites for cutting-edge gas nanosensors, offering high sensing performance, improved scaling capability, low power consumption, and complementary metal–oxide–semiconductor compatibility, making it a compelling candidate for the next generation of ultrascaled FET-based gas nanosensors. Full article

Feedback field-effect transistors (FBFETs) have been studied to obtain near-zero subthreshold swings at 300 K with a high on/off current ratio ~10¹⁰. However, their structural complexity, such as an epitaxy process after an etch process for a Si channel with a thickness of several nanometers, has limited broader research. We demonstrated a FBFET using in-plane WSe₂ p−n homojunction. The WSe₂ FBFET exhibited a minimum subthreshold swing of 153 mV/dec with 30 nm gate dielectric. Our modeling-based projection indicates that the swing of this device can be reduced to 14 mV/dec with 1 nm EOT. Also, the gain of the inverter using the WSe₂ FBFET can be improved by up to 1.53 times compared to a silicon CMOS inverter, and power consumption can be reduced by up to 11.9%. Full article

The development of metal–insulator–semiconductor (MIS) capacitors requires device miniaturization and excellent electrical properties. Traditional SiO₂ gate dielectrics have reached their physical limits. In this context, high-k materials such as TiO₂ are emerging as promising alternatives to SiO₂. However, the deposition of dielectric layers in MIS capacitors typically requires high-vacuum equipment and challenging processing conditions. Therefore, in this study, we present a new method to effectively fabricate a poly(vinylidene fluoride) (PVDF)-based TiO₂ dielectric layer via electrospinning. Nano-microscale layers were formed via electrospinning by applying a high voltage to a polymer solution, and electrical properties were analyzed as a function of the TiO₂ crystalline phase and residual amount of PVDF at different annealing temperatures. Improved electrical properties were observed with increasing TiO₂ anatase content, and the residual amount of PVDF decreased with increasing annealing temperature. The sample annealed at 600 °C showed a lower leakage current than those annealed at 300 and 450 °C, with a leakage current density of 7.5 × 10⁻¹³ A/cm² when Vg = 0 V. Thus, electrospinning-based coating is a cost-effective method to fabricate dielectric thin films. Further studies will show that it is flexible and dielectric tunable, thus contributing to improve the performance of next-generation electronic devices. Full article

The surge in demand for 3D MOSFETs, such as FinFETs, driven by recent technological advances, is explored in this review. FinFETs, positioned as promising alternatives to bulk CMOS, exhibit favorable electrostatic characteristics and offer power/performance benefits, scalability, and control over short-channel effects. Simulations provide insights into functionality and leakage, addressing off-current issues common in narrow band-gap materials within a CMOS-compatible process. Multiple structures have been introduced for FinFETs. Moreover, some studies on the fabrication of FinFETs using different materials have been discussed. Despite their potential, challenges like corner effects, quantum effects, width quantization, layout dependencies, and parasitics have been acknowledged. In the post-planar CMOS landscape, FinFETs show potential for scalability in nanoscale CMOS, which leads to novel structures for them. Finally, recent developments in FinFET-based sensors are discussed. In a general view, this comprehensive review delves into the intricacies of FinFET fabrication, exploring historical development, classifications, and cutting-edge ideas for the used materials and FinFET application, i.e., sensing. Full article

The application of GaN HEMTs on silicon substrates in high-voltage environments is significantly limited due to their complex buffer layer structure and the difficulty in controlling wafer warpage. In this work, we successfully fabricated GaN power HEMTs on 6-inch sapphire substrates using a CMOS-compatible process. A 1.5 µm thin GaN buffer layer with excellent uniformity and a 20 nm in situ SiN gate dielectric ensured uniformly distributed V_TH and R_ON across the entire 6-inch wafer. The fabricated devices with an L_GD of 30 µm and W_G of 36 mm exhibited an R_ON of 18.06 Ω·mm and an off-state breakdown voltage of over 3 kV. The electrical mapping visualizes the high uniformity of R_ON and V_TH distributed across the whole 6-inch wafer, which is of great significance in promoting the applications of GaN power HEMTs for medium-voltage power electronics in the future. Full article