Properties of Bilayer Zr- and Sm-Oxide Gate Dielectric on 4H-SiC Substrate Under Varying Nitrogen and Oxygen Concentrations

Abstract

This work systematically analyses the electrical and structural properties of a bilayer gate dielectric composed of Sm₂O₃ and ZrO₂ on a 4H-SiC substrate. The bilayer thin film was fabricated using a sputtering process, followed by a dry oxidation step with an adjusted oxygen-to-nitrogen (O₂:N₂) gas concentration ratio. XRD analysis validated formation of an amorphous structure with a monoclinic phase for both Sm₂O₃ and ZrO₂ dielectric thin films. High-resolution transmission emission (HRTEM) analysis verified the cross-section of fabricated stacking layers, confirmed physical oxide thickness around 12.08–13.35 nm, and validated the amorphous structure. Meanwhile, XPS confirmed the presence of more stoichiometric dielectric oxide formation for oxidized/nitrided O₂:N₂-incorporated samples, and more sub-stochiometric thin films for samples only oxidized in ambient O₂. The oxidation/nitridation processes with N₂ incorporation influenced the band offsets and revealed conduction band offsets (CBOs) ranging from 2.24 to 2.79 eV. The affected charge movement and influenced electrical performance where optimized samples with gas concentration ratio of 90% O₂:10% N₂ achieved the highest electrical breakdown field of 10.1 MV cm⁻¹ at a leakage current density of 10⁻⁶ A cm⁻². This gate stack also improved key parameters such as the effective dielectric constant ($k_{eff}$) up to 29.75, effective oxide charge ($Q_{eff}$), average interface trap density ($D_{it}$), and slow trap density (STD). The bilayer gate stack of Sm₂O₃ and ZrO₂ revealed potential attractive characteristics as a candidate for high-k gate dielectric applications in metal-oxide-semiconductor (MOS)-based devices.

1. Introduction

The growing worldwide energy crisis necessitates the development of silicon carbide (SiC)-based metal oxide semiconductor (MOS) devices for improving performance of high-frequency electronic systems, particularly in harsh operating environments. SiC has been considered as an excellent alternative to silicon due to its wide bandgap ~3.26 eV, good ohmic contact, high critical breakdown electric field ~3 MV/cm, high saturation electron drift velocity of ~2 × 10⁷ cm/s, and high thermal conductivity of ~3.7 W/cm °C [1]. Its wide bandgap (WBG) capability enables the development of MOS devices that support high voltages and frequencies, addressing scaling limitations. Although early adoption of SiC-based MOS devices benefited from thermally grown silicon oxide (SiO₂) passivation layers, the low dielectric constant (k = 3.9) of SiO₂ has restricted their full potential. Furthermore, reducing SiO₂ thickness below 1.5 nm initiates electron tunnelling that subsequently increases the leakage current [2,3]. This has sparked interest in high-k materials, which provide a physically thicker oxide layer while offering a k-value than SiO₂. The concept is providing a thicker oxide layer while maintaining equivalent oxide thickness, (EOT) proposing analogous effective capacitance [2,4]. Accordingly, integration of high-k materials as gate dielectrics is essential to optimize the effectiveness of WBG SiC devices. It has been well documented that high-k materials must follow the recommended specifications to ensure robust gate dielectric performance. These include reducing the EOT (<1 nm), and a gate leakage current density $J_g$ less than 10⁻² A cm⁻² at a gate voltage $V_g$ ~1 V, and achieving conduction and valence band offsets (CBO and VBO) greater than 1 eV. Additionally, the material should have an interface trap density $D_{it}$ of 10¹¹ cm⁻² eV⁻¹ cm⁻², and possess a high electrical breakdown field ($E_{BD}$). The material must also remain thermodynamically and kinetically stabile under operational conditions [5,6].

Several transitional metal oxides are high-k materials, including Al₂O₃ [7], HfO₂ [8], ZrO₂ [9], and have been explored on the wide bandgap substrate of 4H-SiC. These materials have evidenced promising properties in terms of electrical performance and thermodynamic ability for MOS devices. However, each of them has their own limitations as complete MOS device in counter to SiO₂/Si. Among them, transitional metal oxide (TMO) ZrO₂ is commonly used as a gate dielectric because of its $k$-value of 22 to 25, good interface oxidation with Si substrate, and a bandgap energy between 5.8 and 7.8 eV. It stabilizes easily in cubic or tetragonal phases, enhancing the high-k value and thermal stability at high temperatures [9,10]. ZrO₂ can also be deposited by various methods such as PVD, ALD, and chemical vapor deposition, positioning it as a commonly chosen high-k dielectric [11]. However, ALD-grown ZrO₂ on SiC have drastically led to low VBO (0.52 eV), which enhance hole tunnelling, eventually exposing huge leakage. It has been pointed out that ZrO₂ could not stand alone, which require additional stacking layers [9,12]. Król, et al. [13] reported utilizing ALD-driven ZrO₂/SiC, improving $D_{it}$ up to 10¹¹ eV⁻¹ cm⁻² with the $k$-value of 16.1, with a lower $J_g$ of 10⁻⁶ A cm⁻² at $E_{BD}$ ~7.5 MV cm⁻¹. Kurniawan, et al. [14] reported that ZrO₂ on a SiC gate stack deposited by sputtering achieved a higher $k$-value in the range of 20–80, enhancing the gate leakage $J_g$ up to 10⁻⁸ A cm⁻². For ZrO₂/SiC, the CBO is reported in the range of 1.82–2.3, and the VBO is as low as 0.5–1 eV, making ZrO₂ less suitable as an independent dielectric for 4H-SiC MOS applications [9,12].

Rare earth oxides (REOs) are another potential high-k group that has garnered awareness due to the chemical or thermodynamic stability with Si substrates. This stability is crucial in microelectronics, as it prevents the formation of undesirable silicide during deposition. Various REOs such as Y₂O₃ [15], La₂O₃ [16], Tm₂O₃ [4], and Ho₂O₃ [17] have been employed on SiC for MOS scaling. Although REOs are effective in improving gate leakage and pertaining thermal stability of MOS structure [2,15], they are challenged by hygroscopic moisture effects that can lead to lower-k hydroxides [18,19], causing degradation of dielectric values, increasing thickness and impacting MOS scaling limits. Among REOs, samarium oxide (Sm₂O₃) has a wide bandgap (4.33 eV), high-k (7 to 15), high breakdown electric field (~5 to 7 MV cm⁻¹), a high degree of stability at elevated temperatures, and possesses low leakage current and a large conduction band offset with Si [20]. Pan and Huang [21] studied a direct deposition of a metal oxide layer of Sm₂O₃ on Si utilizing magnetron sputtering, which has shown good thermal stability with Si by producing interfacial silicate while improving electrical performance with a lower leakage of 10⁻⁷ A cm⁻² at 1 V, as indicated in the literature. In our previous studies, Sm₂O₃/Ge gate stack through oxidation/nitridation and magnetron sputtering has provided enhanced E_BD ~13.31 MV cm⁻¹ at 10⁻⁶ A cm⁻² and evidenced as a potential contender to be served as a gate dielectric for MOS-based devices [22]. However, despite these promising properties, the consideration of samarium’s sustainability and natural abundance is essential, as its status as a rare earth element may impact the scalability and long-term viability of Sm₂O₃ in future gate oxide applications.

Interestingly, dielectrics-based multicomponent gate stacks have been the subject of interest to improve MOS gate stack properties, such as in enhancing CBO, interface quality, k-values, leakage current density, and thermal stability [16,23,24]. Furthermore, using REOs such La₂O₃ with ZrO₂ in a bilayer gate stack also supports chemical stability and thermal stability with SiC. The ZrO₂/La₂O₃ bilayer configuration has demonstrated a combined $k$-value reaching 32 after inserting a 2 nm ZrO₂ layer, with a $D_{it}$ $~$10¹² cm⁻² eV⁻¹ and an EOT under 1 nm range [25]. The improvement of the gate stack is attributed to the high-k value of ZrO₂ and intermixing of monoclinic and tetragonal phases. Moreover, the gate stack effectively reduced gate leakage current of $J_g ~$3.5 $\times$ 10⁻⁴ A cm⁻² due to an increased CBO of 2.43 eV [23]. Another study has shown that a bilayer stack of ZrO₂/La₂O₃ [16] can reach a $k$-value increased up to 8.16 by the ZrO₂ layer, achieving low $D_{it}$ $~$10¹¹ cm⁻² eV⁻¹ and an EOT below 1 nm. This improvement is attributed to the orthogonal phase of ZrO₂. The use of rare earth oxides like La₂O₃ with ZrO₂ in bilayer gate stacks has been emphasized for its role in maintaining chemical stability. Therefore, the combination of both Sm₂O₃ and ZrO₂ on a SiC substrate can be utilized to take advantage of the high bandgap energy and dielectric constant of ZrO₂ to improve the electrical properties. Meanwhile, Sm₂O₃ is expected to maintain the thermodynamic stability of the gate stack. Thus, this combination is desired to improve the breakdown electric field and reduce leakage current density in MOS devices, enabling high-power and high-temperature applications.

Nitridation has been employed widely on high-k based devices due to its passivating characteristic for minimizing interfacial defects thorough incorporating nitrogen atoms at the interface. These incorporated N atoms annihilate the oxygen vacancies and reduce carbon density at the dielectric thin film interface [4,26]. Several thin film fabrication methods are frequently employed for MOS, applications including atomic layer deposition (ALD) [27], PVD (RF magnetron Sputtering) [28], and chemical vapor deposition (CVD) [29]. ALD has an excellent film uniformity, with the downside that it is a slow and expensive method. CVD also handles complex depositions, but requires high temperatures. Therefore, sputtering is the ideal thin film deposition, as it is cheaper and has a faster deposition rate despite it having the potential for target material contamination [2,20]. The use of sputtering combined with subsequent oxidation and nitridation of high-k materials on SiC has been shown to enhance the structural and electrical properties of MOS capacitors. It has been suggested that using this method, the formation of amorphous and more stoichiometric gate oxides can elevate the conduction band offset, subsequently improving the bilayer thin film’s leakage current density [30,31]. Nevertheless, the challenges of oxide defects, interface charge trapping, low breakdown field, and high leakage current must be addressed to develop a reliable, high-powered, high-temperature MOS device as the demand for miniaturization continuously increases. The literature [32,33,34] evidenced that variation of the gas flow concentration ratio between (O:N) plays a significant role in regulating thermal stability during gate oxide deposition employing thermal oxidation/nitridation, eventually influencing device performance (gate leakage current density, electrical breakdown, and capacitance). Thus, this paper aims to explore the structural, chemical, and electrical characteristics of bilayer gate dielectrics on 4H-SiC, namely, Sm₂O₃/ZrO₂/SiC produced by various O₂ and N₂ gas concentrations. Additionally, modulation of band alignment mapping for Sm₂O₃/ZrO₂/SiC bilayer gate dielectrics has also been established.

2. Methodology

This experiment utilized n-type 4H-SiC (0001) substrates with a resistivity of 0.020 Ω cm and thickness of 1 μm. Then, these substrates were divided into 1 cm × 1 cm samples and subjected to Radio Corporation of America (RCA) cleaning methods. The removal of impurities is through dipping in hydrofluoric (HF) for 10 s with a ratio of 1:50 of water. Subsequently, a 3 nm thick layer of Sm and Zr was deposited onto the SiC substrates using radio frequency (RF) magnetron sputtering (model: TF-450 SG Control Engineering Pte Ltd., Singapore). The sputtering conditions were carefully controlled: the RF power was set to 170 W, with a base pressure of 3 × 10⁻² Pa and a working pressure of 1.33 × 10⁻⁴ Pa. The sputtering process was carried out for approximately 90 s at room temperature. After the deposition process, the oxidation process took place in a Carbolite CTF horizontal tube furnace for 15 min, in which a combination ratio of O₂ and N₂ airflows was purged once the furnace temperature reached 500 °C, at a thermal rate of 10 °C/min [35]. The samples were divided into four groups, each subjected to different gas concentration ratios during oxidation, as outlined in

Table 1. Bilayer thin film samples with different gas concentrations.

Sample	Gas Concentration
S1	50% O2:50% N2
S2	70% O2:30% N2
S3	90% O2:10% N2
S4	100% O2

.

After the sample preparation, the characterization of the structural and electrical properties of the bilayer was conducted. Firstly, X-ray diffraction (XRD) was used for structural characterization to determine the crystallinity and phase orientation of the bilayer thin films. This was performed using a Malvern Panalytical Empyrean XRD system with a Cu-$K\alpha$ wavelength of ~0.15406 nm, operating at 40 mA and 40 kV, over a 2$\theta$ range of 10° to 120°.

To analyze the chemical composition of the bilayer thin film, X-ray photoelectron spectroscopy (XPS) was carried out with a Thermo Scientific K-Alpha instrument. The XPS analysis parameters were set with an X-ray beam size of 400 × 400 µm², a take-off angle of 45° relative to the normal to surface, and 150 W output power. The survey scan was conducted with a passing energy of 200 eV and 1 eV/step, as the narrow scan was performed with a passing energy of 100 eV and 0.1 eV/step. The valence band (VB) structure was ascertained from the XPS measurements, using the binding energy (B.E.) data from the survey scan for band alignment structure.

The cross-sectional analysis of the samples was conducted using a high-resolution transmission electron microscope (HRTEM), specifically the TECNAI G2 F20. Prior to HRTEM testing, the samples were prepared with a focused ion beam (FIB), and platinum (Pt) coatings were applied to the surface to protect them from potential damage caused by ion bombardment during the FIB process.

Lastly, the electrical characterization of MOS test structures involved depositing a 100 nm platinum electrode with an area of 300 µm × 300 µm onto the substrate using thermal evaporation at a pressure of 9 × 10⁻⁶ mbar. Additionally, an ohmic back contact was created by sputtering 100 nm of aluminum (Al) onto the bottom surface of the substrate via thermal evaporation. The Keithley 4200 semiconductor characterization system (SCS) analyzer was used to extract the current-voltage (I-V) and capacitance-voltage (C-V) characteristics through a probe connector.

3. Results and Discussion

3.1. XRD Analysis

X-ray diffraction (XRD) is used for phase identification, crystal orientation, and crystallite size. In this study, the diffraction angle is in the range from 10° to 60°. In Figure 1, the peaks for monoclinic ZrO₂ (m-ZrO₂), and monoclinic Sm₂O₃ (m-Sm₂O₃) occur at 31.21°, 44.61°, and 50.18°, respectively, for all the samples (S1–S4). Crystal plane orientations (310), (112), and (114) are observed for m-Sm₂O₃ and m-ZrO₂ for investigated samples. The reference codes from the Inorganic Crystal Structure Database (ICSD) were matched as 98-002-6488 for m-ZrO₂ and 01-076-0601 for Sm₂O₃, indicating the presence of expected phase identification and crystal orientation from the experiment.

The amorphous state in the interface is more favoured in gate dielectrics than the crystalline phase due to short-range atomic order. Therefore, the absence of grain boundaries improves the electrical performance with low leakage current and high electrical breakdown voltage. Conversely, the long-range atomic order in crystalline phase creates grain boundaries that act as charge trapping sites and conduction pathways, resulting in higher leakage current [36]. It is observed that all of the samples revealed broad and blunt peaks, suggesting the formation of an amorphous crystal phase. In order to verify the impact of oxidation and nitridation concentration ratio on the crystallinity, each diffraction peak is illustrated in Figure 2. The higher intensity peaks indicate the more crystalline phase. It is noticeable that S3 sample for (310) and (114) of m-Sm₂O₃ is showing the lowest intensity, indicating a more amorphous phase. However, S4 is the least amorphous among all of the samples. The trend is same for m-ZrO₂ (112) as well, suggesting that S3 has the most amorphous interface after oxidation and nitridation ratio. There is the possibility of interface defects, but its visibility is limited due to very low intensity. Peak broadening has been observed for S1, S2, and S4 samples, indicating the existence of defects and oxygen vacancies in the samples. The crystallite size and lattice strain are factors related to peak broadening in XRD spectra. These factors are vital in clarifying the relationship between nitrogen concentration and defect formation in bilayer thin films.

Equation (1) is known as the Debye–Scherrer equation, used to calculate the crystallite size, extracted from Figure 1 [20];

$$D={\displaystyle \frac{K\lambda }{{\beta }_{D }\cos \theta }}$$

(1)

where $D$ is the crystallite size, $\lambda$ is the wavelength of Cu Kα (0.15406 nm), K is the shape factor (0.9), ${\beta }_D$ is full width of half maximum intensity (FHWM), and $\theta$ is peak position. Since the Scherrer equation provides only a lower limit for crystallite size and does not account for micro-strain, a Williamson-Hall (W-H) analysis was also performed.

Accordingly, Figure 3 displays the crystallite size and micro-strain measured through W-H analysis (Figure 4), data which can be extracted from diffraction peaks of XRD. The advantage of W-H analysis is that consideration of intrinsic strain is prioritized for crystallite size measurement as compared to the Debye–Scherrer formula [37]. The strain-induced and size-induced broadening are deconvoluted by the width peak at a certain 2$\theta$ position, affecting the W-H analysis [38]. The summation of broadening of peak that is affected by both micro-strain and crystallite can be defined as in Equation (2).

$${\beta }_{\tau }={\beta }_D+{\beta }_e$$

(2)

where β_τ is the total broadening, and ${\beta }_D$ and ${\beta }_e$ are peaks width at half maximum intensity of the peak broadening caused by crystallite size and micro-strain, respectively. For deriving the W-H process, the induced micro-strain ($\epsilon$) contributing to peak broadening can be expressed by Equation (3).

$$\mathsf{\epsilon }={\displaystyle \frac{{\beta }_e}{4 tan\theta }}$$

(3)

Replacing and rearranging Equations (1) and (3) into Equation (2) stipulates the W-H Equation (4)

$${\beta }_{\tau }cos\theta ={\displaystyle \frac{k\lambda }{D}}+4\epsilon sin\theta$$

(4)

A graph of ${\beta }_{\tau }cos \theta$ versus $4sin\theta$ was plotted based on Equation (4) as per Figure 4. The best linear regression fit (r² = 1) is aimed within the distribution of the plot. The contribution of micro-strain, $\epsilon$, and crystallite size $D$ on Sm₂O₃ peaks with plane orientation (310) and (114) broadening was calculated from the gradient of the graph; ${\displaystyle \frac{k\lambda }{D}}$ is the y-intercept and $D$ can be calculated from this relationship. The W-H plot does not include the m-ZrO₂ peak due to an inadequate visible peak in this surface.

The durability of thin films is governed by a complex interaction between defects and grain boundary effects, which contribute to both leakage current and the reliability of the insulator. The role of crystallite size and micro-strain is significant in providing insight into grain boundaries, pinhole-free films, and its compactness in terms of leakage current [39]. The largest crystallite size is found in S3 (74.15 nm), and the smallest crystallite size is found in S4 (64.19 nm), as indicated in Figure 3. Considering the nitrided samples, the trend of crystallite size increases from S1 to S3 as the N₂ content decreases. The largest crystal of S3 can be attributed to the reduced diffusions of unbounded N₂ or O₂ atoms causing gradual and relatively controlled growth of dielectric oxides. Therefore, the peak broadening decreases and peak intensity is reduced, as per Figure 1. Thin films with smaller crystallite sizes, such as S4, are associated with more grain boundaries, resulting in more structural disorders and pinholes. Defect states such as dangling bonds, vacancies, and interstitials often accumulate in these grain boundary regions, potentially forming conduction pathways for leakage current. However, the larger crystallite size observed in S3 reduces grain boundaries, minimizing defect sites and enhancing leakage current pathways [40]. Accordingly, S3 reduced overall peak intensity, revealing more amorphous-like behavior along with the largest crystallite size (74.15 nm) observed for this sample. This apparent discrepancy could also be attributed to the presence of fewer but larger crystalline domains embedded within an amorphous structure at low peak intensity. The reduction of peak intensity could be attributed to the total number of crystalline regions contributing to diffraction being low and existing in a well-formed and large crystallite, leading to narrower peak widths. Consequently, S3 might contain a combination of large crystallites embedded in a more disordered or amorphous matrix.

Micro-strains can induce lattice mismatch, dislocation, and imperfection. The consequence is that the defects will distort the periodicity of the crystal lattice and lead to broadening in the X-ray diffraction pattern [41]. All of the micro-strain appeared to be positive, suggesting tensile strain was exerted within lattice site. The smallest micro-strain is in the S3 sample, with 0.00064. The lower concentration of N₂ gas in the S3 sample indicates a more cohesive oxide interface with fewer lattice dislocations and distortions. The highest micro-strain is in the S4 sample, with 0.00088. This value highlights a tendency in drawing additional O atoms to diffuse towards the substrate and forming vacancies and interstitials. The lattice structure distortion due to this strain may lead to increased leakage current [42]. Furthermore, high micro-strain may introduce intensified stress on grain boundaries, raising defect densities and disrupting grain uniformity within the dielectric film. Consequently, the large number of lattice defects could lead to electrical breakdown from interface dielectric loss, when the localized electric fields of defect densities could surpass the dielectric strength of the thin film due to excessive charge accumulation onto the defect sites projected to initiate a premature breakdown as in S4. Thus, the low micro-strain in S3 is beneficial for relaxing grain boundaries to reduce defect concentrations, improving the material’s ability to withstand electrical breakdown [17,43,44]. In summary, the S3 sample with the largest crystallite size and lowest micro-strain is predicted to improve J-E properties due to a reduction in grain boundaries and more uniform, compact lattice structure.

3.2. XPS Analysis

The bonding elements in the thin films were identified via X-ray photoelectron spectroscopy (XPS), with the Gaussian–Lorentzian function method applied for curve deconvolution. The survey scan confirmed the detection of Si 2p, Ho 4d, Zr 3d, C 1s, N 1s, and O 1s.

The peaks of XPS O1s spectra are shown in Figure 5a for S1 to S4 samples. The Sm–O/Zr–O bond can be found at 530.25 eV, 530.43 eV, 530.56 eV, and 529.89 eV for S1 to S4 samples, respectively. The nitrided S1–S3 samples have higher integrated areas, indicating less O out-diffusion from the dielectric oxide itself. On the contrary, for the oxidized S4 sample, the Sm–O/Zr–O peak shifted to the lowest binding energy (B.E.) and depleted the integrated area as well, indicating bonds weakening and more out-diffusion O atoms from the dielectric interface itself. The depletion may result from the absence of nitrogen, which accelerated the oxidation of Sm–O/Zr–O interface, causing O atoms out-diffusion leaving oxygen vacancies at the dielectric interface and reduced thermal stability. On the contrary, the nitrided samples S1–S3 have higher integrated areas, indicating less O out-diffusion from the dielectric oxide itself. Meanwhile, the S3 sample exhibits the largest integrated area, with higher B.E. for Sm–O/Zr–O contents, which could be attributed to more controlled supply of O₂:N₂ allowing sufficient oxygen to regulate full oxidation of Sm and Zr. The reduction of nitrogen content at this phase minimizes nitridation-related defects, as well thereby enhancing the formation of more stoichiometric Sm–O/Zr–O bonds. Among the nitrided samples, the S1 sample shifted negatively toward lower B.E. Sm–O/Zr–O, suggesting a sub-stoichiometric oxide composition. The low B.E. and reduction of O contents in the Sm–O/Zr–O can be attributed to an excessive flow of N₂, which partially impedes oxygen diffusion pathways, subsequently weakening the ideal dielectric oxide bond formation.

The B.E. of silicate (Sm–O–Si/Zr–O–Si) bonds were assigned at 532.43 eV, 532.63 eV, 532.72 eV, and 532.03 eV [45] for S1, S2, S3, and S4 samples, respectively. It is observed that the integrated area of silicate increased gradually with the increase of O flow concentration and reduction of N concentration. The formation of silicate indicates SiC substrate tends to oxidize while forming Si–O bonds, which diffused into Sm–O/Zr–O growing (Sm–O–Si/Zr–O–Si) bonds. This silicate formation helps to improve the dielectric constant of the oxide, as well as improve the device properties due to restraining the growth of low-k SiO₂. However, the contribution largely depends on the quality of silicate. Regarding stoichiometry, it is conspicuous that S2 and S3 lean toward higher B.E., suggesting more stoichiometric silicate formation with more regulated proportional distribution of O contents within the silicate network. Among the nitrided samples, S3 induced the largest integrated area along with higher B.E., suggesting more stoichiometric silicate formation due to frequent reactions of SiC and oxygen interstitial at the Sm–O/Zr–O interface. The balanced N incorporation maintained the integrity of O contents in both Sm–O/Zr–O and silicate by controlling oxygen vacancy blockage diffusivity [46], reducing O-related defects within dielectric oxides and forming more stable silicate network. However, both S1 and S4 shifted toward lower B.E., suggesting less stoichiometric, O-deficient Si-rich silicate. Meanwhile, for nitrided S1 sample, a substantial reduction of O content in the flow rate ratio resulted in partial oxidation of SiC, tending to reduce silicate with less O proportion. For S4 surplus of O atoms aggressively oxidized, SiC initiated severe intermixing of Si–O and Sm–O/Zr–O, causing densification of silicate while causing imbalance in O content proportional distribution. Accordingly, both S1 and S4 shifted toward lower B.E., suggesting less stoichiometric O-deficient less stable Si-rich silicate.

Figure 5b indicates the changes of Zr 3d spectra across S1 to S4 samples in the range of 180 to 190 eV. The spin-orbit split of 3d_5/2 and 3d_3/2 is confirmed [47]. The chemical shift between two peaks such as 182.89 and 185.29 assigned to Zr–O contents, the S3 sample with a 2.4 eV difference, indicates full oxidation [48]. Meanwhile, Figure 5c shows the Sm 3d spectra where two peaks exist within the range from 1084.5 to 1113.1 eV. These peaks correspond to two spin-orbit splits with Sm 3d_5/2 and Sm 3d_3/2 (e.g., 1084.57 eV for Sm 3d_5/2 and 1111.68 eV for Sm 3d_3/2), confirming the trivalent oxidation state of Sm–O. Both Sm 3d and Zr 3d follows an analogous trend where the integrated peak area increases monotonically from S1 to S3 and decreased for S1. Additionally, in both spectrums, S2 and S3 shifted toward higher B.E., suggests fewer oxygen vacancies, leading to stronger Zr–O and Sm–O bonds. Meanwhile, S1 and S4 induced defective Zr–O and Sm–O bonds, consisting of a higher level of oxygen vacancies. The O1s spectra aligns well with the observation of Sm 3d and Zr 3d spectra.

In summary, based on XPS analysis for all O1s, Zr 3d, and Zr 3d, confirming the formation of Sm–O/Zr–O, and Zr–O–Si/Sm–O–Si, the nitrided S3 sample condition revealed an optimum B.E. shift, reflecting higher quality with fewer defects of the thin film interface formation during oxidation/nitridation. The chemical shift and integrated area proportion observed in the S4 condition is prone to the formation of O vacancies, which leads to weaker bonds with more defective dielectric interfaces. Thus, the formation of less sub-stoichiometric and stable dielectric oxides and silicates provides effective energy barriers, minimizing charge trapping sites and increasing resistance to electron tunnelling [49], which helps reduce gate leakage currents. The critical role of the oxygen-to-nitrogen (O:N) ratio in improving dielectric quality and device performance is further demonstrated in Section 3.7.

3.3. Band Alignment

The band alignment of the bilayer thin film is shown in Figure 6, where valence band offset (VBO) can be measured from the valence band spectrum and conduction band offset (CBO) from Equation (5). The minimum requirement of 1 eV is needed for CBO and VBO to meet MOS scaling requirement to avoids excessive leakage current of charge carrier [50,51]. Therefore, measuring the CBO and VBO is essential for investigating charge transport and device performance in bilayer thin films. Band alignment has been evaluated using XPS O1s plasmons and valence band spectra. The CBO is derived by using Equation (5)

$$\Delta {\mathrm{E}}_{\mathrm{c}(\mathrm{Z}\mathrm{r}{\mathrm{O}}_2/{\mathrm{S}\mathrm{m}}_2{\mathrm{O}}_3)}={\mathrm{E}}_{\mathrm{g}(\mathrm{Z}\mathrm{r}{\mathrm{O}}_2/{\mathrm{S}\mathrm{m}}_2{\mathrm{O}}_3)}-{\mathrm{E}}_{\mathrm{g}\left(\mathrm{S}\mathrm{i}\mathrm{C}\right)}-{\Delta \mathrm{E}}_{\mathrm{v}(\mathrm{Z}\mathrm{r}{\mathrm{O}}_2/{\mathrm{S}\mathrm{m}}_2{\mathrm{O}}_3/\mathrm{S}\mathrm{i}\mathrm{C})}$$

(5)

Figure 6b illustrates energy bandgaps, $E_g$, which were obtained from O1s plasmon loss XPS survey spectra, while valence band offset (VBO) $\Delta E_v$ were determined by using the valance band spectrum. The overall band alignment is represented in Figure 7.

The value of $\Delta E_v$ from S1 to S4 samples is as follows; 2.24 eV, 2.35 eV, 2.42 eV, and 2.6 eV, respectively. The value of $E_g$ is 3.26 for a SiC substrate [50]. The value of $E_{g(Zr{O}_2/{Sm}_2{O}_3)}$ from S1 to S4 samples is as follows; 8 eV, 8.3 eV, 8.47 eV, and 8.1 eV, respectively. Hence, $\Delta E_c$ on SiC substrate, based on Equation (5), is 2.5 eV, 2.69 eV, 2.79 eV, and 2.24 eV. The insight on the band alignment structure is essential for analyzing charge transport at the high-k/semiconductor interface, where $\Delta E_c$ and $\Delta E_v$ directly influence the energy barrier that electron and hole carriers must overcome or tunnel through at the band edges of the dielectric and substrate. Thus, higher values for CBO and VBO contribute to higher breakdown voltages and lower leakage currents. For n-type semiconductors, electrons as the majority carriers make CBO govern the energy barrier for electron transport [6,52,53]. Figure 8 shows that the highest $\Delta E_c$ is in S3 sample at 2.79 eV, with low N₂ concentration that reduce electron tunnelling across the barrier height. The large CBO in S3 and S2 samples could stem from fewer electron defect states within the microstructure [23]. The increase in bandgap (as in S3) is attributed to the formation of stoichiometric configurations and the combined effect of stabilized Sm₂O₃ and ZrO₂ bilayer thin films, as indicated by XPS. Therefore, a higher CBO (as in S3) creates a large energy barrier, slowing down the electron transport from the SiC conduction band to the Sm₂O₃/ZrO₂ interface. Accordingly, the probability of the charge transport or thermionic emission is decreased, which enhances the insulation and reliability (higher breakdown voltage) of the Sm₂O₃/ZrO₂/SiC system. However, a very high CBO can prevent charge accumulation under bias, negatively influencing capacitance response [53,54]. In contrast, a reduced $\Delta E_c$ for equal O₂:N₂ (S1) and (S4) without N₂ may facilitate electron movement from the substrate conduction band to the Sm₂O₃/ZrO₂ dielectric. According to XPS analysis, these conditions promote the formation of non-stoichiometric silicate (Sm–O–Si/Zr–O–Si), introducing defects and oxygen vacancies, as well as dissociation of Sm₂O₃ and ZrO₂. Consequently, defect states appear within the bandgap, reducing band offsets and increasing tunnelling into dielectric layer. This degrades the leakage current and breakdown voltage. Furthermore, lower band offsets can also increase charge accumulation at the semiconductor–dielectric interface, improving capacitance. However, achieving high capacitance in high-k MOS thin films is challenging due to its dependence on permittivity and oxide thickness [6]. The VBO plays an essential role in restricting hole transport, which preserves dielectric integrity. A higher $\Delta E_v$ in S2 to S4 samples imposes a robust barrier against holes movement, reducing unnecessary and excessive hole injection. This facilitates n-type device operation by promoting electron conduction. The low $\Delta E_v$ in S1 allows hole injection, potentially increasing gate leakage and creating interface states, leading to degradation of performance. Each sample in this study demonstrated $\Delta E_c$ and $\Delta E_v$ above 1 eV, aligning with the MOS scaling requirements. Thus, balancing $\Delta E_c$ and $\Delta E_v$ is necessary for MOS device reliability.

3.4. HRTEM Analysis

The cross-sectional HRTEM images can be observed in Figure 8 where the bilayer Sm₂O₃ and ZrO₂ thin films on 4H-SiC substrate oxidized at gas concentration ratios of 50% O₂:50% N₂ (S1) and 90% O₂:10% N₂ (S3), respectively. Figure 8a presents cross-sectional HRTEM images of the bilayer structures for S1 and S3, showing the overall morphology and interface quality under different gas concentrations. The enlarged views in Figure 8b provide insight into the atomic-scale structure, highlighting variations in interatomic spacing, crystal defects, and lattice ordering. These differences suggest that the gas concentration significantly influences the crystallinity and structural integrity of the dielectric layers, with potential implications for their electrical characteristics. The physical thicknesses of ZrO₂ and Sm₂O₃ were quantified, and their electrical characteristics will be further expanded. The total thickness at S1 is 13.35 nm, and S3 is 12.5 nm. Both of these points will be extrapolated into Figure 9 for approximation thickness of S2 (12.93 nm) and S4 (12.08 nm). Two layered dielectric thin film oxides have been detected in each gas concentration, consisting of Sm₂O₃/ZrO₂ and silicate (Sm–O–Si/Zr–O–Si), as confirmed in XPS and XRD analyses. The darker layer is identified as Sm₂O₃ due to its atomic weight of 67, which is higher than ZrO₂ atomic weight of 40. This higher atomic number means that Sm₂O₃ will scatter electrons more strongly, appearing darker in TEM imaging, while ZrO₂ will scatter fewer, appearing lighter.

Figure 8. (a) Bilayer ZrO₂/Sm₂O₃/4H-SiC with gas concentration variation for S1 and S3 cross-sectional HRTEM images. (b) The average interatomic distance, crystal defects, and crystallinity in enlarged images for S1 and S3.

Figure 8. (a) Bilayer ZrO₂/Sm₂O₃/4H-SiC with gas concentration variation for S1 and S3 cross-sectional HRTEM images. (b) The average interatomic distance, crystal defects, and crystallinity in enlarged images for S1 and S3.

Figure 9. The trend of $t_{ox}$ for bilayer ZrO₂/Sm₂O₃ for each O₂:N₂ concentration ratio.

Figure 9. The trend of $t_{ox}$ for bilayer ZrO₂/Sm₂O₃ for each O₂:N₂ concentration ratio.

The Fast Fourier Transform (FFT) using ImageJ software (v1.54p) is used to inspect the crystallinity structure based on previous images. By transforming HRTEM images into the frequency domain, FFT facilitates the identification of periodic structures and measurement of interplanar spacings, providing insights into the material’s crystalline properties [55]. The inset images allow for observing cloudy spots that show the amorphous state. Multiple FFT pattern locations are polycrystalline in nature, indicating the SiC substrate. The average interatomic spacing for both dielectric layers are 0.25 nm and 0.17 nm for S1 and S3 samples, respectively. The smaller interatomic spacing in S3 reflects a denser atomic structure, thus reducing voids and defect sites. This denser arrangement, combined with fewer grain boundaries and larger crystallite size in S3, helps reduce defect trapping sites, improving gate leakage current. In contrast, S1’s larger interatomic spacing suggests that excessive nitrogen weakened its atomic structure, as evidenced by higher micro-strain from XRD. Furthermore, S1 displayed smaller crystallite sizes than S3, as illustrated in Figure 8b, which is in agreement with the crystallite size observed in XRD. The smaller crystallite size can be attributed to the densely packed grain boundaries and nitrogen-induced defect, which would lead to gate leakage degradation. As shown in Figure 8b, S3 exhibits larger crystallite sizes compared to S1, consistent with the XRD results. This difference is likely due to reduced atomic diffusion and a more uniform microstructure in S3. In contrast, the S1 sample, processed under an imbalanced O₂/N₂ ratio, exhibited smaller crystallite sizes, possibly due to limited grain growth and the presence of finer grain boundaries.

3.5. C-V Characteristics

The C-V characteristics with bias voltage applied from −3 V to 3 V at 100 kHz shows the highest capacitance at accumulation occurs in S3, as presented in Figure 10. The C-V characteristics can be elaborated from Equation (6) [49]:

$$\mathrm{C}={\displaystyle \frac{\mathrm{k}{\mathsf{ϵ}}_{ox}A}{{\mathrm{t}}_{\mathrm{o}\mathrm{x}}}}$$

(6)

The permittivity of free space ${\epsilon }_{ox}$ (8.85 × 10⁻¹² Fm⁻¹) and area of the capacitor $A$ are the constant parameters for capacitance; $C_{ox}$ is the capacitance of gate dielectric, $t_{ox}$ is the total physical oxide thickness, and permittivity of the oxide ${\epsilon }_{ox}$ are constants.

The $C_{total}$ calculation is by adding both layers as per Equation (7) between oxide layer and substrate, as indicated in Section 3.5.

$${\displaystyle \frac{1}{C_{total}}}={\displaystyle \frac{1}{C_{{Ho}_2{O}_3}}}+{\displaystyle \frac{1}{C_{Zr{O}_2}}}$$

(7)

where $C_{{Sm}_2{O}_3}$ and $C_{Zr{O}_2}$ are each layer’s capacitance and are defined in Equation (7). The area of the capacitor $A$ and Equation (6) can be simplified into $k/t_{ox}$. The $t_{ox}$ is extracted from HRTEM results.

The capacitance at accumulation level from samples S1 to S4 is as follows: 2.08 µF cm⁻², 2.2 µF cm⁻², 2.38 µF cm⁻², and 1.98 µF cm⁻², respectively. The S3 sample has the highest $C_{ox}$ at accumulation due to reduced $t_{ox}$. On the contrary, S4 sample has low accumulation capacitance despite having a reduced $t_{ox}$, which can be related with defects at the interface and dielectric properties. The increment of $C_{ox}$ can be linked to the higher k value, as shown in the inset image of Figure 10.

The dielectric constant $k_{eff}$ is 27.77, 28.44, 29.75, and 23.9 for S1 to S4, respectively, as shown in the inset of Figure 10. The high $k_{eff}$ in S3 formation is attributed to the higher stoichiometric and densification of Sm–O/Zr–O content, confirmed by XPS in Section 3.2. A relaxed grain boundary with reduced micro-strain detected in this sample, as evidenced by XRD in Section 3.1, indicates a uniform crystal lattice with fewer interface defects that leads to a higher k-value. Furthermore, the uniformed structure strengthens the local dipole moment, enhancing the ability of dielectric material to be polarized efficiently, and subsequently contributes to increased $C_{ox}$. As for S4, without nitrogen the reduction of $k_{eff}$ could be due to densification of non-stoichiometric dielectric oxides and silicates. Due to lack of oxygen vacancy passivation effect of N content, a higher degree of structural disorder appeared in the Sm–O/Zr–O and Sm–O–Si/Zr–O–Si network, weakening the local dipole moment at the interface, ultimately limiting the dielectric’s polarization to respond to the electric field, leading to a decrease in $C_{ox}$.

Based on the literature, high k-values are attainable with single-layer oxides, such as the 18–19 range for Sm₂O₃ on Si [19]. In contrast, ZrO₂ on Si at different oxidation/nitridation levels shows a k-value of 21.82 [3]. The highest k-value reaches 29.75 (S3) in the bilayer thin film of Sm₂O₃/ZrO₂/SiC, showing a potential high-k alternative.

Figure 11 reveals that the flat band voltage $V_{fb}$ has a positive shift, as the depletion region appeared in the positive region for all concentration ratios. The positive $V_{fb}$ affects the negative accumulation of fixed oxide charge $Q_{eff}$, exhibited in Figure 11. The $Q_{eff}$ is calculated as follows:

$$Q_{eff}={\displaystyle \frac{\left({∆\mathrm{V}}_{\mathrm{f}\mathrm{b}}\right)C_{ox}}{qA}}$$

(8)

where $∆V_{fb}$ is the difference between $V_{fb}$ (ideal) and $V_{fb}$ (experimental), and q is the electronic charge. The highest $Q_{eff}$ is obtained in S4 sample with −5.56 × 10¹² cm⁻², meanwhile the $Q_{eff}$ in S3 sample reached the lowest at −20.8 × 10¹² cm⁻², as shown in Figure 11. The presence of a fixed oxide charge could be attributed to acceptor-type traps such as singly or doubly negatively charged oxygen vacancies ($V_0^{-}$ $V_0^{2-}$) and/or oxygen interstitials ($O^{-}$, $O^{2-}$) within Sm–O/Zr–O lattice sites [52]. Accordingly, reduction of negative fixed oxide charges confirms minimization of oxygen vacancies/oxygen interstitials, which were stabilized by generation of stable silicate content, and contributes to more uniform charge distribution. The observation also suggests that the fixed oxide charge distribution is more pronounced for the samples with absence of N atoms or excessive N in-diffusion. This can be verified with XPS measurements where Sm–O/Zr–O density is shifted lower B.E. for S1 and S4, degrading interface quality and increased oxygen vacancies [56].

From the C-V curve, the hysteresis effect can be observed from the forward and reverse bias applied on the bilayer thin film. The electron trap and release mechanism at the near interface is affected by the hysteresis effect (Figure 12), which could lead to a broader hysteresis loop. The process of charge trapping and release is related to the slow trap density (STD). Equation (9) for STD calculation has been estimated by:

$$STD={\displaystyle \frac{(∆V)C_{ox}}{qA}}$$

(9)

where ΔV is the flat band voltage difference between the hysteresis curve, $A$ is the capacitor area, and $q$ is the electronic charge. The lowest STD is identified in S3 sample with 1.49 × 10¹² cm⁻² and the highest STD generated in S4 sample with 6.78 × 10¹² cm⁻², as exhibited in Figure 11. The physical source of STD has been attributed to the structural defects at high-k/semiconductor interface, permitting the movement of charged carriers, such as electrons or holes, from the substrate into the oxide interface [26]. The lowest STD phenomenon occurred in S3 evidence reduction of slow traps by filling deep-level states through effective passivation N atoms, limiting the capture of majority carriers (electrons in n-type SiC). Despite a higher level of N₂ incorporation for S1 and S2, the rise in STD infers that piling of N atoms into the dielectrics, sited between the Sm₂O₃ and ZrO₂ interface, promoted carrier trap sites. In contrast, the S4 sample amplified the oxygen vacancies, enhancing electron transportation lacking N₂. Thus, increment of STDs extends slow charged sites altering polarization dynamics and effective electric field under bias condition. Accordingly, the dipole polarization reorients but does not de-trap immediately, reverting slower under bias, causing a lag in the device’s response, leading to wider hysteresis as in S4. Furthermore, a large bump in the depletion in S1 indicates that a higher degree of nitrogen-related defect occurs with substantial N₂ integration [46]. All samples revealed a stretched out C-V curve, suggesting a large amount of interface traps are present.

Figure 13 demonstrates the average trap density $D_{it}$ as a function of surface potential ${\phi }_s$ or trap energy level ($E_c$-E) for oxidation and nitridation concentration ratio of bilayer thin films. The Terman method is used to determine the value [57] from the C-V curve, as shown in Equation (10) below:

$$D_{it}={\displaystyle \frac{(∆V_g)C_{ox}}{{\phi }_{s}qA}}$$

(10)

where ${\phi }_s$ represents the surface potential of SiC at a specified gate voltage, $V_g$, and ${∆V}_g$ is the difference between the ideal gate voltage and experimental gate voltage. The highest $D_{it}$ is in S4 sample in the range of 16.4 to 37.4 × 10¹⁴ eV⁻¹ cm⁻² at [$E_c$-$E$] at 0.09 to 0.27 eV. The $D_{it}$ with magnitude of 10¹⁴ eV⁻¹ cm⁻² suggests a substantial number of electronic traps at the semiconductor and gate dielectric interface that can capture or release electrons and holes, increasing electronic state density and impacting electrical characteristics. In this study, the significant $D_{it}$ levels are likely due to oxidation processes that leave a defective Zr–O/Sm–O/SiC interface, generating silicates, oxygen vacancies, and defects related to oxygen and nitrogen diffusion [16,46]. The lowest $D_{it}$ in S3 is attributed to the optimal passivation of N atoms, which reduced overall structural defects related to oxygen vacancies and dangling bonds in dielectric layers, resulting in reduced average interface traps. In S4, the high $D_{it}$ from oxygen vacancies or the diffusion of oxygen at the Sm–O/Zr–O interface formed localized energy states within the gate dielectric and SiC substrate.

3.6. J-E Characteristics

Figure 14 shows the changes of leakage current density J as the electric field E applied for S1 to S4 samples. The electric field, E, is calculated by following Equation (11) [22]:

$$\mathrm{E}={\displaystyle \frac{{\mathrm{V}}_{\mathrm{g}}-{\mathrm{V}}_{\mathrm{f}\mathrm{b}}}{{\mathrm{t}}_{\mathrm{o}\mathrm{x}}}}$$

(11)

where $V_g$ is the gate voltage, $V_{fb}$ is the flat band voltage, and $t_{ox}$ is the total physical oxide thickness. The dielectric breakdown field is classified into two types: hard breakdown $E_H$, which occurs at a large increment in leakage current density under high electric field, and soft breakdown $E_s$, which occurs at a low electric field with a smaller increase in leakage current density. The electrical soft breakdown, $E_s$, is 2.4 MV cm⁻¹, 5.03 MV cm⁻¹, 3.46 MV cm⁻¹, and 1.06 MV cm⁻¹ for S1 to S4 samples, respectively. The leakage current density at $E_s$, is 10⁻⁴, 10⁻⁵, 10⁻⁹, and 10⁻⁶ for S1 to S4 samples, respectively. S3 sample exhibits the highest electrical hard breakdown field $E_H$ at 10.1 MV cm⁻¹, indicating the best electrical performance. Leakage current variations are influenced by factors such as dislocation density and the crystallite size of the dielectric material [2]. XRD analysis in Section 3.1 demonstrated that this sample had the smallest micro-strain and the largest crystallite size. The reduction in micro-strain allowed for a more uniform interface with fewer grain boundary defects, thus lowering localized electric fields at defect sites and enhancing the breakdown field. The larger crystallite size further reduced grain boundaries and charge trap sites, reducing conductive paths. Consequently, S3 shows superior I-V characteristics with an induced field $E_s$ $~$3.46 MV cm⁻¹ and lowest leakage current J $~$10⁻⁹ A cm⁻², suggesting that nitrogen incorporation plays a role in passivating oxygen vacancies or impurities, and affects the overall composition [58]. XRD analysis in Section 3.1 reveals that the S4 (with oxygen) has a smaller crystallite size and higher micro-strain compared to S1–S3 (with N₂ incorporation), resulting in increased grain boundaries and dislocation density within the lattice. These structural defects acted as charge conduction paths, causing higher leakage currents and a reduced breakdown field.

According to Choopun et al. [59], films with a denser oxygen vacancy layer tend to exhibit increased leakage current. In S4, the absence of nitrogen allowed excessive oxygen diffusion, causing oxygen vacancies within Sm–O/Zr–O bonds, as confirmed in XPS (Section 3.2). This led to oxidation of SiC, forming oxygen-deficient sub-stoichiometric silicates, which created additional oxygen vacancies that escalated charge trapping sites, inducing high leakage currents. The J-E behavior is consistent with band alignment findings in Section 3.3, where S3 achieved the highest CBO due to fewer defect states, supporting higher breakdown voltage. The low CBO in S4 is also in good alignment, suggesting that a lower energy barrier is required for electron tunnelling, subsequently hastening electrical breakdown. Overall improved properties due to the incorporation of N₂ samples can be attributed to nitrogen atoms being integrated into the structure, effectively preventing the excessive release of O atoms, reducing oxygen vacancies from the Sm–O/Zr–O interface, thereby maintaining a more stoichiometric oxide [60]. This also suppressed the growth of sub-stoichiometric silicate by limiting excessive oxidation of the SiC substrate. Thus, incorporation of N₂ in S1–S3 limited localized charge trapping sites and improved the J-E characteristics compared to the oxidized S4 sample. However, it is important to realize a balanced N supply, because too little or too much supply could adversely impact the J-E characteristics. As in S1, relatively higher N₂ levels and lower oxygen content caused inadequate oxidation and increased interface nitridation, forming a low-k sub-stoichiometric high-k/SiC structure. Eventually, induced higher levels of charge trapping sites expand conduction pathways, degrading the J-E performance of S1 relative to S2 and S3. The superior J-E performance in S3 supports the XPS findings, where chemical B.E. shifts showed a more stoichiometric high-k/SiC interface. The literature suggests that for reliable MOS gate stacks, $J_g$ should not exceed 10⁻² A cm⁻² and $E_{BD}$ should be in the range of 3 to 4 MV cm⁻¹ for long-term stability [6,49]. In this study, $E_{BD}$ values ranged from 4.67 to 10.1 MV cm⁻¹, and $J_g$ was 10⁻⁹ A cm⁻², suggesting that ZrO₂ + Sm₂O₃ bilayers are a strong candidate for SiC-based MOS applications. The higher $E_{BD}$ achieved in this experiment compared to previous studies (

Table 2. Leakage current density and breakdown field for various gate dielectric stacks.

Configuration	Deposition	J at 1 V (A cm−2)	${\mathit{E}}_{\mathit{B}\mathit{D}}$ (MV cm−1)	Ref.
Ho2O3/SiC	Sputtering	10−6	8.95	[17]
ZrO2/SiC	Sputtering	10−6	5.05	[9]
ZrO2/SiO2/SiC	ALD	~10−10	16	[13]
ZrO2/Ho2O3/SiC	Sputtering	10−11	9.7	[61]
ZrO2/Sm2O3/SiC	Sputtering	10−9	10.1	This work

) are likely due to variations in film thickness and deposition methods.

3.7. Fowler–Nordheim Tunnelling Analysis

The conduction mechanism in this work is Fowler–Nordheim (FN) tunnelling, applied when a high electric field is applied across the gate dielectric. This high electric field reduces the width of the triangular potential barrier, permitting electrons to tunnel into the conduction band of the oxide layer. The FN tunnelling conduction as the electricity applied exceeds 3.5 MV cm⁻¹, according to the literature [62]. FN tunnelling can be expressed in Equations (12)–(14) as follows [20]:

$${\mathrm{J}}_{FN}=\mathrm{A}{\mathrm{E}}^2\exp \left[{\displaystyle \frac{-B}{E}}\right]$$

(12)

$$\mathrm{A}=\left[{\displaystyle \frac{q^3}{8\pi h{\Phi }_B}}\right]\left[{\displaystyle \frac{m}{m_{ox}}}\right]$$

(13)

$$\mathrm{B}={\displaystyle \frac{8\pi {\left(m_{ox}{{\Phi }_B}^3\right)}^{\frac{1}{2}}}{3qh}}$$

(14)

where h is Plank’s constant (4.135 × 10⁻¹⁵ eV s), $m_{ox}$ is effective electron mass, and $m$ is free electron mass. Rearranging Equations (13) and (14) to express A and B as below:

$$\mathrm{A}=1.54 \times {10}^{-6}\left[{\displaystyle \frac{m}{m_{ox}}}\right][{{\Phi }_B]}^{-1}$$

(15)

$$\mathrm{B}=6.83 \times {10}^7\left[{\displaystyle \frac{m_{ox}}{m}}\right]{\left[{{\Phi }_B}^3\right]}^{{\displaystyle \frac{1}{2}}}$$

(16)

Equation (12) can be shortened as

$$\ln \left[{\displaystyle \frac{\mathrm{J}}{{\mathrm{E}}^2}}\right]=-\mathrm{B}\left[{\displaystyle \frac{1}{\mathrm{E}}}\right]+\ln \mathrm{A}$$

(17)

Figure 15 shows the linear plot of FN tunnelling. The barrier height (${\Phi }_B$) can be extracted from this plot where the slope represents B and the intercept represents A.

Figure 16 exhibits that the highest ${\Phi }_B$ is found in the S3 sample with value of 1.73 eV, while the lowest ${\Phi }_B$ is in the S4 sample with 0.76 eV. In S3 sample, there is a low resistance for electron tunnelling into the conduction band from the valence band_. The trend of ${\Phi }_B$ is comparable with CBO extracted from XPS in Section 3.2, where S3 sample demonstrates the highest CBO. In contrast, the low barrier height in the S4 sample suggests a high leakage current density, as the electrons easily tunnel through the metal oxide layers.

4. Conclusions

The bilayer of ZrO₂/Sm₂O₃/SiC thin film underwent oxidation and nitridation using O₂ and N₂, and the effects of the gas concentration ratio were examined in terms of structural and electrical characterization at an oxidation temperature of 500 °C for 15 min. XRD analysis showed the presence of monoclinic ZrO₂ (m-ZrO₂) and monoclinic Sm₂O₃ (m-Sm₂O₃) in all samples. Structural deformation, in terms of crystallite size and micro-strain, is affected by the gas concentration ratio. The S3 sample has the largest crystallite size, indicating fewer grain boundaries or trap sites, which leads to a better conduction band offset (CBO), resulting in reduced leakage current, as observed in J-E analysis. XPS analysis reveals the existence of Zr–O, Sm–O, Zr–O–Si, and Sm–O–Si bonds in all samples. The S3 sample shows the most stoichiometric and thermally stable characteristics. HRTEM results indicate that the physical thickness of the oxide layer ranges from 12.08 to 13.35 nm. Overall, it was observed that the oxidized sample without N₂ incorporation induced a severely defective interface and uniformity of the thin films, leading to degradation of the performance. Meanwhile, S3 sample utilized both oxidation and nitridation effects, where the capacitance is 2.38 µF/cm² with a substantial k-value of ~29.75. The band alignment suggests that the band offset of the S3 sample is $\Delta E_v$ ~2.42 eV and $\Delta E_c$ ~2.79 eV. The hard breakdown electric field for the S3 sample is 10.1 MV cm⁻¹. The incorporation of nitrogen evidenced an improvement to oxygen vacancies and gate stack defect passivation. Therefore, the S3 sample has the most optimum oxidation and nitridation concentration ratio, with a high density of nitrogen atom diffusion, which improves structural defects, as confirmed by XPS analysis. However, the surplus of nitrogen S1 (50:50) was found to degrade the electrical performance (e.g., $E_H$ of S1 is 49.4% lower than S3). In conclusion, a balanced O₂ and N₂ concentration ratio is necessary to lower defect states, improve leakage current density, and enhance the electrical breakdown field. This optimization is crucial for addressing the challenges in MOS scaling for high-power devices.