Search Results (191)

In this paper, we present a system-level model of a digital multibeam antenna designed for Low Earth Orbit satellite communications operating in the Ka-band. We initially develop a suitable array topology, which is based on a thinned lattice, then adopt it as the foundation for evaluating its performance within a digital beamforming architecture. This architecture is implemented in a system-level simulator to evaluate the performance of the transmitter and receiver chains. This study advances the analysis of the digital antennas by incorporating both the RF front-end and digital sections non-idealities into a digital-twin framework. This approach enhances the designer’s ability to optimize the system with a holistic approach and provides insights into how various impairments affect the transmitter and receiver performance, identifying the subsystems’ parameter limits. To achieve this, we analyze several subsystems’ parameters and impairments, assessing their effects on both the antenna radiation and quality of the transmitted and received signals in a real applicative context. The results of this study reveal the sensitivity of the system to the impairments and suggest strategies to trade them off, emphasizing the importance of selecting appropriate subsystem features to optimize overall system performance. Full article

The implementation of Digital Twins (DTs) in hospitality facilities represents a significant opportunity to optimize front-end services, enhancing guest experience and operational efficiency. This paper proposes an ontology-driven approach for DTs in hotel reception areas, focusing on integrating IoT devices, real-time data processing, and service optimization. By modeling interactions between guests, receptionists, and hotel management systems, DTs enhance resource allocation, predictive maintenance, and customer satisfaction. Simulations and historical data analysis enable forecasting demand fluctuations and optimizing check-in/check-out processes. This research provides a structured framework for DT applications in hospitality, validated through scenario-based simulations, showing significant improvements in check-in time and guest satisfaction. Validation was conducted through scenario-based simulations reflecting real-world operational challenges, such as guest surges, room assignment, and staff workload balancing. Metrics including check-in time, guest satisfaction index, task completion rates, and prediction accuracy were used to evaluate performance. Simulations were grounded in historical hotel data and modeled typical peak-period dynamics to ensure realism. Results demonstrated a 25–35% reduction in check-in time, a 20% improvement in staff efficiency, and significant enhancements in guest satisfaction, underscoring the practical value of the proposed framework in real hospitality settings. Full article

Cardiovascular diseases remain one of the leading causes of mortality worldwide, highlighting the importance of effective monitoring and early diagnosis. While electrocardiography (ECG) is the standard technique for evaluating the heart’s electrical activity and detecting rhythm and conduction abnormalities, it alone is insufficient for identifying certain conditions, such as valvular disorders. Phonocardiography (PCG) allows the recording and analysis of heart sounds and improves the diagnostic accuracy when combined with ECG. In this study, ECG and PCG signals were simultaneously acquired from a resting adult subject using a compact system comprising an analog front-end (model AD8232, manufactured by Analog Devices, Wilmington, MA, USA) for ECG acquisition and a digital stethoscope built around a condenser electret microphone (model HM-9250, manufactured by HMYL, Anqing, China). Both the ECG electrodes and the microphone were positioned on the chest to ensure the spatial alignment of the signals. An adaptive segmentation algorithm was developed to segment PCG and ECG signals based on their morphological and temporal features. This algorithm identifies the onset and peaks of S1 and S2 heart sounds in the PCG and the Q, R, and S waves in the ECG, enabling the extraction of the systolic time intervals such as EMAT, PEP, LVET, and LVST parameters proven useful in the diagnosis and monitoring of cardiovascular diseases. Based on the segmented signals, the measured averages (EMAT = 74.35 ms, PEP = 89.00 ms, LVET = 244.39 ms, LVST = 258.60 ms) were consistent with the reference standards, demonstrating the reliability of the developed method. The proposed algorithm was validated on synchronized ECG and PCG signals from multiple subjects in an open-source dataset (BSSLAB Localized ECG Data). The systolic intervals extracted using the proposed method closely matched the literature values, confirming the robustness across different recording conditions; in detail, the mean Q–S1 interval was 40.45 ms (≈45 ms reference value, mean difference: −4.85 ms, LoA: −3.42 ms and −6.09 ms) and the R–S1 interval was 14.09 ms (≈15 ms reference value, mean difference: −1.2 ms, LoA: −0.55 ms and −1.85 ms). In conclusion, the results demonstrate the potential of the joint ECG and PCG analysis to improve the long-term monitoring of cardiovascular diseases. Full article

This paper proposes a dual-mode CMOS analog front-end (AFE) circuit for short-wave infrared (SWIR) image sensors, which integrates a hybrid readout circuit (ROIC) and a 12-bit two-step single-slope analog-to-digital converter (TS-SS ADC). The ROIC dynamically switches between buffered-direct-injection (BDI) and direct-injection (DI) modes, thus balancing injection efficiency against power consumption. While the DI structure offers simplicity and low power, it suffers from unstable biasing and reduced injection efficiency under high background currents. Conversely, the BDI structure enhances injection efficiency and bias stability via an input buffer but incurs higher power consumption. To address this trade-off, a dual-mode injection architecture with mode-switching transistors is implemented. Mode selection is executed in-pixel via a low-leakage transmission gate and coordinated by the column timing controller, enabling low-current pixels to operate in low-noise BDI mode, whereas high-current pixels revert to the low-power DI mode. The TS-SS ADC employs a four-terminal comparator and dynamic reference voltage compensation to mitigate charge leakage and offset, which improves signal-to-noise ratio (SNR) and linearity. The prototype occupies 2.1 mm × 2.88 mm in a 0.18 µm CMOS process and serves a 64 × 64 array. The AFE achieves a dynamic range of 75.58 dB, noise of 249.42 μV, and 81.04 mW power consumption. Full article

The inherent non-ideal characteristics of circuit components and inter-channel mismatch errors induce nonlinear amplitude and phase distortions in time-interleaved pipelined analog-to-digital converters (TI-pipelined ADCs), significantly degrading system performance. Limited by prior modeling, conventional digital calibration methods only correct partial errors, while machine learning (ML) approaches achieve comprehensive calibration at a high computational cost. This work proposes an ensemble calibration framework that combines polynomial modeling and ML techniques. The ensemble calibration framework employs a two-stage correction: a learned Volterra front-end performs forward mapping to compensate static baseline nonlinear distortions, while a lightweight neural network back-end implements inverse mapping to correct dynamic nonlinear distortions and inter-channel mismatch errors adaptively. Experiments conducted on TI-pipelined ADCs show improvements in both the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR). It is noteworthy that in two ADCs fabricated using 40 nm CMOS technology, the 12-bit, 3000 MS/s silicon-validated four-channel TI-pipelined ADC exhibits SFDR and SNDR improvements from 35.47 dB and 35.35 dB to 79.70 dB and 55.63 dB, respectively, while the 16-bit, 1000 MS/s silicon-validated four-channel TI-pipelined ADC demonstrates an enhancement from 38.62 dB and 40.21 dB to 80.90 dB and 62.43 dB, respectively. Furthermore, a comparison with related studies reveals that our method achieves comprehensive calibration performance for wide-band inputs while substantially reducing computational complexity, requiring only 4.4 K parameters and 8.57 M floating-point operations per second (FLOPs). Full article

Compact, broadband, multi-channel RF chips with low loss and high integration are required for high-performance phased-array systems. Presented in this paper is a four-channel, multifunction RF chip operating in the 5–18 GHz frequency range that integrates broadband phase shifting, amplitude control, power amplification, and switching functions. The chip is designed to have flip-chip bonding and stacked gold bumps to enable the compact 3D integration of the GaAs pHEMT and Si-CMOS. To ensure high-density interconnects with minimal parasitic effects, a fan-in redistribution process is implemented. The RF front-end part of this chip, fabricated through a 0.15 µm GaAs pHEMT process, integrates 6-bit digital phase shifters, 6-bit digital attenuators, low-noise amplifiers (LNAs), power amplifiers (PAs), and single-pole double-throw (SPDT) switches. To enhance multi-channel isolation and reduce crosstalk between RF chips and digital circuits, high isolation techniques, including a ground-coupled shield layer in the fan-in process and on-chip shield cavities, are utilized, which achieve isolation levels greater than 41 dB between adjacent RF channels. The measurement results demonstrate a reception gain of 0 dB with ±0.6 dB flatness, an NF below 11 dB, and transmit gain of more than 10 dB, with a VSWR of below 1.6 over the entire 5–18 GHz frequency band. The 6-bit phase shifter achieves a root mean square (RMS) phase error below 2.5° with an amplitude variation of less than 0.8 dB, while the 6-bit attenuator exhibits an RMS attenuation error of below 0.5 dB and a phase variation of less than 7°. The RF and digital chips are heterogeneously integrated using flip-chip and fan-in technology, resulting in a compact chip size of 6.2 × 6.2 × 0.33 mm³. These results validate that this is a compact, high-performance solution for advanced phased-array radar applications. Full article

In the rapidly advancing digital era, the demand for miniaturized and high-performance electronic devices is increasing, particularly in applications such as wireless communication, unmanned aerial vehicles, and healthcare devices. Radio-frequency microelectromechanical systems (RF MEMS), particularly RF MEMS switches, play a crucial role in enhancing RF performance by providing low-loss, high-isolation switching and precise signal path control in reconfigurable RF front-end systems. Among different configurations, electrothermally actuated bistable lateral RF MEMS switches are preferred for their energy efficiency, requiring power only during transitions. This paper presents a novel approach to improve the RF performance of such a switch through structural modifications and machine learning (ML)-driven optimization. To enable efficient high-frequency operation, the H-clamp structure was re-engineered into various lateral configurations, among which the I-clamp exhibited superior RF characteristics. The proposed I-clamp switch was optimized using an eXtreme Gradient Boost (XGBoost) ML model to predict optimal design parameters while significantly reducing the computational overhead of conventional EM simulations. Activation functions were employed within the ML model to improve the accuracy of predicting optimal design parameters by capturing complex nonlinear relationships. The proposed methodology reduced design time by 87.7%, with the optimized I-clamp switch achieving −0.8 dB insertion loss and −70 dB isolation at 10 GHz. Full article

The transition from 5G to 6G wireless systems introduces new challenges at the physical layer, including the need for higher frequency operations, massive MIMO deployment, advanced beamforming techniques, and sustainable energy harvesting mechanisms. A plethora of feature articles, review and white papers, and roadmaps elaborate on the perspectives and research challenges of wireless systems, in general, including both unified physical and cyber space. Hence, this paper presents a comprehensive review of the technological challenges and recent advancements in wireless communication hardware that underpin the development of next-generation networks, particularly 6G. Emphasizing the physical layer, the study explores critical enabling technologies including beamforming, massive MIMO, reconfigurable intelligent surfaces (RIS), millimeter-wave (mmWave) and terahertz (THz) communications, wireless power transfer, and energy harvesting. These technologies are analyzed in terms of their functional roles, implementation challenges, and integration into future wireless infrastructure. Beyond traditional physical layer components, the paper also discusses the role of reconfigurable RF front-ends, innovative antenna architectures, and user-end devices that contribute to the adaptability and efficiency of emerging communication systems. In addition, the inclusion of application-driven paradigms such as digital twins highlights how new use cases are shaping design requirements and pushing the boundaries of hardware capabilities. By linking foundational physical-layer technologies with evolving application demands, this work provides a holistic perspective aimed at guiding future research directions and informing the design of scalable, energy-efficient, and resilient wireless communication platforms for the Future Internet. Specifically, we first try to identify the demands and, in turn, explore existing or emerging technologies that have the potential to meet these needs. Especially, there will be an extended reference about the state-of-the-art antennas for massive MIMO terrestrial and non-terrestrial networks. Full article

This paper presents hardware-efficient phase demodulation schemes for FPGA-based digital phase-sensitive optical time-domain reflectometry ($\varphi$-OTDR) receivers. We first derive a signal model for the heterodyne $\varphi$-OTDR frontend, then propose and analyze three demodulation methods: (1) a baseband reconstruction approach via zero-IF downconversion, (2) an analytic signal generation technique using the Hilbert transform (HT), and (3) a wavelet transform (WT)-based alternative for analytic signal extraction. Algorithm-hardware co-design implementations are detailed for both RFSoC and conventional FPGA platforms, with resource utilization comparisons. Additionally, we introduce an incremental DC-rejected phase unwrapper (IDRPU) algorithm to jointly address phase unwrapping and DC drift removal, minimizing computational overhead while avoiding numerical overflow. Experiments on simulated and real-world $\varphi$-OTDR data show that the HT method matches the performance of zero-IF demodulation with simpler hardware and lower resource usage, while the WT method offers enhanced robustness against fading noise (3.35–22.47 dB SNR improvement in fading conditions), albeit with slightly ambiguous event boundaries and higher hardware utilization. These findings provide actionable insights for demodulator design in distributed acoustic sensing (DAS) applications and advance the development of single-chip DAS systems. Full article

Advanced multi-channel acoustic emission (AE) monitoring systems often rely on complex and costly architectures, especially those requiring custom FPGA-based hardware. In this work, we present a digital signal processing (DSP)-based approach to high-performance AE acquisition, implemented using a simplified analog front-end (AFE) and a commercially available synchronous data acquisition (DAQ) card (NI USB-6356). This design eliminates the need for specialized FPGA development, improving accessibility and reducing system complexity. A key feature of the system is the replacement of traditional analog filters with a software-defined digital band-pass filtering module implemented in LabVIEW. This allows for real-time or post-processing filtering with adjustable parameters, enhancing flexibility in data analysis. The system supports 8-channel synchronous sampling at 1.25 MS/s, and performance evaluations demonstrate a dynamic range of 79.22 dB and a signal-to-noise ratio (SNR) of 85.39 dB. These results confirm the system’s ability to maintain high fidelity in AE signal acquisition without the need for dedicated hardware filtering or custom DAQ hardware. The proposed method offers a practical and validated alternative for multi-channel AE monitoring, with potential applications in structural health monitoring, materials testing, and other engineering domains. Full article

Deepfake technology uses artificial intelligence to create highly realistic but fake audio, video, or images, often making it difficult to distinguish from real content. Due to its potential use for misinformation, fraud, and identity theft, deepfake technology has gained a bad reputation in the digital world. Recently, many works have reported on the detection of deepfake videos/images. However, few studies have concentrated on developing robust deepfake voice detection systems. Among most existing studies in this field, a deepfake voice detection system commonly requires a large amount of training data and a robust backbone to detect real and logistic attack audio. For acoustic feature extractions, Mel-frequency Filter Bank (MFB)-based approaches are more suitable for extracting speech signals than applying the raw spectrum as input. Recurrent Neural Networks (RNNs) have been successfully applied to Natural Language Processing (NLP), but these backbones suffer from gradient vanishing or explosion while processing long-term sequences. In addition, the cross-dataset evaluation of most deepfake voice recognition systems has weak performance, leading to a system robustness issue. To address these issues, we propose an acoustic feature-fusion method to combine Mel-spectrum and pitch representation based on cross-attention mechanisms. Then, we combine a Transformer encoder with a convolutional neural network block to extract global and local features as a front end. Finally, we connect the back end with one linear layer for classification. We summarized several deepfake voice detectors’ performances on the silence-segment processed ASVspoof 2019 dataset. Our proposed method can achieve an Equal Error Rate (EER) of 26.41%, while most of the existing methods result in EER higher than 30%. We also tested our proposed method on the ASVspoof 2021 dataset, and found that it can achieve an EER as low as 28.52%, while the EER values for existing methods are all higher than 28.9%. Full article

This paper presents a comprehensive review of GaAs HBT-based Doherty power amplifiers (DPAs) targeting 5G New Radio (NR) handset applications. Focusing on the critical challenges of linearity enhancement, back-off efficiency improvement, bandwidth extension under low-voltage (3.4 V) operation, and chip thermal management, the authors analyze state-of-the-art DPAs published in recent years. Key innovations including dynamic power division technique, third order intermodulation (IM3) cancellation technology, and compact output combiners are comparatively studied. Using 5G NR signals, the critical performance of the latest reported PA such as maximum linear power, back-off efficiency, bandwidth, and operating voltage are quantitatively investigated. The measurement results demonstrated that the best performance in recent DPAs achieved high linear power of 31 dBm with 34% PAE and 30 dBm with 31% PAE at the N78 and N77 bands, respectively. The corresponding adjacent channel leakage ratios (ACLRs) were lower than −36.5 dBc without digital pre-distortion (DPD). This review provides a comprehensive understanding of the latest advancements and future directions in highly efficient and linear DPA designs for 5G handset front-end modules. Full article

Edge-computing applications demand ultra-low-power architectures for both feature extraction and classification tasks. In this manuscript, a Keyword Spotting (KWS) system tailored for energy-constrained portable environments is proposed. A 16-channel analog filter bank is employed for audio feature extraction, followed by a digital Gated Recurrent Unit (GRU) classifier. The filter bank is behaviorally modeled, making use of second-order band-pass transfer functions, simulating the analog front-end (AFE) processing. To enable efficient deployment, the GRU classifier is trained using a Learned Step Size (LSQ) and Look-Up Table (LUT)-aware quantization method. The resulting quantized model, with 4-bit weights and 8-bit activation functions (W4A8), achieves 91.35% accuracy across 12 classes, including 10 keywords from the Google Speech Command Dataset v2 (GSCDv2), with less than 1% degradation compared to its full-precision counterpart. The model is estimated to require only 34.8 kB of memory and 62,400 multiply–accumulate (MAC) operations per inference in real-time settings. Furthermore, the robustness of the AFE against noise and analog impairments is evaluated by injecting Gaussian noise and perturbing the filter parameters (center frequency and quality factor) in the test data, respectively. The obtained results confirm a strong classification performance even under degraded circuit-level conditions, supporting the suitability of the proposed system for ultra-low-power, noise-resilient edge applications. Full article

Based on Digital Beamforming (DBF) technology, spaceborne SAR systems can achieve high-resolution and wide-swath (HRWS) imaging. When combined with reflector antennas, the DBF-SCORE (Digital Beamforming-SCan On REceive) system also features light weight and low cost, making it an important choice for spaceborne HRWS SAR. This paper firstly proposes an advanced Full-chain Real-time Internal Calibration (FRIC) scheme, where the calibration path covers the entire receive chain from the antenna feed port to the input port of the Analog-to-Digital Converter (ADC) and achieves high-precision internal calibration concurrently with data acquisition. Secondly, based on the L-band reflector antenna DBF-SCORE system architecture, the design of radio frequency (RF) front end, namely the Transmit-Receive-Calibration Module (TRCM), is carried out. We propose the implementation of azimuth encoding modulation of the calibration signal through periodic switch control within the TRCM. Subsequently, the calibration signal is extracted using waveform diversity technology and its Signal-to-Noise Ratio (SNR) is improved through azimuth coherent integration technology. In addition, a ground verification system is established using the TRCM to evaluate the comprehensive performance of transmitting, receiving, and real-time internal calibration. Experimental results verify the effectiveness of the FRIC scheme and provide valuable insights for future spaceborne DBF SAR systems. Full article

Distortions of electrocardiograms (ECGs) caused by mandatory high-pass and low-pass analog RC filters in ECG devices are always present. The fidelity of the ECG waveform requires limiting the RC cutoff frequencies of the diagnostic (0.05–150 Hz) and monitoring systems (0.5–40 Hz). However, the use of fixed frequency bands is a compromise between enhanced noise immunity and ECG distortions. This study aims to propose active inverse high-pass and low-pass filters which are able to compensate for distortions in digital recordings of RC-filtered ECGs, thereby overcoming the limitations imposed by analog filtering. A new straightforward design of an inverse high-pass filter (IHPF) uses an integrator as the forward-path gain block, with a feedback loop containing an active digital filter equivalent to the analog RC high-pass filter. In contrast, the inverse low-pass filter (ILPF) employs a constant-gain block in the forward path to ensure stability and prevent phase delay, while its feedback path features an active digital counterpart of the RC low-pass filter. Second-order inverse filters are created by cascading two first-order stages. The proposed filters were validated according to essential performance requirements for electrocardiographs. The low-frequency (impulse) responses of IHPFs with cutoff frequencies of 0.05–5 Hz exhibit no overshoot and undershoot by magnitudes of 0.1–25 µV, well within the ±100 µV compliance limit defined for a test rectangular pulse (3 mV, 100 ms). The high-frequency responses of ILPFs with cutoff frequencies of 10–150 Hz present a relative amplitude drop of only 0.2–2.5%, far below the 10% limit for peak amplitude reduction of a triangular pulse (1.5 mV) with 20 ms vs. 200 ms widths. For any of the eight ECG leads (I, II, and V1–V6) available in the standard signal (ANE20000), the IHPF (0.05–5 Hz) presents ST-segment deviations <5 μV (within the ±25 μV limit) and R- and S-peak deviations <±3.5% (within the ±5% limit). The ILPF (10–150 Hz) preserves R- and S-peak amplitudes with deviations less than −1%. Diagnostic-level recovery of ECG waveforms distorted by first- and second-order analog RC filters in ECG devices is possible with the innovative and comprehensive inverse filter design presented in this study. This approach offers a significant advancement in ECG signal processing, effectively restoring essential waveform components even after aggressive, noise-robust analog filtering in ECG acquisition circuits. Although validated for ECG signals, the proposed inverse filters are also applicable to other biosignal front-end circuits employing RC coupling. Full article