Search Results (21)

Flash memory, as the core unit of a compute-in-memory (CIM) array, requires multiple positive and negative (PN) high voltages (HVs) for word lines (WLs) to operate during storage and computation. A traditional WL driver generates these voltages using several charge pumps (CPs), leading to significant area overhead. This paper presents a novel multi-mode CP (MMCP) that generates all required HVs for a CIM array under a single CP, supporting CIM unit operation in programming, readout, and erase modes. Unlike traditional voltage multipliers, the MMCP eliminates the need for multiple CPs, reducing area and pump capacitor usage. Compared to a PN CP that drives a common load, the MMCP can provide multiple PN HVs by using level shifters (LSs) and switches. The MMCP is designed in a 55 nm standard CMOS process with an area of only 0.021 mm². Additionally, this paper proposes global PN HV switches, which can correctly deliver the PN HVs generated by the MMCP from the same port (at different times) to the upper and lower power rails of WL driver circuits. Simulation results show that with a 2.5 V supply, 100 pF load, and 50 $\mathsf{\mu }$A current, the maximum error due to ripple is only 0.28%. Full article

This paper proposes an adaptive acceleration lock compensation technology for phase-locked loops (PLLs) based on a novel dual-mode programmable ring voltage-controlled oscillator (ring-VCO). In addition, a time-to-digital converter (TDC) is designed to accurately quantify the phase difference from the phase frequency detector (PFD) in order to optimize the dead-zone effect while dynamically switching an auxiliary charge pump (CP) module to realize fast phase locking. Furthermore, a TDC-controlled three/five-stage dual-mode adaptively continuously switched VCO is proposed to optimize the phase noise (PN) and power efficiency, leading to an optimal performance tradeoff of the PLL. Based on the 180 nm/1.8 V standard CMOS technology, the complete PLL design and a corresponding simulation analysis are implemented. The results show that, with a 1 GHz reference signal as the input, the output frequency is 50–324 MHz, with a wide tuning range of 260 MHz and a low phase noise of −98.07 dBc/Hz@1 MHz. The key phase-locking time is reduced to 1.11 μs, and the power dissipation is lowered to 1.86 mW with a layout area of 66 μm × 128 μm. A significantly remarkable multiobjective performance tradeoff with topology optimization is realized, which is in contrast to several similar design cases of PLLs. Full article

Among all the functions that electronics currently perform, clock synthesis has a backbone role. Charge pump phase-locked loops (CP-PLL) are widely used to accomplish clock synthesis thanks to their versatility. One of the most critical parts of CP-PLLs is the charge pump, which greatly influences the system’s performance. Even though several high-performance charge pumps have been proposed in the past, with the quick spread of electronics in all the engineering fields, the design of such electronic devices has encountered several additional challenges dictated by external environmental conditions. Examples of these engineering sectors are space, aerospace, industrial, and automotive applications, where the charge pump has to face high environmental temperatures and radiation effects. As a consequence, its design and experimental characterization have to be performed to ensure reliability when operating in harsh conditions. However, to the best of the authors’ knowledge, no works in the literature have ever presented a complete charge pump design and characterization in such harsh environments. Therefore, to fill this gap, this paper presents a charge pump for PLL applications specifically designed to reach operating temperatures up to 200 °C and total ionizing dose levels up to 100 Mrad. All design choices have been experimentally verified and are discussed throughout the paper in detail. With the proposed design, we obtained an output current variation of less than 8% at 200 °C and less than 2.5% at 100 Mrad. As opposed to the CPs that can be found in the literature, these results were measured on silicon. The performed measurements confirm that the current variation at 200 °C is better than that of the state-of-the-art CPs operating at lower temperatures, which, moreover, were only simulated. Full article

A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase the phase detection gain by ~100× compared to the Phase-Frequency Detectors (PFDs) used in conventional PLLs. Using this high detection gain, the noise contribution of the PFD and Charge Pump (CP), reference clock, and dividers on the PLL output is minimized, enabling low output jitter at low power, even when using low-frequency reference clocks. To provide a sufficient frequency locking range, an auxiliary frequency-locked loop (AFLL) is embedded within the INPLL. An integrated Lock Detector (LD) helps detect the INPLL locked state and disables the AFLL to save on power consumption and minimize its impact on the INPLL jitter. The proposed INPLL layout measures 700 µm × 350 µm, consumes 350 µW, and exhibits an integrated phase noise (IPN) of −37 dBc (from 10 kHz to 10 MHz), equivalent to 2.9 ps rms jitter, while keeping the spur level 64 dBc lower, resulting in jitter figure of Merit ($Fo{M}_{jitter}$) ~−236 dB. Full article

This paper proposes a circuit model of a cross-coupled CMOS AC–DC charge pump (XC–CP) operating in the subthreshold region. The aim is to improve the efficiency of designing XC–CPs with a variety of specifications, e.g., input and output voltages and AC input frequency. First, it is shown that the output resistance (Ro) of XC–CP is much higher than those of CPs with single diodes (SD–CP) and ultra-low-power diodes (ULPD–CP) as charge transfer switches (CTSs). Second, the reason behind the above feature of XC–CP, identified by a simple model, is that the gate-to-source voltages of CTS MOSFETs are independent of the output voltage of the CP. Third, the high but finite Ro of XC–CP is explainable with a more accurate model that includes the dependence of the saturation current of MOSFETs operating in the subthreshold region on the drain-to-source voltage, which is a function of the output voltage of CP. The model is in good agreement with measured and simulated results of XC–, SD–, and ULPD–CPs fabricated in a 250 nm CMOS. Full article

This paper presents a novel inductorless dual-mode buck-boost charge pump (CP) based DC-DC converter. The proposed architecture allows the same circuit to accomplish two modes of operation, buck and boost, for degrading or elevating the output voltage, respectively, compared to the input. To achieve each mode, only a switching of the input–output connections is needed without any other modification in the design of the DC-DC converter. The dual-mode configuration aims to merge two different functions into one circuit, minimizing the design time and the area the DC-DC converter occupies on the die. The proposed buck-boost CP has been designed using TSMC 65 nm complementary metal–oxide–semiconductor (CMOS) technology. The functional input voltage range of the CP in boost mode is 1.2 V to 1.8 V and the typical output voltage is 1.8 V. For the buck mode, the input voltage range is 3.2 V to 3.6 V and the output is 1.5 V. For both modes, the output can be easily modified to new values by changing the comparator configuration. Efficiency results are also provided for the two modes. Full article

The phase-locked loop is a technique that has contributed significantly to technological advancements in many applications in the fast-evolving digital era. In this paper, a Phase Locked Loop (PLL) is designed using 90 nm CMOS technology node with 1.8 V supply voltage. It features a PLL design with minimum power consumption of 194.26 µW with better transient analysis and DC analysis in an analog-to-digital environment. The proposed PLL design provides the best solution for many applications where a PLL is required with high performance but has to be accommodated in less area and low power consumption than state-of-the-art methods. This PLL not only works at high speed but also makes whole system work at low power in a very effective manner, which suits the present digital electronics circuits. Full article

A power management unit (PMU) is an essential block for diversified multi-functional low-power Internet of Things (IoT) and biomedical electronics. This paper includes a theoretical analysis of a high current, single-stage ac-dc, reconfigurable, dual output, regulating rectifier consisting of pulse width modulation (PWM) and pulse frequency modulation (PFM). The regulating rectifier provides two independently regulated supply voltages of 1.8 V and 3.3 V from an input ac voltage. The PFM control feedback consists of feedback-driven regulation to adjust the driving frequency of the power transistors through adaptive buffers in the active rectifier. The PWM/PFM mode control provides a feedback loop to adjust the conduction duration accurately and minimize power losses. The design also includes an adiabatic charge pump (CP) to provide a higher voltage level. The adiabatic CP consists of latch-up and power-saving topologies to enhance its power efficiency. Simulation results show that the dual regulating rectifier has 94.3% voltage conversion efficiency with an ac input magnitude of 3.5 Vp. The power conversion efficiency of the regulated 3.3 V output voltage is 82.3%. The adiabatic CP has an overall voltage conversion efficiency (VCE) of 92.9% with a total on-chip capacitance of 60 pF. The circuit was designed using 180 nm CMOS technology. Full article

This paper proposed a 5.42~6.28 GHz type-II phase locked loop (PLL) for the sake of both loop filter switching capability and extensive programmability. An on-chip loop filter is used in conjunction with off-chip one to form a switching filter pair for diverse application scenarios. In order to strike a balance between dead-zone elimination and noise contribution minimization, a 3-bit programmable reset time ranging from 25 ps to 200 ps with a step of 25 ps is brought into PFD (phase frequency detector) design while CP (charge pump) current is programmable from 200 μA to 900 μA with a 100 μA/step digital control. Power management units (PMU) including bandgap and low dropout regulators (LDO) are integrated on-chip with resistor string trimming which effectively counteracts fabrication variations. In addition, a piecewise linear VCO with 3-bit control is designed with a fully digital 6-bit multi-modulus divider (MMD) chain cascaded. The proposed PLL is implemented in a 40-nm bulk CMOS process and the power consumption is 8 mA@1.2 V, in which around 5 mA@1.2 V is consumed by output buffers. The fabricated PLL chip achieves a frequency tuning range of 5.42~6.28 GHz, a phase noise ranging from −107.2~−110.4 dBc/Hz@1 MHz offset from carrier, a reference spur of lower than −70 dBc when on-chip active loop filter bandwidth is set to be around 500 KHz. Its FoM is approximately −176.98~−180.18 dBc/Hz while FoM_T is approximately −180.32~−183.52 dBc/Hz@1 MHz offset from carrier. Its most specifications are comparable to or better than most existing literature. Full article

Recently, with the aim of extending the use of the CP in all those applications where a time-variant signal must be amplified with its DC component above the positive power supply rail, the signal amplification feature of a conventional Dickson charge pump (CP) has been investigated, introducing a small-signal model for each particular condition in which a CP can work. In this paper this idea is further investigated, especially under the slow switching limit (SSL) condition, and experimental validation has been carried out using a 65 nm CMOS technology for four different voltage gain values. Starting from an equivalent model of the CP, the main small- and large-signal parameters are analytically derived and discussed in depth. As a proof of concept, experimental measurements on four CPs with different numbers of stages confirm the validity of this unconventional application and the effectiveness of the CP when used as an amplifier. Full article

This paper proposes a stacked field-effect transistor (FET) single-pole, double-throw (SPDT) RF switch which is capable of multi-standard. Negative voltage generator (NVG), logic controller, level shifter, and RF Switch branches are integrated. A PMOS self-biased strategy is proposed to improve linearity and simplify the design of the logic controller and level shifter. In order to reduce the influence of NVG, a new charge pump (CP) is proposed, and a low pass filter (LPF) is added to stabilize bias voltages. A new layout of the switch FET is proposed to minimize the product of on-state resistance and off-state capacitance (time constant). The RF switch proposed in this paper was implemented in the 0.18 μm silicon on insulator (SOI) process. The measured results show the P1 dB of 40 dBm, and the isolation (ISO) and insert loss (IL) at 1 GHz/5 GHz of 37 dB/22 dB, and 0.36 dB/0.55 dB. The operating frequency range is DC-6 GHz. Supply current is 37uA with the supply voltage of 2.6V. Full article

Nanofluid electrodes with high loading of active solid materials have significant potential as high energy density flow battery electrolytes; however, two key criteria need to be met: they must have a manageable viscosity for pumping and simultaneously exhibit good electrochemical activity. A typical dispersion of nickel hydroxide nanoparticles (~100 nm) is limited to 5–10 wt.% of solids, above which it has a paste-like consistency, incompatible with flow applications. We report on the successful formulation of stable dispersions of a nano-scale nickel hydroxide cathode (β-Ni(OH)₂) with up to 60 wt.% of solids and low viscosity (32 cP at 25 °C), utilizing a surface graft of small organic molecules. The fraction of grafting moiety is less than 3 wt.% of the nanoparticle weight, and its presence is crucial for the colloidal stability and low viscosity of suspensions. Electrochemical testing of the pristine and modified β-Ni(OH)₂ nanoparticles in the form of solid casted electrodes were found to be comparable with the latter exhibiting a maximum discharge capacity of ~237 mAh/g over 50 consecutive charge–discharge cycles, close to the theoretical capacity of 289 mAh/g. Full article

In this paper, we present a successive approximation register (SAR) analog-to-digital converter (ADC) with a charge-pump (CP) phase-locked loop (PLL) and a bootstrapped switch, also called PLL-SAR ADC. To meet system-on-chip (SOC) and industrial requirements, the proposed SAR ADC and the control circuits of electric vehicles must be integrated into a single chip and be fabricated using the TSMC 0.25-μm 1P3M complementary metal oxide semiconductor (CMOS) high-voltage process. It is difficult to implement a high-speed SAR ADC with the TSMC 0.25-μm CMOS high-voltage process because it includes an N-type buried layer, which shorts all p-type metal oxide semiconductor field-effect transistor (PMOSFET) bodies together to withstand high voltages. In the proposed PLL-SAR ADC, two clock signals, an external clock signal and an internal clock signal from the CP-PLL, are provided to guarantee that a correct clock signal is fed. This design improves the robustness of the designed system. A monotonic capacitor-switching procedure is considered to reduce power consumption. Furthermore, a bootstrapped switch was added along with a dummy switch and a dummy transistor to eliminate disturbances in the input voltages and to improve the device’s anti-noise capability. Moreover, a two-stage dynamic comparator was used to prevent kickback noise induced by the parasitic capacitors. The measurements indicate that the signal-to-noise-and-distortion ratio, effective number of bits, power consumption, and chip area are 53.82 dB, 8.65 bits, 1.256 mW, and 1.261 × 0.975 mm², respectively. The FoM is approximately 0.625 pJ/conv-step at 1.256 mW, 8.65 bits, and 5 MS/s. The high sampling rate of 5 MS/s and high accuracy of 8.65 bits are the main advantages of the proposed PLL-SAR ADC. Full article

This paper realized a charge pump phase locked loop (CPPLL) frequency source circuit based on 0.15 μm Win GaAs pHEMT process. In this paper, an improved fully differential edge-triggered frequency discriminator (PFD) and an improved differential structure charge pump (CP) are proposed respectively. In addition, a low noise voltage-controlled oscillator (VCO) and a static 64:1 frequency divider is realized. Finally, the phase locked loop (PLL) is realized by cascading each module. Measurement results show that the output signal frequency of the proposed CPPLL is 3.584 GHz–4.021 GHz, the phase noise at the frequency offset of 1 MHz is −117.82 dBc/Hz, and the maximum output power is 4.34 dBm. The chip area is 2701 μm × 3381 μm, and the power consumption is 181 mw. Full article

This paper presents a prototype of an auto-ranging phase-locked loop (PLL) with low jitter noise over a wide operating frequency range using the multiband programmable voltage-controlled oscillator (VCO) gain stage with automatic band selection. We successfully reduce the VCO gain (Kvco) and retain the desired frequency band. The proposed PLL comprises a prescaler, phase frequency detector (PFD), charge pump (CP), programmable VCO and automatic band selection circuit. The PLL prototype with all subblocks was implemented using the TSMC 0.18 μm 1P6M process. Contrary to conventional PLL architectures, the proposed architecture incorporates a real-time check and automatic band selection circuit in the secondary loop. A high-performance dual-loop PLL wide tuning range was realized using an ASIC digital control circuit. A suitable way to maintain the Kvco low is to use multiple discrete frequency bands to accommodate the required frequency range. To maintain a low Kvco and fast locking, the automatic frequency band selection circuit also has two indigenous, most probable voltage levels. The proposed architecture provides the flexibility of not only band hopping but also band twisting to obtain an optimized Kvco for the desired output range, with the minimum jitter and spurs. The proposed programmable VCO was designed using a voltage-to-current-converter circuit and current DAC followed by a four-stage differential ring oscillator with a cross-coupled pair. The VCO frequency output range is 150–400 MHz, while the input frequency is 25 MHz. A sequential phase detection loop with a negligible dead zone was designed to adjust fine phase errors between the reference and feedback clocks. All circuit blocks of the proposed PLL were simulated using the EDA tool HSPICE and layout generation by Laker. The simulation and measured results of the proposed PLL show high linearity, with a dead zone of less than 10 pV. The differential VCO was used to improve the linearity and phase noise of the PLL. The chip measured results show rms jitter of 19.10 ps. The PLL prototype also has an additional safety feature of a power down mode. The automatic band selection PLL has good immunity for possible frequency drifting due to temperature, process and supply voltage variations. The proposed PLL is designed for −40 to +85 °C, a wide temperature range. Full article