A 5.42~6.28 GHz Type-II PLL with Dead-Zone Programmability and Charge Pump Mismatch Trimming

Abstract

This paper proposed a 5.42~6.28 GHz type-II phase locked loop (PLL) for the sake of both loop filter switching capability and extensive programmability. An on-chip loop filter is used in conjunction with off-chip one to form a switching filter pair for diverse application scenarios. In order to strike a balance between dead-zone elimination and noise contribution minimization, a 3-bit programmable reset time ranging from 25 ps to 200 ps with a step of 25 ps is brought into PFD (phase frequency detector) design while CP (charge pump) current is programmable from 200 μA to 900 μA with a 100 μA/step digital control. Power management units (PMU) including bandgap and low dropout regulators (LDO) are integrated on-chip with resistor string trimming which effectively counteracts fabrication variations. In addition, a piecewise linear VCO with 3-bit control is designed with a fully digital 6-bit multi-modulus divider (MMD) chain cascaded. The proposed PLL is implemented in a 40-nm bulk CMOS process and the power consumption is 8 mA@1.2 V, in which around 5 mA@1.2 V is consumed by output buffers. The fabricated PLL chip achieves a frequency tuning range of 5.42~6.28 GHz, a phase noise ranging from −107.2~−110.4 dBc/Hz@1 MHz offset from carrier, a reference spur of lower than −70 dBc when on-chip active loop filter bandwidth is set to be around 500 KHz. Its FoM is approximately −176.98~−180.18 dBc/Hz while FoM_T is approximately −180.32~−183.52 dBc/Hz@1 MHz offset from carrier. Its most specifications are comparable to or better than most existing literature.

1. Introduction

As a fundamental block in high purity carrier generation and robust signal modulation, PLLs with wide bandwidth, superb phase noise and jitter, low spur and harmonics, fine frequency resolution and fast locking feature are critically needed in wireless communications and radar detections. Although all digital PLLs (ADPLL) are assumed to be process scalable and have an ease of digital calibration [1] while sub-sampling PLLs (SSPLL) is assumed to exhibit an acceptable performance and power tradeoff [2], there is still no universal IC solution to fulfill the aforementioned five requirements concurrently. In short, PLL design is still a case-by-case design, and custom chip solution will be mostly in progress regardless of technology innovation and design technique renovation.

Among various tradeoffs in PLLs, loop bandwidth is usually regarded as both a design priority and a key to strike a balance between phase noise and settling time while programmability in other specifications is also a prerequisite for reconfigurability in PLLs. A low loop bandwidth leads to a refined phase noise and a longer locking time while the reverse is verified via behavioral modeling. Aiming at simultaneous low phase noise and short settling time, a ton of techniques including loop filter array, charge pump array and dual-path PFD are proposed [3,4,5,6]. However, when a large variation range is required in loop bandwidth, none of them work properly and off-chip loop filter is employed all the way to work. Thus, a practical solution to dynamic loop bandwidth still needs a combination of off-chip loop filter and on-chip one with other loop parameters such as PFD reset-time and CP current made programmable.

In order to both improve power efficiency and increase universal adaptability of PLLs, this work adopts a type-II PLL topology with added programmability in PFD/CP/VCO and digital trimming in PMU in order to concurrently boost the phase noise/spur performance and increase the analog accuracy. On-chip active filter is utilized together with off-chip one to accommodate different systematic requirements. In addition, pre-scaler is omitted for lower power consumption and CML-to-TSPC converter is utilized between VCO buffer and MMD chain. The rest of this paper is organized as follows. Section 2 provides the outline of the PLL presented with design details of sub-blocks including PFD/CP/loop filter/VCO/buffer/MMD and etc. Section 3 provides the fabrication and measurement results of the presented PLL. Section 4 contains the conclusion.

2. PLL Designs

A PLL with on-chip active loop filter and off-chip one is presented and illustrated in Figure 1 with PFD, CP, loop filter, VCO, buffer and MMD, which includes a 150MHz reference oscillator input and two differential output ports VOUTP/VOUTN. The loop filter is switchable between off-chip and on-chip mode while other blocks are integrated on-chip. A CML-to-TSPC block is inserted to both drive digital logic and perform differential-to-single conversion. Digital serial-to-parallel interface (SPI) is designed with register banks to facilitate PMU calibration and MASH configuration. An unconditional stable MASH 1-1-1 topology is utilized for fractional division function. In default mode, integer PLL is activated with MASH powered off. PFD discriminates the time difference between divider output and reference. CP translates the digital time difference from PFD into analog signal with the help of loop filter. The analog signal tunes the VCO and output the high frequency output both into test buffer and internal buffer. CML-to-TSPC transforms CML signals into TSPC signals. MMD is programmable to help output the desired output digital signal into PFD.

Figure 1. PLL architecture.

2.1. PFD Topology

The main issue in PFD design is elimination of the dead zone without obvious increase in thermal noise contribution. If the reset time is too short, dead zone emerges. Otherwise, noise contribution attributed to CP rises linearly with respect to reset time, although dead zone vanishes. Thus, a traditional tri-state PFD topology is adopted with a little modification to its reset path as depicted in blue bracket in Figure 2. A 3-bit thermometer coded capacitor array is inserted between inverter chains which leads to 25~200 ps programmable reset time with a step of 25 ps. The thermometer code helps minimize capacitor array size by around 78% compared to what binary code does. (The former capacitor array size is 8 units while the latter one is 36 units.) In addition, inverter and transmission gate sizes are carefully designed in order to guarantee accurate timing edges and subsequently low charge/discharge mismatch across process/voltage/temperature (PVT) variations.

Figure 2. PFD topology.

2.2. CP Topology

Intrinsically, charge pump is a one-bit DAC which translates digital signals at PFD output into analog ones with distortions and interference as low as possible. Thus, four major issues complicate high performance CP realizations: (1) charge/discharge mismatch; (2) charge sharing mismatch; (3) clock feedthrough effect; (4) channel charge injection effect in switch transistors. In order to feedback and calibrate mismatch current in a real-time manner, OPAMPs named OPA1/OPA2/OPA3 are introduced into the charge pump topology as shown in Figure 3. OPA1 is utilized to self-calibrate the mismatch between charging and discharging current while OPA2/OPA3 are used to stabilize the drain voltage of current source and to eliminate potential charge sharing effect. In order to minimize clock feedthrough effect and channel charge injection, complementary switches, dummy cells such as M6/7/12/13/17/18/22/23 are utilized. Rail-to-rail OPAMP topology is selected for OPA1/2/3 designs, which is shown in Figure 4. Post-simulation reveals that PFD/CP can differentiate 10 ps offset between reference clock and divider output signal. The rail-to-rail OPAMP shows a maximum voltage gain larger than 65 dB with a phase margin higher than 45° across all PVT corners, which minimizes the mismatch between charge and discharge currents to an acceptable level.

Figure 3. CP topology.

Figure 4. Rail-to-rail OPAMP schematic.

2.3. Divider Chain Topology

Since typical TSPC divider by two or three is simulated with the help of low threshold voltage deep n-well NMOS and its operation frequency can reach approximately 8 GHz, pure TSPC divide by two or three units is cascaded with a first stage CML-to-TSPC logic converter which comes out as a pure digital MMD as illustrated in Figure 5. The CML-to-TSPC block functions as a differential to single converter and realizes voltage swing transformation. Inverter chains are placed between TSPC blocks both to enhance voltage swing and to sharpen pulse edges. Special care should be taken to guarantee high frequency inverter chain response. A post-simulation reveals that this divider chain can operate well up to 8GHz across all PVT corners.

Figure 5. Divider chain topology.

2.4. VCO Topology

In order to implement a robust VCO, a 3-bit piece wisely linearized VCO topology is designed with power hungry output buffers in Figure 6. A KVCO of 500 MHz/V is iteratively designed with an in-band variation of around 20% while its phase noise is around −107~−112 dBc/Hz@1 MHz offset from carrier. A frequency tuning range of 5.2~6.5 GHz is achieved with eight curves available.

Figure 6. VCO topology.

2.5. PMU Topology

PMU adopts a traditional bandgap and low dropout regulator (LDO) topology as depicted in Figure 7 and Figure 8. PMU works under a 2.5 V power supply while the LDO outputs a stable 2 V power supply. An on-chip 10-bit resistor string trimming is designed with the help of SPI control. The post-simulated bandgap voltage reference is around 1.12 V and its current reference is around 10 μA.

Figure 7. LDO schematic.

Figure 8. Bandgap schematic.

2.6. Loop Filter Topology

A hybrid loop filter with on/off-chip switch capability is proposed in Figure 1 and their low-pass-filter function divides at the frequency of around 500 KHz. The on-chip loop filter utilizes an active-R-C bi-quad topology and achieves a programmable LPF-3 dB corner of 500 KHz~1.2 MHz with a step of 100 KHz while the off-chip one achieves lower than 500 KHz bandwidth with the help of off-chip lumped elements. The OPAMP adopted in the on-chip active loop filter is depicted in Figure 9a while the buffer adopted is shown in Figure 9b. The OPAMP shows a high gain bandwidth product (GBW) and excellent power efficiency while the buffer is a power-efficient one with large drive capability. The utilization of the two blocks not only helps improve on-chip programmability, but also functions when large load capacitance emerges. The transfer functions of the OPAMP and the buffer are depicted below in (1) and (6), respectively.

$$H(s)=\frac{V_{OUT}}{V_{IN}}=\frac{A_{v,1st}\cdot A_{v,3rd}}{(1-j\omega /p_1)\cdot (1-j\omega /p_2)},$$

(1)

$$A_{v,1st}=g_{m,M1/2}\cdot \frac{r_{ds,M1/2}\cdot r_{ds,M3/4}}{r_{ds,M1/2}+r_{ds,M3/4}},$$

(2)

$$A_{v,3rd}=1+\frac{g_{m,M11/12}}{g_{m,M10/9}},$$

(3)

$$p_1\approx -C_{VON2\_DW/VOP2\_DW}/\frac{2r_{ds,M1/2}\cdot r_{ds,M3/4}}{r_{ds,M1/2}+r_{ds,M3/4}},$$

(4)

$$p_2\approx -C_L/2\cdot g_{m,M10},$$

(5)

$$V_{out}/V_{in}=g_{m1}{R}_1/(1+g_{m1}{R}_1).$$

(6)

Figure 9. OPAMP and buffer in active loop filter. (a) OPAMP schematic; (b) buffer schematic.

3. Measurement Results

The PLL is fabricated in a 40-nm bulk CMOS technology and its photograph is given in Figure 10. The VCO frequency ranges from 5.42 to 6.28 GHz with its K_VCO variation of less than 20% according to Figure 11. The PLL consumes 8 mA@1.2 V while around 5 mA@1.2 V is consumed by output buffers. The measured phase noise is −107.2~−110.4 dBc/Hz@1MHz offset from in-band carrier according to Figure 12, the measured reference spur is lower than −70 dBc when PLL loop bandwidth is set to be around 100 KHz according to Figure 13. FoM is around −176.98~−180.18 dBc/Hz while FoM_T is around −180.32~−183.52 dBc/Hz@1 MHz offset from in-band carrier. Although the phase noise of the PLL chip is somewhat normal on average compared with previous reports, the overall FoM and FoM_T outperforms previous reports while a small batch test with more than 10 samples validates the practicality. In conclusion, the PLL chip is an excellent solution with all specifications taken into account as Table 1.

Figure 10. PLL chip: (a) layout photograph; (b) chip micro-photograph; (c) PCB substrate.

Figure 11. Measured VCO frequency tuning curves.

Figure 12. Measured phase noise of the PLL at different frequency locked.

Figure 13. Measured spur of the PLL at 5.642 GHz.

Table 1. Performance specification comparison.

Ref.	[3] JSSC 2010	[4] MWCL 2013	[5] TMTT 2009	[6] MWCL 2021	This Work
Process	180-nm CMOS	130-nm CMOS	90-nm CMOS	65-nm CMOS	40-nm CMOS
Architect	CP array	CP array	Dual-path	LF array	Programmable PFD+CP array+ LF switch
Freq. (GHz)	5.27~5.6	5.18~5.32 5.74~5.82	3.8~5.15	5.26~5.98	5.42~6.28
Ref. (MHz)	10	20	<−70	10	120
Loop BW (KHz)	40	280	30	500 /1000	100
Ref. Spurs (dBc)	<−70	<−63	<−70	<−59	<−70
PN@1MHz(dBc/Hz)	−114	−102	−115	−95~−102	−107.2~−110.4
Chip Size (mm2)	1.61	0.76	1.5	1	0.83
Pdc (mW)	19.8	28.8	11	21.24	3.6/9.6 *
FoM (dBc/Hz)	−175.73	−161.81~−162.64	−177.61	−163.73~−170.73	−176.98~−180.18 −181.24~−184.44 *
FoMT (dBc/Hz)	−171.39	−150.33~ −151.16	−187.19	−165.89~−172.89	−180.32~−183.52 −184.58~−187.78

"*" means excluding testing buffers.

4. Conclusions

This paper presented a type-II PLL with full programmability in PFD reset-time, CP output current, on-chip/off-chip loop filter and VCO frequency curves. In addition, bandgap current mismatch trimming is incorporated into PMU. In addition, fully digital divider chain with MASH 1-1-1 is incorporated to both improve the frequency resolution with low-bit dither and improve power efficiency. From the measurement results, the fabricated chip demonstrates an overall superior performance in FoM and FoM_T while the small batch test validates its practicality. In short, the PLL chip solution proposed a flexible design concept for all readers.